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https://github.com/edk2-porting/linux-next.git
synced 2024-11-19 16:14:13 +08:00
Merge branch 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev
* 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev: ata_piix: The Sony TZ90 needs the cable type hardcoding ata_piix: ICH7 does not support correct MWDMA timings Avoid world-writable sysfs files in libata driver. libata: fix suspend/resume for ATA SEMB devices libata: clear ering on resume pata_pdc202xx_old: fix UDMA33 handling sata_mv: use new sata phy register settings for new devices libata: fix attach error handling
This commit is contained in:
Linus Torvalds
commit
7b5ca22643
@ -72,6 +72,7 @@
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* ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
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* and must be dword aligned
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* ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
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* ICH7 errata #16 - MWDMA1 timings are incorrect
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*
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* Should have been BIOS fixed:
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* 450NX: errata #19 - DMA hangs on old 450NX
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@ -94,7 +95,7 @@
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#include <linux/dmi.h>
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#define DRV_NAME "ata_piix"
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#define DRV_VERSION "2.12"
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#define DRV_VERSION "2.13"
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enum {
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PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
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@ -136,6 +137,7 @@ enum piix_controller_ids {
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ich_pata_33, /* ICH up to UDMA 33 only */
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ich_pata_66, /* ICH up to 66 Mhz */
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ich_pata_100, /* ICH up to UDMA 100 */
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ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
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ich5_sata,
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ich6_sata,
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ich6m_sata,
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@ -216,8 +218,8 @@ static const struct pci_device_id piix_pci_tbl[] = {
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/* ICH6 (and 6) (i915) UDMA 100 */
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{ 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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/* ICH7/7-R (i945, i975) UDMA 100*/
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{ 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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{ 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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{ 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
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{ 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
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/* ICH8 Mobile PATA Controller */
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{ 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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@ -487,6 +489,15 @@ static struct ata_port_info piix_port_info[] = {
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.port_ops = &ich_pata_ops,
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},
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[ich_pata_100_nomwdma1] =
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{
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.flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2_ONLY,
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.udma_mask = ATA_UDMA5,
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.port_ops = &ich_pata_ops,
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},
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[ich5_sata] =
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{
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.flags = PIIX_SATA_FLAGS,
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@ -594,6 +605,7 @@ static const struct ich_laptop ich_laptop[] = {
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{ 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
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{ 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
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{ 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
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{ 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
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/* end marker */
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{ 0, }
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};
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@ -4091,7 +4091,9 @@ int ata_dev_revalidate(struct ata_device *dev, unsigned int new_class,
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/* fail early if !ATA && !ATAPI to avoid issuing [P]IDENTIFY to PMP */
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if (ata_class_enabled(new_class) &&
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new_class != ATA_DEV_ATA && new_class != ATA_DEV_ATAPI) {
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new_class != ATA_DEV_ATA &&
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new_class != ATA_DEV_ATAPI &&
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new_class != ATA_DEV_SEMB) {
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ata_dev_printk(dev, KERN_INFO, "class mismatch %u != %u\n",
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dev->class, new_class);
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rc = -ENODEV;
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@ -2783,6 +2783,12 @@ static int ata_eh_revalidate_and_attach(struct ata_link *link,
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} else if (dev->class == ATA_DEV_UNKNOWN &&
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ehc->tries[dev->devno] &&
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ata_class_enabled(ehc->classes[dev->devno])) {
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/* Temporarily set dev->class, it will be
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* permanently set once all configurations are
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* complete. This is necessary because new
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* device configuration is done in two
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* separate loops.
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*/
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dev->class = ehc->classes[dev->devno];
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if (dev->class == ATA_DEV_PMP)
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@ -2790,6 +2796,11 @@ static int ata_eh_revalidate_and_attach(struct ata_link *link,
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else
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rc = ata_dev_read_id(dev, &dev->class,
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readid_flags, dev->id);
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/* read_id might have changed class, store and reset */
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ehc->classes[dev->devno] = dev->class;
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dev->class = ATA_DEV_UNKNOWN;
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switch (rc) {
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case 0:
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/* clear error info accumulated during probe */
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@ -2799,13 +2810,11 @@ static int ata_eh_revalidate_and_attach(struct ata_link *link,
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case -ENOENT:
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/* IDENTIFY was issued to non-existent
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* device. No need to reset. Just
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* thaw and kill the device.
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* thaw and ignore the device.
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*/
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ata_eh_thaw_port(ap);
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dev->class = ATA_DEV_UNKNOWN;
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break;
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default:
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dev->class = ATA_DEV_UNKNOWN;
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goto err;
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}
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}
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@ -2826,11 +2835,15 @@ static int ata_eh_revalidate_and_attach(struct ata_link *link,
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dev->class == ATA_DEV_PMP)
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continue;
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dev->class = ehc->classes[dev->devno];
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ehc->i.flags |= ATA_EHI_PRINTINFO;
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rc = ata_dev_configure(dev);
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ehc->i.flags &= ~ATA_EHI_PRINTINFO;
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if (rc)
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if (rc) {
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dev->class = ATA_DEV_UNKNOWN;
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goto err;
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}
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spin_lock_irqsave(ap->lock, flags);
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ap->pflags |= ATA_PFLAG_SCSI_HOTPLUG;
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@ -3494,6 +3507,8 @@ static void ata_eh_handle_port_suspend(struct ata_port *ap)
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*/
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static void ata_eh_handle_port_resume(struct ata_port *ap)
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{
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struct ata_link *link;
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struct ata_device *dev;
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unsigned long flags;
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int rc = 0;
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@ -3508,6 +3523,17 @@ static void ata_eh_handle_port_resume(struct ata_port *ap)
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WARN_ON(!(ap->pflags & ATA_PFLAG_SUSPENDED));
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/*
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* Error timestamps are in jiffies which doesn't run while
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* suspended and PHY events during resume isn't too uncommon.
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* When the two are combined, it can lead to unnecessary speed
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* downs if the machine is suspended and resumed repeatedly.
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* Clear error history.
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*/
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ata_for_each_link(link, ap, HOST_FIRST)
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ata_for_each_dev(dev, link, ALL)
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ata_ering_clear(&dev->ering);
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ata_acpi_set_state(ap, PMSG_ON);
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if (ap->ops->port_resume)
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@ -313,7 +313,7 @@ ata_scsi_em_message_show(struct device *dev, struct device_attribute *attr,
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return ap->ops->em_show(ap, buf);
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return -EINVAL;
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}
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DEVICE_ATTR(em_message, S_IRUGO | S_IWUGO,
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DEVICE_ATTR(em_message, S_IRUGO | S_IWUSR,
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ata_scsi_em_message_show, ata_scsi_em_message_store);
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EXPORT_SYMBOL_GPL(dev_attr_em_message);
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@ -366,7 +366,7 @@ ata_scsi_activity_store(struct device *dev, struct device_attribute *attr,
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}
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return -EINVAL;
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}
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DEVICE_ATTR(sw_activity, S_IWUGO | S_IRUGO, ata_scsi_activity_show,
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DEVICE_ATTR(sw_activity, S_IWUSR | S_IRUGO, ata_scsi_activity_show,
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ata_scsi_activity_store);
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EXPORT_SYMBOL_GPL(dev_attr_sw_activity);
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@ -2,7 +2,7 @@
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* pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
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* (C) 2005 Red Hat Inc
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* Alan Cox <alan@lxorguk.ukuu.org.uk>
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* (C) 2007 Bartlomiej Zolnierkiewicz
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* (C) 2007,2009 Bartlomiej Zolnierkiewicz
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*
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* Based in part on linux/drivers/ide/pci/pdc202xx_old.c
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*
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@ -158,7 +158,7 @@ static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
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u32 len;
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/* Check we keep host level locking here */
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if (adev->dma_mode >= XFER_UDMA_2)
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if (adev->dma_mode > XFER_UDMA_2)
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iowrite8(ioread8(clock) | sel66, clock);
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else
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iowrite8(ioread8(clock) & ~sel66, clock);
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@ -212,7 +212,7 @@ static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
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iowrite8(ioread8(clock) & ~sel66, clock);
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}
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/* Flip back to 33Mhz for PIO */
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if (adev->dma_mode >= XFER_UDMA_2)
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if (adev->dma_mode > XFER_UDMA_2)
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iowrite8(ioread8(clock) & ~sel66, clock);
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ata_bmdma_stop(qc);
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pdc202xx_set_piomode(ap, adev);
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@ -293,6 +293,10 @@ enum {
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FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
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FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
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PHY_MODE9_GEN2 = 0x398,
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PHY_MODE9_GEN1 = 0x39c,
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PHYCFG_OFS = 0x3a0, /* only in 65n devices */
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MV5_PHY_MODE = 0x74,
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MV5_LTMODE = 0x30,
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MV5_PHY_CTL = 0x0C,
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@ -609,6 +613,8 @@ static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
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static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
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void __iomem *mmio);
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static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
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static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
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void __iomem *mmio, unsigned int port);
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static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
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static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
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unsigned int port_no);
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@ -807,6 +813,14 @@ static const struct mv_hw_ops mv_soc_ops = {
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.reset_bus = mv_soc_reset_bus,
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};
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static const struct mv_hw_ops mv_soc_65n_ops = {
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.phy_errata = mv_soc_65n_phy_errata,
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.enable_leds = mv_soc_enable_leds,
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.reset_hc = mv_soc_reset_hc,
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.reset_flash = mv_soc_reset_flash,
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.reset_bus = mv_soc_reset_bus,
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};
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/*
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* Functions
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*/
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@ -3397,6 +3411,53 @@ static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
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return;
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}
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static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
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void __iomem *mmio, unsigned int port)
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{
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void __iomem *port_mmio = mv_port_base(mmio, port);
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u32 reg;
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reg = readl(port_mmio + PHY_MODE3);
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reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
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reg |= (0x1 << 27);
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reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
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reg |= (0x1 << 29);
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writel(reg, port_mmio + PHY_MODE3);
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reg = readl(port_mmio + PHY_MODE4);
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reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
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reg |= (0x1 << 16);
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writel(reg, port_mmio + PHY_MODE4);
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reg = readl(port_mmio + PHY_MODE9_GEN2);
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reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
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reg |= 0x8;
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reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
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writel(reg, port_mmio + PHY_MODE9_GEN2);
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reg = readl(port_mmio + PHY_MODE9_GEN1);
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reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
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reg |= 0x8;
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reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
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writel(reg, port_mmio + PHY_MODE9_GEN1);
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}
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/**
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* soc_is_65 - check if the soc is 65 nano device
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*
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* Detect the type of the SoC, this is done by reading the PHYCFG_OFS
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* register, this register should contain non-zero value and it exists only
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* in the 65 nano devices, when reading it from older devices we get 0.
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*/
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static bool soc_is_65n(struct mv_host_priv *hpriv)
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{
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void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
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if (readl(port0_mmio + PHYCFG_OFS))
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return true;
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return false;
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}
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static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
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{
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u32 ifcfg = readl(port_mmio + SATA_IFCFG);
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@ -3737,6 +3798,9 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
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}
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break;
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case chip_soc:
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if (soc_is_65n(hpriv))
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hpriv->ops = &mv_soc_65n_ops;
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else
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hpriv->ops = &mv_soc_ops;
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hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
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MV_HP_ERRATA_60X1C0;
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@ -3800,6 +3864,7 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx)
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n_hc = mv_get_hc_count(host->ports[0]->flags);
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for (port = 0; port < host->n_ports; port++)
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if (hpriv->ops->read_preamp)
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hpriv->ops->read_preamp(hpriv, port, mmio);
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rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
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