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irqchip/gic-v3: Refactor the arm64 specific parts
This patch moves the GICv3 system register access helpers to arch/arm64/. Their 32bit counterparts will need to use mrc/mcr accesses instead of mrs_s/msr_s. [maz: fixed conflict with Cavium erratum handling] Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Jean-Philippe Brucker
Marc Zyngier
parent
ee5f7d6462
commit
7936e914f7
162
arch/arm64/include/asm/arch_gicv3.h
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162
arch/arm64/include/asm/arch_gicv3.h
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@ -0,0 +1,162 @@
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/*
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* arch/arm64/include/asm/arch_gicv3.h
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*
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* Copyright (C) 2015 ARM Ltd.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_ARCH_GICV3_H
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#define __ASM_ARCH_GICV3_H
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#include <asm/sysreg.h>
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#define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
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#define ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
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#define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
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#define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
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#define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
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#define ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
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#define ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
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#define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
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#define ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
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/*
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* System register definitions
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*/
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#define ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
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#define ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
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#define ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
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#define ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
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#define ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
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#define ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5)
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#define ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
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#define __LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
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#define __LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
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#define ICH_LR0_EL2 __LR0_EL2(0)
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#define ICH_LR1_EL2 __LR0_EL2(1)
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#define ICH_LR2_EL2 __LR0_EL2(2)
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#define ICH_LR3_EL2 __LR0_EL2(3)
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#define ICH_LR4_EL2 __LR0_EL2(4)
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#define ICH_LR5_EL2 __LR0_EL2(5)
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#define ICH_LR6_EL2 __LR0_EL2(6)
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#define ICH_LR7_EL2 __LR0_EL2(7)
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#define ICH_LR8_EL2 __LR8_EL2(0)
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#define ICH_LR9_EL2 __LR8_EL2(1)
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#define ICH_LR10_EL2 __LR8_EL2(2)
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#define ICH_LR11_EL2 __LR8_EL2(3)
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#define ICH_LR12_EL2 __LR8_EL2(4)
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#define ICH_LR13_EL2 __LR8_EL2(5)
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#define ICH_LR14_EL2 __LR8_EL2(6)
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#define ICH_LR15_EL2 __LR8_EL2(7)
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#define __AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
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#define ICH_AP0R0_EL2 __AP0Rx_EL2(0)
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#define ICH_AP0R1_EL2 __AP0Rx_EL2(1)
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#define ICH_AP0R2_EL2 __AP0Rx_EL2(2)
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#define ICH_AP0R3_EL2 __AP0Rx_EL2(3)
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#define __AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
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#define ICH_AP1R0_EL2 __AP1Rx_EL2(0)
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#define ICH_AP1R1_EL2 __AP1Rx_EL2(1)
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#define ICH_AP1R2_EL2 __AP1Rx_EL2(2)
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#define ICH_AP1R3_EL2 __AP1Rx_EL2(3)
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#ifndef __ASSEMBLY__
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#include <linux/stringify.h>
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/* Low level accessors */
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static inline void gic_write_eoir(u64 irq)
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{
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asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq));
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isb();
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}
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static inline void gic_write_dir(u64 irq)
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{
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asm volatile("msr_s " __stringify(ICC_DIR_EL1) ", %0" : : "r" (irq));
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isb();
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}
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static inline u64 gic_read_iar_common(void)
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{
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u64 irqstat;
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asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
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return irqstat;
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}
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/*
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* Cavium ThunderX erratum 23154
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*
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* The gicv3 of ThunderX requires a modified version for reading the
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* IAR status to ensure data synchronization (access to icc_iar1_el1
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* is not sync'ed before and after).
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*/
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static inline u64 gic_read_iar_cavium_thunderx(void)
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{
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u64 irqstat;
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asm volatile(
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"nop;nop;nop;nop\n\t"
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"nop;nop;nop;nop\n\t"
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"mrs_s %0, " __stringify(ICC_IAR1_EL1) "\n\t"
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"nop;nop;nop;nop"
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: "=r" (irqstat));
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mb();
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return irqstat;
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}
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static inline void gic_write_pmr(u64 val)
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{
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asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val));
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}
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static inline void gic_write_ctlr(u64 val)
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{
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asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val));
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isb();
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}
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static inline void gic_write_grpen1(u64 val)
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{
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asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val));
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isb();
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}
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static inline void gic_write_sgi1r(u64 val)
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{
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asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
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}
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static inline u64 gic_read_sre(void)
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{
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u64 val;
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asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
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return val;
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}
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static inline void gic_write_sre(u64 val)
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{
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asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));
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isb();
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARCH_GICV3_H */
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@ -108,37 +108,7 @@ static void gic_redist_wait_for_rwp(void)
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gic_do_wait_for_rwp(gic_data_rdist_rd_base());
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}
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/* Low level accessors */
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static u64 gic_read_iar_common(void)
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{
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u64 irqstat;
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asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
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return irqstat;
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}
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/*
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* Cavium ThunderX erratum 23154
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*
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* The gicv3 of ThunderX requires a modified version for reading the
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* IAR status to ensure data synchronization (access to icc_iar1_el1
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* is not sync'ed before and after).
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*/
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static u64 gic_read_iar_cavium_thunderx(void)
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{
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u64 irqstat;
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asm volatile(
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"nop;nop;nop;nop\n\t"
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"nop;nop;nop;nop\n\t"
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"mrs_s %0, " __stringify(ICC_IAR1_EL1) "\n\t"
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"nop;nop;nop;nop"
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: "=r" (irqstat));
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mb();
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return irqstat;
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}
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#ifdef CONFIG_ARM64
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static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx);
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static u64 __maybe_unused gic_read_iar(void)
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@ -148,28 +118,7 @@ static u64 __maybe_unused gic_read_iar(void)
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else
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return gic_read_iar_common();
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}
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static void __maybe_unused gic_write_pmr(u64 val)
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{
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asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val));
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}
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static void __maybe_unused gic_write_ctlr(u64 val)
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{
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asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val));
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isb();
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}
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static void __maybe_unused gic_write_grpen1(u64 val)
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{
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asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val));
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isb();
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}
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static void __maybe_unused gic_write_sgi1r(u64 val)
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{
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asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
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}
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#endif
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static void gic_enable_redist(bool enable)
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{
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@ -856,8 +805,10 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
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static void gicv3_enable_quirks(void)
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{
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#ifdef CONFIG_ARM64
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if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154))
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static_branch_enable(&is_cavium_thunderx);
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#endif
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}
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static int __init gic_of_init(struct device_node *node, struct device_node *parent)
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@ -18,8 +18,6 @@
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#ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H
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#define __LINUX_IRQCHIP_ARM_GIC_V3_H
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#include <asm/sysreg.h>
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/*
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* Distributor registers. We assume we're running non-secure, with ARE
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* being set. Secure-only and non-ARE registers are not described.
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@ -293,19 +291,8 @@
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#define ICH_VMCR_PMR_SHIFT 24
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#define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
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#define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
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#define ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
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#define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
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#define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
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#define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
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#define ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
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#define ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
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#define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
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#define ICC_IAR1_EL1_SPURIOUS 0x3ff
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#define ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
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#define ICC_SRE_EL2_SRE (1 << 0)
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#define ICC_SRE_EL2_ENABLE (1 << 3)
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@ -321,54 +308,10 @@
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#define ICC_SGI1R_AFFINITY_3_SHIFT 48
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#define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT)
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/*
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* System register definitions
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*/
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#define ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
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#define ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
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#define ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
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#define ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
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#define ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
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#define ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5)
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#define ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
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#define __LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
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#define __LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
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#define ICH_LR0_EL2 __LR0_EL2(0)
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#define ICH_LR1_EL2 __LR0_EL2(1)
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#define ICH_LR2_EL2 __LR0_EL2(2)
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#define ICH_LR3_EL2 __LR0_EL2(3)
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#define ICH_LR4_EL2 __LR0_EL2(4)
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#define ICH_LR5_EL2 __LR0_EL2(5)
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#define ICH_LR6_EL2 __LR0_EL2(6)
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#define ICH_LR7_EL2 __LR0_EL2(7)
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#define ICH_LR8_EL2 __LR8_EL2(0)
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#define ICH_LR9_EL2 __LR8_EL2(1)
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#define ICH_LR10_EL2 __LR8_EL2(2)
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#define ICH_LR11_EL2 __LR8_EL2(3)
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#define ICH_LR12_EL2 __LR8_EL2(4)
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#define ICH_LR13_EL2 __LR8_EL2(5)
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#define ICH_LR14_EL2 __LR8_EL2(6)
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#define ICH_LR15_EL2 __LR8_EL2(7)
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#define __AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
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#define ICH_AP0R0_EL2 __AP0Rx_EL2(0)
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#define ICH_AP0R1_EL2 __AP0Rx_EL2(1)
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#define ICH_AP0R2_EL2 __AP0Rx_EL2(2)
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#define ICH_AP0R3_EL2 __AP0Rx_EL2(3)
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#define __AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
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#define ICH_AP1R0_EL2 __AP1Rx_EL2(0)
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#define ICH_AP1R1_EL2 __AP1Rx_EL2(1)
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#define ICH_AP1R2_EL2 __AP1Rx_EL2(2)
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#define ICH_AP1R3_EL2 __AP1Rx_EL2(3)
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#include <asm/arch_gicv3.h>
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#ifndef __ASSEMBLY__
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#include <linux/stringify.h>
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#include <asm/msi.h>
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/*
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* We need a value to serve as a irq-type for LPIs. Choose one that will
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* hopefully pique the interest of the reviewer.
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@ -386,39 +329,26 @@ struct rdists {
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u64 flags;
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};
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static inline void gic_write_eoir(u64 irq)
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{
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asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq));
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isb();
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}
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static inline void gic_write_dir(u64 irq)
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{
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asm volatile("msr_s " __stringify(ICC_DIR_EL1) ", %0" : : "r" (irq));
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isb();
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}
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static inline bool gic_enable_sre(void)
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{
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u64 val;
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asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
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if (val & ICC_SRE_EL1_SRE)
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return true;
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val |= ICC_SRE_EL1_SRE;
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asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));
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isb();
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asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
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return !!(val & ICC_SRE_EL1_SRE);
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}
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struct irq_domain;
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int its_cpu_init(void);
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int its_init(struct device_node *node, struct rdists *rdists,
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struct irq_domain *domain);
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static inline bool gic_enable_sre(void)
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{
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u32 val;
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val = gic_read_sre();
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if (val & ICC_SRE_EL1_SRE)
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return true;
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val |= ICC_SRE_EL1_SRE;
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gic_write_sre(val);
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val = gic_read_sre();
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return !!(val & ICC_SRE_EL1_SRE);
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}
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#endif
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#endif
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