mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-15 08:44:14 +08:00
irqchip: crossbar: Convert dra7 crossbar to stacked domains
Support for the TI crossbar used on the DRA7 family of chips is implemented as an ugly hack on the side of the GIC. Converting it to stacked domains makes it slightly more palatable, as it results in a cleanup. Unfortunately, as the DT bindings failed to acknowledge the fact that this is actually yet another interrupt controller (the third, actually), we have yet another breakage. Oh well. Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1426088629-15377-3-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Marc Zyngier
Jason Cooper
parent
08b55e2a92
commit
783d31863f
@ -454,7 +454,6 @@
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mcp_rtc: rtc@6f {
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compatible = "microchip,mcp7941x";
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reg = <0x6f>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_LOW>; /* IRQ_SYS_1N */
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pinctrl-names = "default";
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@ -477,7 +476,7 @@
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&uart3 {
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status = "okay";
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interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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<&dra7_pmx_core 0x248>;
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pinctrl-names = "default";
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@ -446,7 +446,7 @@
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
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interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
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<&dra7_pmx_core 0x3e0>;
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};
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@ -13,14 +13,13 @@
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#include "skeleton.dtsi"
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#define MAX_SOURCES 400
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#define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ti,dra7xx";
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interrupt-parent = <&gic>;
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interrupt-parent = <&crossbar_mpu>;
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aliases {
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i2c0 = &i2c1;
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@ -50,18 +49,19 @@
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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interrupt-parent = <&gic>;
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};
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gic: interrupt-controller@48211000 {
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compatible = "arm,cortex-a15-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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arm,routable-irqs = <192>;
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reg = <0x48211000 0x1000>,
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<0x48212000 0x1000>,
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<0x48214000 0x2000>,
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<0x48216000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-parent = <&gic>;
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};
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/*
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@ -91,8 +91,8 @@
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ti,hwmods = "l3_main_1", "l3_main_2";
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reg = <0x44000000 0x1000000>,
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<0x45000000 0x1000>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
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interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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prm: prm@4ae06000 {
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compatible = "ti,dra7-prm";
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@ -344,7 +344,7 @@
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uart1: serial@4806a000 {
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compatible = "ti,omap4-uart";
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reg = <0x4806a000 0x100>;
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interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart1";
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clock-frequency = <48000000>;
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status = "disabled";
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@ -355,7 +355,7 @@
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uart2: serial@4806c000 {
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compatible = "ti,omap4-uart";
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reg = <0x4806c000 0x100>;
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interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart2";
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clock-frequency = <48000000>;
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status = "disabled";
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@ -366,7 +366,7 @@
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uart3: serial@48020000 {
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compatible = "ti,omap4-uart";
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reg = <0x48020000 0x100>;
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interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart3";
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clock-frequency = <48000000>;
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status = "disabled";
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@ -377,7 +377,7 @@
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uart4: serial@4806e000 {
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compatible = "ti,omap4-uart";
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reg = <0x4806e000 0x100>;
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interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart4";
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clock-frequency = <48000000>;
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status = "disabled";
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@ -388,7 +388,7 @@
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uart5: serial@48066000 {
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compatible = "ti,omap4-uart";
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reg = <0x48066000 0x100>;
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interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart5";
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clock-frequency = <48000000>;
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status = "disabled";
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@ -399,7 +399,7 @@
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uart6: serial@48068000 {
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compatible = "ti,omap4-uart";
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reg = <0x48068000 0x100>;
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interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart6";
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clock-frequency = <48000000>;
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status = "disabled";
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@ -410,7 +410,7 @@
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uart7: serial@48420000 {
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compatible = "ti,omap4-uart";
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reg = <0x48420000 0x100>;
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interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart7";
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clock-frequency = <48000000>;
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status = "disabled";
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@ -419,7 +419,7 @@
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uart8: serial@48422000 {
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compatible = "ti,omap4-uart";
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reg = <0x48422000 0x100>;
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interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart8";
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clock-frequency = <48000000>;
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status = "disabled";
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@ -428,7 +428,7 @@
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uart9: serial@48424000 {
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compatible = "ti,omap4-uart";
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reg = <0x48424000 0x100>;
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interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart9";
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clock-frequency = <48000000>;
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status = "disabled";
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@ -437,7 +437,7 @@
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uart10: serial@4ae2b000 {
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compatible = "ti,omap4-uart";
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reg = <0x4ae2b000 0x100>;
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interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart10";
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clock-frequency = <48000000>;
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status = "disabled";
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@ -1337,9 +1337,12 @@
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status = "disabled";
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};
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crossbar_mpu: crossbar@4a020000 {
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crossbar_mpu: crossbar@4a002a48 {
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compatible = "ti,irq-crossbar";
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reg = <0x4a002a48 0x130>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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#interrupt-cells = <3>;
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ti,max-irqs = <160>;
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ti,max-crossbar-sources = <MAX_SOURCES>;
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ti,reg-size = <2>;
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@ -160,7 +160,6 @@
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pinctrl-0 = <&tps65917_pins_default>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
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interrupt-parent = <&gic>;
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interrupt-controller;
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#interrupt-cells = <2>;
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@ -25,6 +25,7 @@
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pmu {
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compatible = "arm,cortex-a15-pmu";
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interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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@ -41,8 +41,9 @@
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pmu {
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compatible = "arm,cortex-a15-pmu";
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interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
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};
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ocp {
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@ -22,7 +22,6 @@
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#include <linux/of_platform.h>
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#include <linux/export.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/irqchip/irq-crossbar.h>
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#include <linux/of_address.h>
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#include <linux/reboot.h>
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#include <linux/genalloc.h>
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@ -292,8 +291,5 @@ void __init omap_gic_of_init(void)
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skip_errata_init:
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omap_wakeupgen_init();
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#ifdef CONFIG_IRQ_CROSSBAR
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irqcrossbar_init();
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#endif
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irqchip_init();
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}
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@ -11,11 +11,12 @@
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/slab.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/irqchip/irq-crossbar.h>
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#include "irqchip.h"
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#define IRQ_FREE -1
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#define IRQ_RESERVED -2
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@ -24,6 +25,7 @@
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/**
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* struct crossbar_device - crossbar device description
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* @lock: spinlock serializing access to @irq_map
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* @int_max: maximum number of supported interrupts
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* @safe_map: safe default value to initialize the crossbar
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* @max_crossbar_sources: Maximum number of crossbar sources
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@ -33,6 +35,7 @@
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* @write: register write function pointer
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*/
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struct crossbar_device {
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raw_spinlock_t lock;
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uint int_max;
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uint safe_map;
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uint max_crossbar_sources;
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@ -44,72 +47,101 @@ struct crossbar_device {
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static struct crossbar_device *cb;
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static inline void crossbar_writel(int irq_no, int cb_no)
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static void crossbar_writel(int irq_no, int cb_no)
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{
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writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
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}
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static inline void crossbar_writew(int irq_no, int cb_no)
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static void crossbar_writew(int irq_no, int cb_no)
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{
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writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
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}
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static inline void crossbar_writeb(int irq_no, int cb_no)
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static void crossbar_writeb(int irq_no, int cb_no)
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{
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writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
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}
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static inline int get_prev_map_irq(int cb_no)
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{
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int i;
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for (i = cb->int_max - 1; i >= 0; i--)
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if (cb->irq_map[i] == cb_no)
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return i;
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return -ENODEV;
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}
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static inline int allocate_free_irq(int cb_no)
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static struct irq_chip crossbar_chip = {
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.name = "CBAR",
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.irq_eoi = irq_chip_eoi_parent,
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_set_wake = irq_chip_set_wake_parent,
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#ifdef CONFIG_SMP
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.irq_set_affinity = irq_chip_set_affinity_parent,
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#endif
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};
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static int allocate_gic_irq(struct irq_domain *domain, unsigned virq,
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irq_hw_number_t hwirq)
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{
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struct of_phandle_args args;
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int i;
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int err;
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raw_spin_lock(&cb->lock);
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for (i = cb->int_max - 1; i >= 0; i--) {
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if (cb->irq_map[i] == IRQ_FREE) {
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cb->irq_map[i] = cb_no;
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return i;
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cb->irq_map[i] = hwirq;
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break;
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}
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}
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raw_spin_unlock(&cb->lock);
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return -ENODEV;
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if (i < 0)
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return -ENODEV;
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args.np = domain->parent->of_node;
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args.args_count = 3;
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args.args[0] = 0; /* SPI */
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args.args[1] = i;
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args.args[2] = IRQ_TYPE_LEVEL_HIGH;
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err = irq_domain_alloc_irqs_parent(domain, virq, 1, &args);
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if (err)
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cb->irq_map[i] = IRQ_FREE;
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else
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cb->write(i, hwirq);
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return err;
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}
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static inline bool needs_crossbar_write(irq_hw_number_t hw)
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static int crossbar_domain_alloc(struct irq_domain *d, unsigned int virq,
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unsigned int nr_irqs, void *data)
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{
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int cb_no;
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struct of_phandle_args *args = data;
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irq_hw_number_t hwirq;
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int i;
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if (hw > GIC_IRQ_START) {
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cb_no = cb->irq_map[hw - GIC_IRQ_START];
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if (cb_no != IRQ_RESERVED && cb_no != IRQ_SKIP)
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return true;
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if (args->args_count != 3)
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return -EINVAL; /* Not GIC compliant */
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if (args->args[0] != 0)
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return -EINVAL; /* No PPI should point to this domain */
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hwirq = args->args[1];
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if ((hwirq + nr_irqs) > cb->max_crossbar_sources)
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return -EINVAL; /* Can't deal with this */
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for (i = 0; i < nr_irqs; i++) {
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int err = allocate_gic_irq(d, virq + i, hwirq + i);
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if (err)
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return err;
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irq_domain_set_hwirq_and_chip(d, virq + i, hwirq + i,
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&crossbar_chip, NULL);
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}
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return false;
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}
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static int crossbar_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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if (needs_crossbar_write(hw))
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cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]);
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return 0;
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}
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/**
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* crossbar_domain_unmap - unmap a crossbar<->irq connection
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* @d: domain of irq to unmap
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* @irq: virq number
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* crossbar_domain_free - unmap/free a crossbar<->irq connection
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* @domain: domain of irq to unmap
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* @virq: virq number
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* @nr_irqs: number of irqs to free
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*
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* We do not maintain a use count of total number of map/unmap
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* calls for a particular irq to find out if a irq can be really
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@ -117,14 +149,20 @@ static int crossbar_domain_map(struct irq_domain *d, unsigned int irq,
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* after which irq is anyways unusable. So an explicit map has to be called
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* after that.
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*/
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static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq)
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static void crossbar_domain_free(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs)
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{
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irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq;
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int i;
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if (needs_crossbar_write(hw)) {
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cb->irq_map[hw - GIC_IRQ_START] = IRQ_FREE;
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cb->write(hw - GIC_IRQ_START, cb->safe_map);
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raw_spin_lock(&cb->lock);
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for (i = 0; i < nr_irqs; i++) {
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struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
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irq_domain_reset_irq_data(d);
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cb->irq_map[d->hwirq] = IRQ_FREE;
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cb->write(d->hwirq, cb->safe_map);
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}
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raw_spin_unlock(&cb->lock);
|
||||
}
|
||||
|
||||
static int crossbar_domain_xlate(struct irq_domain *d,
|
||||
@ -133,44 +171,22 @@ static int crossbar_domain_xlate(struct irq_domain *d,
|
||||
unsigned long *out_hwirq,
|
||||
unsigned int *out_type)
|
||||
{
|
||||
int ret;
|
||||
int req_num = intspec[1];
|
||||
int direct_map_num;
|
||||
if (d->of_node != controller)
|
||||
return -EINVAL; /* Shouldn't happen, really... */
|
||||
if (intsize != 3)
|
||||
return -EINVAL; /* Not GIC compliant */
|
||||
if (intspec[0] != 0)
|
||||
return -EINVAL; /* No PPI should point to this domain */
|
||||
|
||||
if (req_num >= cb->max_crossbar_sources) {
|
||||
direct_map_num = req_num - cb->max_crossbar_sources;
|
||||
if (direct_map_num < cb->int_max) {
|
||||
ret = cb->irq_map[direct_map_num];
|
||||
if (ret == IRQ_RESERVED || ret == IRQ_SKIP) {
|
||||
/* We use the interrupt num as h/w irq num */
|
||||
ret = direct_map_num;
|
||||
goto found;
|
||||
}
|
||||
}
|
||||
|
||||
pr_err("%s: requested crossbar number %d > max %d\n",
|
||||
__func__, req_num, cb->max_crossbar_sources);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = get_prev_map_irq(req_num);
|
||||
if (ret >= 0)
|
||||
goto found;
|
||||
|
||||
ret = allocate_free_irq(req_num);
|
||||
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
found:
|
||||
*out_hwirq = ret + GIC_IRQ_START;
|
||||
*out_hwirq = intspec[1];
|
||||
*out_type = intspec[2];
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops routable_irq_domain_ops = {
|
||||
.map = crossbar_domain_map,
|
||||
.unmap = crossbar_domain_unmap,
|
||||
.xlate = crossbar_domain_xlate
|
||||
static const struct irq_domain_ops crossbar_domain_ops = {
|
||||
.alloc = crossbar_domain_alloc,
|
||||
.free = crossbar_domain_free,
|
||||
.xlate = crossbar_domain_xlate,
|
||||
};
|
||||
|
||||
static int __init crossbar_of_init(struct device_node *node)
|
||||
@ -293,7 +309,8 @@ static int __init crossbar_of_init(struct device_node *node)
|
||||
cb->write(i, cb->safe_map);
|
||||
}
|
||||
|
||||
register_routable_domain_ops(&routable_irq_domain_ops);
|
||||
raw_spin_lock_init(&cb->lock);
|
||||
|
||||
return 0;
|
||||
|
||||
err_reg_offset:
|
||||
@ -309,18 +326,37 @@ err_cb:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id crossbar_match[] __initconst = {
|
||||
{ .compatible = "ti,irq-crossbar" },
|
||||
{}
|
||||
};
|
||||
|
||||
int __init irqcrossbar_init(void)
|
||||
static int __init irqcrossbar_init(struct device_node *node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
struct device_node *np;
|
||||
np = of_find_matching_node(NULL, crossbar_match);
|
||||
if (!np)
|
||||
return -ENODEV;
|
||||
struct irq_domain *parent_domain, *domain;
|
||||
int err;
|
||||
|
||||
if (!parent) {
|
||||
pr_err("%s: no parent, giving up\n", node->full_name);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
parent_domain = irq_find_host(parent);
|
||||
if (!parent_domain) {
|
||||
pr_err("%s: unable to obtain parent domain\n", node->full_name);
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
err = crossbar_of_init(node);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
domain = irq_domain_add_hierarchy(parent_domain, 0,
|
||||
cb->max_crossbar_sources,
|
||||
node, &crossbar_domain_ops,
|
||||
NULL);
|
||||
if (!domain) {
|
||||
pr_err("%s: failed to allocated domain\n", node->full_name);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
crossbar_of_init(np);
|
||||
return 0;
|
||||
}
|
||||
|
||||
IRQCHIP_DECLARE(ti_irqcrossbar, "ti,irq-crossbar", irqcrossbar_init);
|
||||
|
||||
@ -1,11 +0,0 @@
|
||||
/*
|
||||
* drivers/irqchip/irq-crossbar.h
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
int irqcrossbar_init(void);
|
||||
Loading…
Reference in New Issue
Block a user