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drm/i915: Clear GPU read domains on reset
Clear the GPU read domain for the inactive objects on a reset so that they are correctly invalidated on reuse. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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@ -391,6 +391,11 @@ int i965_reset(struct drm_device *dev, u8 flags)
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*/
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i915_gem_reset_flushing_list(dev);
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/* Move everything out of the GPU domains to ensure we do any
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* necessary invalidation upon reuse.
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*/
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i915_gem_reset_inactive_gpu_domains(dev);
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/*
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* Set the domains we want to reset (GRDOM/bits 2 and 3) as
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* well as the reset bit (GR/bit 0). Setting the GR bit
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@ -998,6 +998,7 @@ int i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
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bool interruptible);
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void i915_gem_retire_requests(struct drm_device *dev);
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void i915_gem_reset_flushing_list(struct drm_device *dev);
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void i915_gem_reset_inactive_gpu_domains(struct drm_device *dev);
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void i915_gem_clflush_object(struct drm_gem_object *obj);
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int i915_gem_object_set_domain(struct drm_gem_object *obj,
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uint32_t read_domains,
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@ -1699,6 +1699,19 @@ void i915_gem_reset_flushing_list(struct drm_device *dev)
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}
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}
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void i915_gem_reset_inactive_gpu_domains(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_gem_object *obj_priv;
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list_for_each_entry(obj_priv,
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&dev_priv->mm.inactive_list,
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list)
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{
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obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
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}
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}
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/**
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* This function clears the request list as sequence numbers are passed.
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*/
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