mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-15 08:44:14 +08:00
Linux 5.4-rc7
-----BEGIN PGP SIGNATURE----- iQFSBAABCAA8FiEEq68RxlopcLEwq+PEeb4+QwBBGIYFAl3IqJQeHHRvcnZhbGRz QGxpbnV4LWZvdW5kYXRpb24ub3JnAAoJEHm+PkMAQRiGOiUH+gOEDwid5OODaFAd CggXugdFIlBZefKqGVNW5sjgX8pxFWHXuEMC8iNb6QXtQZdFrI6LFf9hhUDmzQtm 6y1LPxxEiTZjObMEsBNylb7tyzgujFHcAlp0Zro3w/HLCqmYTSP3FF46i2u6KZfL XhkpM4X7R7qxlfpdhlfESv/ElRGocZe6SwXfC7pcPo5flFcmkdu9ijqhNd/6CZ/h Nf9rTsD/wEDVUelFbgVN+LJzlaB0tsyc4Zbof07n8OsFZjhdEOop8gfM/kTBLcyY 6bh66SfDScdsNnC/l8csbPjSZRx+i+nQs67DyhGNnsSAFgHBZdC4Tb/2mDCwhCLR dUvuYZc= =1N6F -----END PGP SIGNATURE----- Merge v5.4-rc7 into drm-next We have the i915 security fixes to backmerge, but first let's clear the decks for other drivers to avoid a bigger mess. Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
commit
77e0723bd2
8
.mailmap
8
.mailmap
@ -108,6 +108,10 @@ Jason Gunthorpe <jgg@ziepe.ca> <jgg@mellanox.com>
|
||||
Jason Gunthorpe <jgg@ziepe.ca> <jgunthorpe@obsidianresearch.com>
|
||||
Javi Merino <javi.merino@kernel.org> <javi.merino@arm.com>
|
||||
<javier@osg.samsung.com> <javier.martinez@collabora.co.uk>
|
||||
Jayachandran C <c.jayachandran@gmail.com> <jayachandranc@netlogicmicro.com>
|
||||
Jayachandran C <c.jayachandran@gmail.com> <jchandra@broadcom.com>
|
||||
Jayachandran C <c.jayachandran@gmail.com> <jchandra@digeo.com>
|
||||
Jayachandran C <c.jayachandran@gmail.com> <jnair@caviumnetworks.com>
|
||||
Jean Tourrilhes <jt@hpl.hp.com>
|
||||
<jean-philippe@linaro.org> <jean-philippe.brucker@arm.com>
|
||||
Jeff Garzik <jgarzik@pretzel.yyz.us>
|
||||
@ -196,7 +200,8 @@ Oleksij Rempel <linux@rempel-privat.de> <o.rempel@pengutronix.de>
|
||||
Oleksij Rempel <linux@rempel-privat.de> <ore@pengutronix.de>
|
||||
Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it>
|
||||
Patrick Mochel <mochel@digitalimplant.org>
|
||||
Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
|
||||
Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
|
||||
Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
|
||||
Peter A Jonsson <pj@ludd.ltu.se>
|
||||
Peter Oruba <peter@oruba.de>
|
||||
Peter Oruba <peter.oruba@amd.com>
|
||||
@ -229,6 +234,7 @@ Shuah Khan <shuah@kernel.org> <shuahkhan@gmail.com>
|
||||
Shuah Khan <shuah@kernel.org> <shuah.khan@hp.com>
|
||||
Shuah Khan <shuah@kernel.org> <shuahkh@osg.samsung.com>
|
||||
Shuah Khan <shuah@kernel.org> <shuah.kh@samsung.com>
|
||||
Simon Arlott <simon@octiron.net> <simon@fire.lp0.eu>
|
||||
Simon Kelley <simon@thekelleys.org.uk>
|
||||
Stéphane Witzmann <stephane.witzmann@ubpmes.univ-bpclermont.fr>
|
||||
Stephen Hemminger <shemminger@osdl.org>
|
||||
|
@ -91,6 +91,11 @@ stable kernels.
|
||||
| ARM | MMU-500 | #841119,826419 | N/A |
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
| Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_845719 |
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
| Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_843419 |
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
| Cavium | ThunderX ITS | #22375,24313 | CAVIUM_ERRATUM_22375 |
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
|
||||
@ -126,7 +131,7 @@ stable kernels.
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
| Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
| Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |
|
||||
| Qualcomm Tech. | Kryo/Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
| Qualcomm Tech. | QDF2400 ITS | E0065 | QCOM_QDF2400_ERRATUM_0065 |
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
|
@ -496,12 +496,12 @@ properties:
|
||||
|
||||
- description: Theobroma Systems RK3368-uQ7 with Haikou baseboard
|
||||
items:
|
||||
- const: tsd,rk3368-uq7-haikou
|
||||
- const: tsd,rk3368-lion-haikou
|
||||
- const: rockchip,rk3368
|
||||
|
||||
- description: Theobroma Systems RK3399-Q7 with Haikou baseboard
|
||||
items:
|
||||
- const: tsd,rk3399-q7-haikou
|
||||
- const: tsd,rk3399-puma-haikou
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Tronsmart Orion R68 Meta
|
||||
|
@ -1,7 +1,7 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/allwinner,sun4i-a10-csi.yaml#
|
||||
$id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-csi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 CMOS Sensor Interface (CSI) Device Tree Bindings
|
||||
@ -27,14 +27,12 @@ properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: The CSI interface clock
|
||||
- description: The CSI module clock
|
||||
- description: The CSI ISP clock
|
||||
- description: The CSI DRAM clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: mod
|
||||
- const: isp
|
||||
- const: ram
|
||||
|
||||
@ -89,9 +87,8 @@ examples:
|
||||
compatible = "allwinner,sun7i-a20-csi0";
|
||||
reg = <0x01c09000 0x1000>;
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI0>,
|
||||
<&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
|
||||
clock-names = "bus", "mod", "isp", "ram";
|
||||
clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
|
||||
clock-names = "bus", "isp", "ram";
|
||||
resets = <&ccu RST_CSI0>;
|
||||
|
||||
port {
|
||||
|
@ -33,13 +33,13 @@ patternProperties:
|
||||
allOf:
|
||||
- $ref: "/schemas/types.yaml#/definitions/string"
|
||||
- enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
|
||||
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, ESPI,
|
||||
ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1,
|
||||
GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2,
|
||||
GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12,
|
||||
I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7,
|
||||
I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, LPC,
|
||||
LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2,
|
||||
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC,
|
||||
ESPI, ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWSPIWP, GPIT0,
|
||||
GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
|
||||
GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, I2C1, I2C10, I2C11,
|
||||
I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6,
|
||||
I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ,
|
||||
LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2,
|
||||
MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2,
|
||||
NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3,
|
||||
NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1,
|
||||
@ -48,47 +48,45 @@ patternProperties:
|
||||
PWM8, PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3,
|
||||
RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12,
|
||||
SALT13, SALT14, SALT15, SALT16, SALT2, SALT3, SALT4, SALT5,
|
||||
SALT6, SALT7, SALT8, SALT9, SD1, SD2, SD3, SD3DAT4, SD3DAT5,
|
||||
SD3DAT6, SD3DAT7, SGPM1, SGPS1, SIOONCTRL, SIOPBI, SIOPBO,
|
||||
SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1,
|
||||
SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11,
|
||||
TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5,
|
||||
TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1,
|
||||
TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13, UART6, UART7,
|
||||
UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3,
|
||||
WDTRST4, ]
|
||||
SALT6, SALT7, SALT8, SALT9, SD1, SD2, SGPM1, SGPS1, SIOONCTRL,
|
||||
SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1,
|
||||
SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1,
|
||||
TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3,
|
||||
TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2,
|
||||
THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13,
|
||||
UART6, UART7, UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2,
|
||||
WDTRST3, WDTRST4, ]
|
||||
groups:
|
||||
allOf:
|
||||
- $ref: "/schemas/types.yaml#/definitions/string"
|
||||
- enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
|
||||
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, ESPI,
|
||||
ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWQSPID, FWSPIWP, GPIT0,
|
||||
GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
|
||||
GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1,
|
||||
I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3,
|
||||
I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6,
|
||||
JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ,
|
||||
MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3,
|
||||
MDIO4, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4,
|
||||
NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1,
|
||||
NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE,
|
||||
PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, PWM12G0, PWM12G1,
|
||||
PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, PWM15G1, PWM2, PWM3,
|
||||
PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, PWM9G0, PWM9G1, QSPI1,
|
||||
QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3,
|
||||
RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1,
|
||||
SALT11G0, SALT11G1, SALT12G0, SALT12G1, SALT13G0, SALT13G1,
|
||||
SALT14G0, SALT14G1, SALT15G0, SALT15G1, SALT16G0, SALT16G1,
|
||||
SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9G0,
|
||||
SALT9G1, SD1, SD2, SD3, SD3DAT4, SD3DAT5, SD3DAT6, SD3DAT7,
|
||||
SGPM1, SGPS1, SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD,
|
||||
SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2,
|
||||
SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13,
|
||||
TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8,
|
||||
TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4,
|
||||
UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6,
|
||||
UART7, UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3,
|
||||
WDTRST4, ]
|
||||
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1,
|
||||
EMMCG4, EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID,
|
||||
FWQSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5,
|
||||
GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5, GPIU6,
|
||||
GPIU7, HVI3C3, HVI3C4, I2C1, I2C10, I2C11, I2C12, I2C13, I2C14,
|
||||
I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9,
|
||||
I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD,
|
||||
LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3, MACLINK4,
|
||||
MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1,
|
||||
NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2,
|
||||
NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4,
|
||||
OSCCLK, PEWAKE, PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1,
|
||||
PWM12G0, PWM12G1, PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0,
|
||||
PWM15G1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1,
|
||||
PWM9G0, PWM9G1, QSPI1, QSPI2, RGMII1, RGMII2, RGMII3, RGMII4,
|
||||
RMII1, RMII2, RMII3, RMII4, RXD1, RXD2, RXD3, RXD4, SALT1,
|
||||
SALT10G0, SALT10G1, SALT11G0, SALT11G1, SALT12G0, SALT12G1,
|
||||
SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0, SALT15G1,
|
||||
SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7,
|
||||
SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPS1, SIOONCTRL,
|
||||
SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1,
|
||||
SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1,
|
||||
TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3,
|
||||
TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2,
|
||||
THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12G0,
|
||||
UART12G1, UART13G0, UART13G1, UART6, UART7, UART8, UART9, VB,
|
||||
VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4, ]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
@ -30,8 +30,8 @@ if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- const: regulator-fixed
|
||||
- const: regulator-fixed-clock
|
||||
- regulator-fixed
|
||||
- regulator-fixed-clock
|
||||
|
||||
regulator-name: true
|
||||
|
||||
|
@ -24,15 +24,17 @@ description: |
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- sifive,rocket0
|
||||
- sifive,e5
|
||||
- sifive,e51
|
||||
- sifive,u54-mc
|
||||
- sifive,u54
|
||||
- sifive,u5
|
||||
- const: riscv
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- sifive,rocket0
|
||||
- sifive,e5
|
||||
- sifive,e51
|
||||
- sifive,u54-mc
|
||||
- sifive,u54
|
||||
- sifive,u5
|
||||
- const: riscv
|
||||
- const: riscv # Simulator only
|
||||
description:
|
||||
Identifies that the hart uses the RISC-V instruction set
|
||||
and identifies the type of the hart.
|
||||
@ -66,12 +68,8 @@ properties:
|
||||
insensitive, letters in the riscv,isa string must be all
|
||||
lowercase to simplify parsing.
|
||||
|
||||
timebase-frequency:
|
||||
type: integer
|
||||
minimum: 1
|
||||
description:
|
||||
Specifies the clock frequency of the system timer in Hz.
|
||||
This value is common to all harts on a single system image.
|
||||
# RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
|
||||
timebase-frequency: false
|
||||
|
||||
interrupt-controller:
|
||||
type: object
|
||||
@ -93,7 +91,6 @@ properties:
|
||||
|
||||
required:
|
||||
- riscv,isa
|
||||
- timebase-frequency
|
||||
- interrupt-controller
|
||||
|
||||
examples:
|
||||
|
@ -1,8 +1,8 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
==============================================================
|
||||
Linux* Base Driver for the Intel(R) PRO/100 Family of Adapters
|
||||
==============================================================
|
||||
=============================================================
|
||||
Linux Base Driver for the Intel(R) PRO/100 Family of Adapters
|
||||
=============================================================
|
||||
|
||||
June 1, 2018
|
||||
|
||||
@ -21,7 +21,7 @@ Contents
|
||||
In This Release
|
||||
===============
|
||||
|
||||
This file describes the Linux* Base Driver for the Intel(R) PRO/100 Family of
|
||||
This file describes the Linux Base Driver for the Intel(R) PRO/100 Family of
|
||||
Adapters. This driver includes support for Itanium(R)2-based systems.
|
||||
|
||||
For questions related to hardware requirements, refer to the documentation
|
||||
@ -138,9 +138,9 @@ version 1.6 or later is required for this functionality.
|
||||
The latest release of ethtool can be found from
|
||||
https://www.kernel.org/pub/software/network/ethtool/
|
||||
|
||||
Enabling Wake on LAN* (WoL)
|
||||
---------------------------
|
||||
WoL is provided through the ethtool* utility. For instructions on
|
||||
Enabling Wake on LAN (WoL)
|
||||
--------------------------
|
||||
WoL is provided through the ethtool utility. For instructions on
|
||||
enabling WoL with ethtool, refer to the ethtool man page. WoL will be
|
||||
enabled on the system during the next shut down or reboot. For this
|
||||
driver version, in order to enable WoL, the e100 driver must be loaded
|
||||
|
@ -1,8 +1,8 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
===========================================================
|
||||
Linux* Base Driver for Intel(R) Ethernet Network Connection
|
||||
===========================================================
|
||||
==========================================================
|
||||
Linux Base Driver for Intel(R) Ethernet Network Connection
|
||||
==========================================================
|
||||
|
||||
Intel Gigabit Linux driver.
|
||||
Copyright(c) 1999 - 2013 Intel Corporation.
|
||||
@ -438,10 +438,10 @@ ethtool
|
||||
The latest release of ethtool can be found from
|
||||
https://www.kernel.org/pub/software/network/ethtool/
|
||||
|
||||
Enabling Wake on LAN* (WoL)
|
||||
---------------------------
|
||||
Enabling Wake on LAN (WoL)
|
||||
--------------------------
|
||||
|
||||
WoL is configured through the ethtool* utility.
|
||||
WoL is configured through the ethtool utility.
|
||||
|
||||
WoL will be enabled on the system during the next shut down or reboot.
|
||||
For this driver version, in order to enable WoL, the e1000 driver must be
|
||||
|
@ -1,8 +1,8 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
======================================================
|
||||
Linux* Driver for Intel(R) Ethernet Network Connection
|
||||
======================================================
|
||||
=====================================================
|
||||
Linux Driver for Intel(R) Ethernet Network Connection
|
||||
=====================================================
|
||||
|
||||
Intel Gigabit Linux driver.
|
||||
Copyright(c) 2008-2018 Intel Corporation.
|
||||
@ -338,7 +338,7 @@ and higher cannot be forced. Use the autonegotiation advertising setting to
|
||||
manually set devices for 1 Gbps and higher.
|
||||
|
||||
Speed, duplex, and autonegotiation advertising are configured through the
|
||||
ethtool* utility.
|
||||
ethtool utility.
|
||||
|
||||
Caution: Only experienced network administrators should force speed and duplex
|
||||
or change autonegotiation advertising manually. The settings at the switch must
|
||||
@ -351,9 +351,9 @@ will not attempt to auto-negotiate with its link partner since those adapters
|
||||
operate only in full duplex and only at their native speed.
|
||||
|
||||
|
||||
Enabling Wake on LAN* (WoL)
|
||||
---------------------------
|
||||
WoL is configured through the ethtool* utility.
|
||||
Enabling Wake on LAN (WoL)
|
||||
--------------------------
|
||||
WoL is configured through the ethtool utility.
|
||||
|
||||
WoL will be enabled on the system during the next shut down or reboot. For
|
||||
this driver version, in order to enable WoL, the e1000e driver must be loaded
|
||||
|
@ -1,8 +1,8 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
==============================================================
|
||||
Linux* Base Driver for Intel(R) Ethernet Multi-host Controller
|
||||
==============================================================
|
||||
=============================================================
|
||||
Linux Base Driver for Intel(R) Ethernet Multi-host Controller
|
||||
=============================================================
|
||||
|
||||
August 20, 2018
|
||||
Copyright(c) 2015-2018 Intel Corporation.
|
||||
@ -120,8 +120,8 @@ rx-flow-hash tcp4|udp4|ah4|esp4|sctp4|tcp6|udp6|ah6|esp6|sctp6 m|v|t|s|d|f|n|r
|
||||
Known Issues/Troubleshooting
|
||||
============================
|
||||
|
||||
Enabling SR-IOV in a 64-bit Microsoft* Windows Server* 2012/R2 guest OS under Linux KVM
|
||||
---------------------------------------------------------------------------------------
|
||||
Enabling SR-IOV in a 64-bit Microsoft Windows Server 2012/R2 guest OS under Linux KVM
|
||||
-------------------------------------------------------------------------------------
|
||||
KVM Hypervisor/VMM supports direct assignment of a PCIe device to a VM. This
|
||||
includes traditional PCIe devices, as well as SR-IOV-capable devices based on
|
||||
the Intel Ethernet Controller XL710.
|
||||
|
@ -1,8 +1,8 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
==================================================================
|
||||
Linux* Base Driver for the Intel(R) Ethernet Controller 700 Series
|
||||
==================================================================
|
||||
=================================================================
|
||||
Linux Base Driver for the Intel(R) Ethernet Controller 700 Series
|
||||
=================================================================
|
||||
|
||||
Intel 40 Gigabit Linux driver.
|
||||
Copyright(c) 1999-2018 Intel Corporation.
|
||||
@ -384,7 +384,7 @@ NOTE: You cannot set the speed for devices based on the Intel(R) Ethernet
|
||||
Network Adapter XXV710 based devices.
|
||||
|
||||
Speed, duplex, and autonegotiation advertising are configured through the
|
||||
ethtool* utility.
|
||||
ethtool utility.
|
||||
|
||||
Caution: Only experienced network administrators should force speed and duplex
|
||||
or change autonegotiation advertising manually. The settings at the switch must
|
||||
|
@ -1,8 +1,8 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
==================================================================
|
||||
Linux* Base Driver for Intel(R) Ethernet Adaptive Virtual Function
|
||||
==================================================================
|
||||
=================================================================
|
||||
Linux Base Driver for Intel(R) Ethernet Adaptive Virtual Function
|
||||
=================================================================
|
||||
|
||||
Intel Ethernet Adaptive Virtual Function Linux driver.
|
||||
Copyright(c) 2013-2018 Intel Corporation.
|
||||
@ -19,7 +19,7 @@ Contents
|
||||
Overview
|
||||
========
|
||||
|
||||
This file describes the iavf Linux* Base Driver. This driver was formerly
|
||||
This file describes the iavf Linux Base Driver. This driver was formerly
|
||||
called i40evf.
|
||||
|
||||
The iavf driver supports the below mentioned virtual function devices and
|
||||
|
@ -1,8 +1,8 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
===================================================================
|
||||
Linux* Base Driver for the Intel(R) Ethernet Connection E800 Series
|
||||
===================================================================
|
||||
==================================================================
|
||||
Linux Base Driver for the Intel(R) Ethernet Connection E800 Series
|
||||
==================================================================
|
||||
|
||||
Intel ice Linux driver.
|
||||
Copyright(c) 2018 Intel Corporation.
|
||||
|
@ -1,8 +1,8 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
===========================================================
|
||||
Linux* Base Driver for Intel(R) Ethernet Network Connection
|
||||
===========================================================
|
||||
==========================================================
|
||||
Linux Base Driver for Intel(R) Ethernet Network Connection
|
||||
==========================================================
|
||||
|
||||
Intel Gigabit Linux driver.
|
||||
Copyright(c) 1999-2018 Intel Corporation.
|
||||
@ -129,9 +129,9 @@ version is required for this functionality. Download it at:
|
||||
https://www.kernel.org/pub/software/network/ethtool/
|
||||
|
||||
|
||||
Enabling Wake on LAN* (WoL)
|
||||
---------------------------
|
||||
WoL is configured through the ethtool* utility.
|
||||
Enabling Wake on LAN (WoL)
|
||||
--------------------------
|
||||
WoL is configured through the ethtool utility.
|
||||
|
||||
WoL will be enabled on the system during the next shut down or reboot. For
|
||||
this driver version, in order to enable WoL, the igb driver must be loaded
|
||||
|
@ -1,8 +1,8 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
============================================================
|
||||
Linux* Base Virtual Function Driver for Intel(R) 1G Ethernet
|
||||
============================================================
|
||||
===========================================================
|
||||
Linux Base Virtual Function Driver for Intel(R) 1G Ethernet
|
||||
===========================================================
|
||||
|
||||
Intel Gigabit Virtual Function Linux driver.
|
||||
Copyright(c) 1999-2018 Intel Corporation.
|
||||
|
@ -1,8 +1,8 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
=============================================================================
|
||||
Linux* Base Driver for the Intel(R) Ethernet 10 Gigabit PCI Express Adapters
|
||||
=============================================================================
|
||||
===========================================================================
|
||||
Linux Base Driver for the Intel(R) Ethernet 10 Gigabit PCI Express Adapters
|
||||
===========================================================================
|
||||
|
||||
Intel 10 Gigabit Linux driver.
|
||||
Copyright(c) 1999-2018 Intel Corporation.
|
||||
@ -519,8 +519,8 @@ The offload is also supported for ixgbe's VFs, but the VF must be set as
|
||||
Known Issues/Troubleshooting
|
||||
============================
|
||||
|
||||
Enabling SR-IOV in a 64-bit Microsoft* Windows Server* 2012/R2 guest OS
|
||||
-----------------------------------------------------------------------
|
||||
Enabling SR-IOV in a 64-bit Microsoft Windows Server 2012/R2 guest OS
|
||||
---------------------------------------------------------------------
|
||||
Linux KVM Hypervisor/VMM supports direct assignment of a PCIe device to a VM.
|
||||
This includes traditional PCIe devices, as well as SR-IOV-capable devices based
|
||||
on the Intel Ethernet Controller XL710.
|
||||
|
@ -1,8 +1,8 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
=============================================================
|
||||
Linux* Base Virtual Function Driver for Intel(R) 10G Ethernet
|
||||
=============================================================
|
||||
============================================================
|
||||
Linux Base Virtual Function Driver for Intel(R) 10G Ethernet
|
||||
============================================================
|
||||
|
||||
Intel 10 Gigabit Virtual Function Linux driver.
|
||||
Copyright(c) 1999-2018 Intel Corporation.
|
||||
|
@ -1,8 +1,8 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
==========================================================
|
||||
Linux* Driver for the Pensando(R) Ethernet adapter family
|
||||
==========================================================
|
||||
========================================================
|
||||
Linux Driver for the Pensando(R) Ethernet adapter family
|
||||
========================================================
|
||||
|
||||
Pensando Linux Ethernet driver.
|
||||
Copyright(c) 2019 Pensando Systems, Inc
|
||||
|
@ -207,8 +207,8 @@ TCP variables:
|
||||
|
||||
somaxconn - INTEGER
|
||||
Limit of socket listen() backlog, known in userspace as SOMAXCONN.
|
||||
Defaults to 128. See also tcp_max_syn_backlog for additional tuning
|
||||
for TCP sockets.
|
||||
Defaults to 4096. (Was 128 before linux-5.4)
|
||||
See also tcp_max_syn_backlog for additional tuning for TCP sockets.
|
||||
|
||||
tcp_abort_on_overflow - BOOLEAN
|
||||
If listening service is too slow to accept new connections,
|
||||
@ -408,11 +408,14 @@ tcp_max_orphans - INTEGER
|
||||
up to ~64K of unswappable memory.
|
||||
|
||||
tcp_max_syn_backlog - INTEGER
|
||||
Maximal number of remembered connection requests, which have not
|
||||
received an acknowledgment from connecting client.
|
||||
Maximal number of remembered connection requests (SYN_RECV),
|
||||
which have not received an acknowledgment from connecting client.
|
||||
This is a per-listener limit.
|
||||
The minimal value is 128 for low memory machines, and it will
|
||||
increase in proportion to the memory of machine.
|
||||
If server suffers from overload, try increasing this number.
|
||||
Remember to also check /proc/sys/net/core/somaxconn
|
||||
A SYN_RECV request socket consumes about 304 bytes of memory.
|
||||
|
||||
tcp_max_tw_buckets - INTEGER
|
||||
Maximal number of timewait sockets held by system simultaneously.
|
||||
|
@ -436,6 +436,10 @@ by the driver:
|
||||
encryption.
|
||||
* ``tx_tls_ooo`` - number of TX packets which were part of a TLS stream
|
||||
but did not arrive in the expected order.
|
||||
* ``tx_tls_skip_no_sync_data`` - number of TX packets which were part of
|
||||
a TLS stream and arrived out-of-order, but skipped the HW offload routine
|
||||
and went to the regular transmit flow as they were retransmissions of the
|
||||
connection handshake.
|
||||
* ``tx_tls_drop_no_sync_data`` - number of TX packets which were part of
|
||||
a TLS stream dropped, because they arrived out of order and associated
|
||||
record could not be found.
|
||||
|
39
MAINTAINERS
39
MAINTAINERS
@ -2326,11 +2326,13 @@ F: drivers/edac/altera_edac.
|
||||
|
||||
ARM/SPREADTRUM SoC SUPPORT
|
||||
M: Orson Zhai <orsonzhai@gmail.com>
|
||||
M: Baolin Wang <baolin.wang@linaro.org>
|
||||
M: Baolin Wang <baolin.wang7@gmail.com>
|
||||
M: Chunyan Zhang <zhang.lyra@gmail.com>
|
||||
S: Maintained
|
||||
F: arch/arm64/boot/dts/sprd
|
||||
N: sprd
|
||||
N: sc27xx
|
||||
N: sc2731
|
||||
|
||||
ARM/STI ARCHITECTURE
|
||||
M: Patrice Chotard <patrice.chotard@st.com>
|
||||
@ -3054,6 +3056,7 @@ M: Daniel Borkmann <daniel@iogearbox.net>
|
||||
R: Martin KaFai Lau <kafai@fb.com>
|
||||
R: Song Liu <songliubraving@fb.com>
|
||||
R: Yonghong Song <yhs@fb.com>
|
||||
R: Andrii Nakryiko <andriin@fb.com>
|
||||
L: netdev@vger.kernel.org
|
||||
L: bpf@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf.git
|
||||
@ -3099,7 +3102,7 @@ S: Supported
|
||||
F: arch/arm64/net/
|
||||
|
||||
BPF JIT for MIPS (32-BIT AND 64-BIT)
|
||||
M: Paul Burton <paul.burton@mips.com>
|
||||
M: Paul Burton <paulburton@kernel.org>
|
||||
L: netdev@vger.kernel.org
|
||||
L: bpf@vger.kernel.org
|
||||
S: Maintained
|
||||
@ -3186,7 +3189,7 @@ N: bcm216*
|
||||
N: kona
|
||||
F: arch/arm/mach-bcm/
|
||||
|
||||
BROADCOM BCM2835 ARM ARCHITECTURE
|
||||
BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE
|
||||
M: Eric Anholt <eric@anholt.net>
|
||||
M: Stefan Wahren <wahrenst@gmx.net>
|
||||
L: bcm-kernel-feedback-list@broadcom.com
|
||||
@ -3194,6 +3197,7 @@ L: linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
T: git git://github.com/anholt/linux
|
||||
S: Maintained
|
||||
N: bcm2711
|
||||
N: bcm2835
|
||||
F: drivers/staging/vc04_services
|
||||
|
||||
@ -3240,8 +3244,6 @@ S: Maintained
|
||||
F: drivers/usb/gadget/udc/bcm63xx_udc.*
|
||||
|
||||
BROADCOM BCM7XXX ARM ARCHITECTURE
|
||||
M: Brian Norris <computersforpeace@gmail.com>
|
||||
M: Gregory Fong <gregory.0xf0@gmail.com>
|
||||
M: Florian Fainelli <f.fainelli@gmail.com>
|
||||
M: bcm-kernel-feedback-list@broadcom.com
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
@ -3739,7 +3741,6 @@ F: drivers/crypto/cavium/cpt/
|
||||
|
||||
CAVIUM THUNDERX2 ARM64 SOC
|
||||
M: Robert Richter <rrichter@cavium.com>
|
||||
M: Jayachandran C <jnair@caviumnetworks.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm64/boot/dts/cavium/thunder2-99xx*
|
||||
@ -8014,7 +8015,7 @@ S: Maintained
|
||||
F: drivers/usb/atm/ueagle-atm.c
|
||||
|
||||
IMGTEC ASCII LCD DRIVER
|
||||
M: Paul Burton <paul.burton@mips.com>
|
||||
M: Paul Burton <paulburton@kernel.org>
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/auxdisplay/img-ascii-lcd.txt
|
||||
F: drivers/auxdisplay/img-ascii-lcd.c
|
||||
@ -10531,8 +10532,12 @@ F: mm/memblock.c
|
||||
F: Documentation/core-api/boot-time-mm.rst
|
||||
|
||||
MEMORY MANAGEMENT
|
||||
M: Andrew Morton <akpm@linux-foundation.org>
|
||||
L: linux-mm@kvack.org
|
||||
W: http://www.linux-mm.org
|
||||
T: quilt https://ozlabs.org/~akpm/mmotm/
|
||||
T: quilt https://ozlabs.org/~akpm/mmots/
|
||||
T: git git://github.com/hnaz/linux-mm.git
|
||||
S: Maintained
|
||||
F: include/linux/mm.h
|
||||
F: include/linux/gfp.h
|
||||
@ -10841,7 +10846,7 @@ F: drivers/usb/image/microtek.*
|
||||
|
||||
MIPS
|
||||
M: Ralf Baechle <ralf@linux-mips.org>
|
||||
M: Paul Burton <paul.burton@mips.com>
|
||||
M: Paul Burton <paulburton@kernel.org>
|
||||
M: James Hogan <jhogan@kernel.org>
|
||||
L: linux-mips@vger.kernel.org
|
||||
W: http://www.linux-mips.org/
|
||||
@ -10855,7 +10860,7 @@ F: arch/mips/
|
||||
F: drivers/platform/mips/
|
||||
|
||||
MIPS BOSTON DEVELOPMENT BOARD
|
||||
M: Paul Burton <paul.burton@mips.com>
|
||||
M: Paul Burton <paulburton@kernel.org>
|
||||
L: linux-mips@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/clock/img,boston-clock.txt
|
||||
@ -10865,7 +10870,7 @@ F: drivers/clk/imgtec/clk-boston.c
|
||||
F: include/dt-bindings/clock/boston-clock.h
|
||||
|
||||
MIPS GENERIC PLATFORM
|
||||
M: Paul Burton <paul.burton@mips.com>
|
||||
M: Paul Burton <paulburton@kernel.org>
|
||||
L: linux-mips@vger.kernel.org
|
||||
S: Supported
|
||||
F: Documentation/devicetree/bindings/power/mti,mips-cpc.txt
|
||||
@ -11420,7 +11425,6 @@ F: include/trace/events/tcp.h
|
||||
NETWORKING [TLS]
|
||||
M: Boris Pismenny <borisp@mellanox.com>
|
||||
M: Aviad Yehezkel <aviadye@mellanox.com>
|
||||
M: Dave Watson <davejwatson@fb.com>
|
||||
M: John Fastabend <john.fastabend@gmail.com>
|
||||
M: Daniel Borkmann <daniel@iogearbox.net>
|
||||
M: Jakub Kicinski <jakub.kicinski@netronome.com>
|
||||
@ -13918,7 +13922,7 @@ F: drivers/mtd/nand/raw/r852.h
|
||||
|
||||
RISC-V ARCHITECTURE
|
||||
M: Paul Walmsley <paul.walmsley@sifive.com>
|
||||
M: Palmer Dabbelt <palmer@sifive.com>
|
||||
M: Palmer Dabbelt <palmer@dabbelt.com>
|
||||
M: Albert Ou <aou@eecs.berkeley.edu>
|
||||
L: linux-riscv@lists.infradead.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git
|
||||
@ -14795,7 +14799,7 @@ F: drivers/media/usb/siano/
|
||||
F: drivers/media/mmc/siano/
|
||||
|
||||
SIFIVE DRIVERS
|
||||
M: Palmer Dabbelt <palmer@sifive.com>
|
||||
M: Palmer Dabbelt <palmer@dabbelt.com>
|
||||
M: Paul Walmsley <paul.walmsley@sifive.com>
|
||||
L: linux-riscv@lists.infradead.org
|
||||
T: git git://github.com/sifive/riscv-linux.git
|
||||
@ -14805,7 +14809,7 @@ N: sifive
|
||||
|
||||
SIFIVE FU540 SYSTEM-ON-CHIP
|
||||
M: Paul Walmsley <paul.walmsley@sifive.com>
|
||||
M: Palmer Dabbelt <palmer@sifive.com>
|
||||
M: Palmer Dabbelt <palmer@dabbelt.com>
|
||||
L: linux-riscv@lists.infradead.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pjw/sifive.git
|
||||
S: Supported
|
||||
@ -17347,6 +17351,12 @@ F: include/linux/vbox_utils.h
|
||||
F: include/uapi/linux/vbox*.h
|
||||
F: drivers/virt/vboxguest/
|
||||
|
||||
VIRTUAL BOX SHARED FOLDER VFS DRIVER:
|
||||
M: Hans de Goede <hdegoede@redhat.com>
|
||||
L: linux-fsdevel@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/staging/vboxsf/*
|
||||
|
||||
VIRTUAL SERIO DEVICE DRIVER
|
||||
M: Stephen Chandler Paul <thatslyude@gmail.com>
|
||||
S: Maintained
|
||||
@ -18047,6 +18057,7 @@ F: Documentation/vm/zsmalloc.rst
|
||||
ZSWAP COMPRESSED SWAP CACHING
|
||||
M: Seth Jennings <sjenning@redhat.com>
|
||||
M: Dan Streetman <ddstreet@ieee.org>
|
||||
M: Vitaly Wool <vitaly.wool@konsulko.com>
|
||||
L: linux-mm@kvack.org
|
||||
S: Maintained
|
||||
F: mm/zswap.c
|
||||
|
4
Makefile
4
Makefile
@ -2,8 +2,8 @@
|
||||
VERSION = 5
|
||||
PATCHLEVEL = 4
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc4
|
||||
NAME = Nesting Opossum
|
||||
EXTRAVERSION = -rc7
|
||||
NAME = Kleptomaniac Octopus
|
||||
|
||||
# *DOCUMENTATION*
|
||||
# To see a list of typical targets execute "make help"
|
||||
|
@ -65,6 +65,14 @@
|
||||
clock-frequency = <33333333>;
|
||||
};
|
||||
|
||||
reg_5v0: regulator-5v0 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "5v0-supply";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
cpu_intc: cpu-interrupt-controller {
|
||||
compatible = "snps,archs-intc";
|
||||
interrupt-controller;
|
||||
@ -264,6 +272,21 @@
|
||||
clocks = <&input_clk>;
|
||||
cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>,
|
||||
<&creg_gpio 1 GPIO_ACTIVE_LOW>;
|
||||
|
||||
spi-flash@0 {
|
||||
compatible = "sst26wf016b", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <4000000>;
|
||||
};
|
||||
|
||||
adc@1 {
|
||||
compatible = "ti,adc108s102";
|
||||
reg = <1>;
|
||||
vref-supply = <®_5v0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
creg_gpio: gpio@14b0 {
|
||||
|
@ -32,6 +32,8 @@ CONFIG_INET=y
|
||||
CONFIG_DEVTMPFS=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_NETDEVICES=y
|
||||
@ -55,6 +57,8 @@ CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_DWAPB=y
|
||||
CONFIG_GPIO_SNPS_CREG=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_DRM=y
|
||||
# CONFIG_DRM_FBDEV_EMULATION is not set
|
||||
CONFIG_DRM_UDL=y
|
||||
@ -72,6 +76,8 @@ CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_DW_AXI_DMAC=y
|
||||
CONFIG_IIO=y
|
||||
CONFIG_TI_ADC108S102=y
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
|
@ -614,8 +614,8 @@ static int arc_pmu_device_probe(struct platform_device *pdev)
|
||||
/* loop thru all available h/w condition indexes */
|
||||
for (i = 0; i < cc_bcr.c; i++) {
|
||||
write_aux_reg(ARC_REG_CC_INDEX, i);
|
||||
cc_name.indiv.word0 = read_aux_reg(ARC_REG_CC_NAME0);
|
||||
cc_name.indiv.word1 = read_aux_reg(ARC_REG_CC_NAME1);
|
||||
cc_name.indiv.word0 = le32_to_cpu(read_aux_reg(ARC_REG_CC_NAME0));
|
||||
cc_name.indiv.word1 = le32_to_cpu(read_aux_reg(ARC_REG_CC_NAME1));
|
||||
|
||||
arc_pmu_map_hw_event(i, cc_name.str);
|
||||
arc_pmu_add_raw_event_attr(i, cc_name.str);
|
||||
|
@ -111,13 +111,13 @@
|
||||
reg = <0x70>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
i2c-mux-idle-disconnect;
|
||||
|
||||
i2c@0 {
|
||||
/* FMC A */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
i2c-mux-idle-disconnect;
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
@ -125,7 +125,6 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
i2c-mux-idle-disconnect;
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
@ -133,7 +132,6 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
i2c-mux-idle-disconnect;
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
@ -141,7 +139,6 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
i2c-mux-idle-disconnect;
|
||||
};
|
||||
|
||||
i2c@4 {
|
||||
@ -149,14 +146,12 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
i2c-mux-idle-disconnect;
|
||||
};
|
||||
|
||||
i2c@5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
i2c-mux-idle-disconnect;
|
||||
|
||||
ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; };
|
||||
ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; };
|
||||
@ -182,14 +177,12 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6>;
|
||||
i2c-mux-idle-disconnect;
|
||||
};
|
||||
|
||||
i2c@7 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <7>;
|
||||
i2c-mux-idle-disconnect;
|
||||
|
||||
u41: pca9575@20 {
|
||||
compatible = "nxp,pca9575";
|
||||
|
@ -113,6 +113,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>;
|
||||
bus-width = <4>;
|
||||
mmc-pwrseq = <&wifi_pwrseq>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
|
@ -9,6 +9,14 @@
|
||||
reg = <0 0x40000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
/*
|
||||
* Since there is no upstream GPIO driver yet,
|
||||
* remove the incomplete node.
|
||||
*/
|
||||
/delete-node/ act;
|
||||
};
|
||||
|
||||
reg_3v3: fixed-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3V3";
|
||||
|
@ -328,6 +328,10 @@
|
||||
pinctrl-0 = <&pinctrl_pwm3>;
|
||||
};
|
||||
|
||||
&snvs_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -207,6 +207,10 @@
|
||||
vin-supply = <&sw1c_reg>;
|
||||
};
|
||||
|
||||
&snvs_poweroff {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
@ -230,6 +230,8 @@
|
||||
accelerometer@1c {
|
||||
compatible = "fsl,mma8451";
|
||||
reg = <0x1c>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mma8451_int>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
@ -628,6 +630,12 @@
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_mma8451_int: mma8451intgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm3: pwm1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
|
||||
|
@ -448,7 +448,7 @@
|
||||
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
|
||||
reg = <0x302d0000 0x10000>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_CLK_DUMMY>,
|
||||
clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
|
||||
<&clks IMX7D_GPT1_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
@ -457,7 +457,7 @@
|
||||
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
|
||||
reg = <0x302e0000 0x10000>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_CLK_DUMMY>,
|
||||
clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
|
||||
<&clks IMX7D_GPT2_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
@ -467,7 +467,7 @@
|
||||
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
|
||||
reg = <0x302f0000 0x10000>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_CLK_DUMMY>,
|
||||
clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
|
||||
<&clks IMX7D_GPT3_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
@ -477,7 +477,7 @@
|
||||
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
|
||||
reg = <0x30300000 0x10000>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_CLK_DUMMY>,
|
||||
clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
|
||||
<&clks IMX7D_GPT4_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
|
@ -192,3 +192,7 @@
|
||||
&twl_gpio {
|
||||
ti,use-leds;
|
||||
};
|
||||
|
||||
&twl_keypad {
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -369,7 +369,7 @@
|
||||
compatible = "ti,wl1285", "ti,wl1283";
|
||||
reg = <2>;
|
||||
/* gpio_100 with gpmc_wait2 pad as wakeirq */
|
||||
interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>,
|
||||
interrupts-extended = <&gpio4 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&omap4_pmx_core 0x4e>;
|
||||
interrupt-names = "irq", "wakeup";
|
||||
ref-clock-frequency = <26000000>;
|
||||
|
@ -474,7 +474,7 @@
|
||||
compatible = "ti,wl1271";
|
||||
reg = <2>;
|
||||
/* gpio_53 with gpmc_ncs3 pad as wakeup */
|
||||
interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_RISING>,
|
||||
interrupts-extended = <&gpio2 21 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&omap4_pmx_core 0x3a>;
|
||||
interrupt-names = "irq", "wakeup";
|
||||
ref-clock-frequency = <38400000>;
|
||||
|
@ -512,7 +512,7 @@
|
||||
compatible = "ti,wl1281";
|
||||
reg = <2>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 53 */
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */
|
||||
ref-clock-frequency = <26000000>;
|
||||
tcxo-clock-frequency = <26000000>;
|
||||
};
|
||||
|
@ -69,7 +69,7 @@
|
||||
compatible = "ti,wl1271";
|
||||
reg = <2>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <9 IRQ_TYPE_EDGE_RISING>; /* gpio 41 */
|
||||
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; /* gpio 41 */
|
||||
ref-clock-frequency = <38400000>;
|
||||
};
|
||||
};
|
||||
|
@ -362,7 +362,7 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wlcore_irq_pin>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <14 IRQ_TYPE_EDGE_RISING>; /* gpio 14 */
|
||||
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */
|
||||
ref-clock-frequency = <26000000>;
|
||||
};
|
||||
};
|
||||
|
@ -1146,7 +1146,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
gpu_cm: clock-controller@1500 {
|
||||
gpu_cm: gpu_cm@1500 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0x1500 0x100>;
|
||||
#address-cells = <1>;
|
||||
|
@ -609,13 +609,13 @@
|
||||
<STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <3>;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
|
||||
bias-pull-up;
|
||||
drive-push-pull;
|
||||
slew-rate = <3>;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -637,13 +637,13 @@
|
||||
<STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <3>;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
|
||||
bias-pull-up;
|
||||
drive-push-pull;
|
||||
slew-rate = <3>;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -183,14 +183,12 @@
|
||||
|
||||
ov5640: camera@3c {
|
||||
compatible = "ovti,ov5640";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ov5640_pins>;
|
||||
reg = <0x3c>;
|
||||
clocks = <&clk_ext_camera>;
|
||||
clock-names = "xclk";
|
||||
DOVDD-supply = <&v2v8>;
|
||||
powerdown-gpios = <&stmfx_pinctrl 18 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&stmfx_pinctrl 19 GPIO_ACTIVE_LOW>;
|
||||
powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
|
||||
reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
|
||||
rotation = <180>;
|
||||
status = "okay";
|
||||
|
||||
@ -223,15 +221,8 @@
|
||||
|
||||
joystick_pins: joystick {
|
||||
pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
|
||||
drive-push-pull;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
ov5640_pins: camera {
|
||||
pins = "agpio2", "agpio3"; /* stmfx pins 18 & 19 */
|
||||
drive-push-pull;
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@ -932,7 +932,7 @@
|
||||
interrupt-names = "int0", "int1";
|
||||
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
||||
clock-names = "hclk", "cclk";
|
||||
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
|
||||
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -945,7 +945,7 @@
|
||||
interrupt-names = "int0", "int1";
|
||||
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
||||
clock-names = "hclk", "cclk";
|
||||
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
|
||||
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -380,9 +380,8 @@
|
||||
compatible = "allwinner,sun7i-a20-csi0";
|
||||
reg = <0x01c09000 0x1000>;
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI0>,
|
||||
<&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
|
||||
clock-names = "bus", "mod", "isp", "ram";
|
||||
clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
|
||||
clock-names = "bus", "isp", "ram";
|
||||
resets = <&ccu RST_CSI0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -192,6 +192,7 @@
|
||||
vqmmc-supply = <®_dldo1>;
|
||||
non-removable;
|
||||
wakeup-source;
|
||||
keep-power-in-suspend;
|
||||
status = "okay";
|
||||
|
||||
brcmf: wifi@1 {
|
||||
|
@ -602,6 +602,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x70>;
|
||||
i2c-mux-idle-disconnect;
|
||||
|
||||
sff0_i2c: i2c@1 {
|
||||
#address-cells = <1>;
|
||||
@ -640,6 +641,7 @@
|
||||
reg = <0x71>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
i2c-mux-idle-disconnect;
|
||||
|
||||
sff5_i2c: i2c@1 {
|
||||
#address-cells = <1>;
|
||||
|
@ -167,6 +167,7 @@ CONFIG_FB=y
|
||||
CONFIG_FIRMWARE_EDID=y
|
||||
CONFIG_FB_DA8XX=y
|
||||
CONFIG_BACKLIGHT_PWM=m
|
||||
CONFIG_BACKLIGHT_GPIO=m
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_LOGO=y
|
||||
CONFIG_SOUND=m
|
||||
|
@ -276,6 +276,7 @@ CONFIG_VIDEO_OV5640=m
|
||||
CONFIG_VIDEO_OV5645=m
|
||||
CONFIG_IMX_IPUV3_CORE=y
|
||||
CONFIG_DRM=y
|
||||
CONFIG_DRM_MSM=y
|
||||
CONFIG_DRM_PANEL_LVDS=y
|
||||
CONFIG_DRM_PANEL_SIMPLE=y
|
||||
CONFIG_DRM_PANEL_SEIKO_43WVF1G=y
|
||||
|
@ -356,15 +356,15 @@ CONFIG_DRM_OMAP_CONNECTOR_HDMI=m
|
||||
CONFIG_DRM_OMAP_CONNECTOR_ANALOG_TV=m
|
||||
CONFIG_DRM_OMAP_PANEL_DPI=m
|
||||
CONFIG_DRM_OMAP_PANEL_DSI_CM=m
|
||||
CONFIG_DRM_OMAP_PANEL_SONY_ACX565AKM=m
|
||||
CONFIG_DRM_OMAP_PANEL_LGPHILIPS_LB035Q02=m
|
||||
CONFIG_DRM_OMAP_PANEL_SHARP_LS037V7DW01=m
|
||||
CONFIG_DRM_OMAP_PANEL_TPO_TD028TTEC1=m
|
||||
CONFIG_DRM_OMAP_PANEL_TPO_TD043MTEA1=m
|
||||
CONFIG_DRM_OMAP_PANEL_NEC_NL8048HL11=m
|
||||
CONFIG_DRM_TILCDC=m
|
||||
CONFIG_DRM_PANEL_SIMPLE=m
|
||||
CONFIG_DRM_TI_TFP410=m
|
||||
CONFIG_DRM_PANEL_LG_LB035Q02=m
|
||||
CONFIG_DRM_PANEL_NEC_NL8048HL11=m
|
||||
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
|
||||
CONFIG_DRM_PANEL_SONY_ACX565AKM=m
|
||||
CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
|
||||
CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
|
||||
CONFIG_FB=y
|
||||
CONFIG_FIRMWARE_EDID=y
|
||||
CONFIG_FB_MODE_HELPERS=y
|
||||
|
@ -82,7 +82,7 @@
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#ifdef CONFIG_CPU_CP15_MMU
|
||||
static inline unsigned int get_domain(void)
|
||||
static __always_inline unsigned int get_domain(void)
|
||||
{
|
||||
unsigned int domain;
|
||||
|
||||
@ -94,7 +94,7 @@ static inline unsigned int get_domain(void)
|
||||
return domain;
|
||||
}
|
||||
|
||||
static inline void set_domain(unsigned val)
|
||||
static __always_inline void set_domain(unsigned int val)
|
||||
{
|
||||
asm volatile(
|
||||
"mcr p15, 0, %0, c3, c0 @ set domain"
|
||||
@ -102,12 +102,12 @@ static inline void set_domain(unsigned val)
|
||||
isb();
|
||||
}
|
||||
#else
|
||||
static inline unsigned int get_domain(void)
|
||||
static __always_inline unsigned int get_domain(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void set_domain(unsigned val)
|
||||
static __always_inline void set_domain(unsigned int val)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
@ -22,7 +22,7 @@
|
||||
* perform such accesses (eg, via list poison values) which could then
|
||||
* be exploited for priviledge escalation.
|
||||
*/
|
||||
static inline unsigned int uaccess_save_and_enable(void)
|
||||
static __always_inline unsigned int uaccess_save_and_enable(void)
|
||||
{
|
||||
#ifdef CONFIG_CPU_SW_DOMAIN_PAN
|
||||
unsigned int old_domain = get_domain();
|
||||
@ -37,7 +37,7 @@ static inline unsigned int uaccess_save_and_enable(void)
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void uaccess_restore(unsigned int flags)
|
||||
static __always_inline void uaccess_restore(unsigned int flags)
|
||||
{
|
||||
#ifdef CONFIG_CPU_SW_DOMAIN_PAN
|
||||
/* Restore the user access mask */
|
||||
|
@ -68,7 +68,7 @@ ENDPROC(__vet_atags)
|
||||
* The following fragment of code is executed with the MMU on in MMU mode,
|
||||
* and uses absolute addresses; this is not position independent.
|
||||
*
|
||||
* r0 = cp#15 control register
|
||||
* r0 = cp#15 control register (exc_ret for M-class)
|
||||
* r1 = machine ID
|
||||
* r2 = atags/dtb pointer
|
||||
* r9 = processor ID
|
||||
@ -137,7 +137,8 @@ __mmap_switched_data:
|
||||
#ifdef CONFIG_CPU_CP15
|
||||
.long cr_alignment @ r3
|
||||
#else
|
||||
.long 0 @ r3
|
||||
M_CLASS(.long exc_ret) @ r3
|
||||
AR_CLASS(.long 0) @ r3
|
||||
#endif
|
||||
.size __mmap_switched_data, . - __mmap_switched_data
|
||||
|
||||
|
@ -201,6 +201,8 @@ M_CLASS(streq r3, [r12, #PMSAv8_MAIR1])
|
||||
bic r0, r0, #V7M_SCB_CCR_IC
|
||||
#endif
|
||||
str r0, [r12, V7M_SCB_CCR]
|
||||
/* Pass exc_ret to __mmap_switched */
|
||||
mov r0, r10
|
||||
#endif /* CONFIG_CPU_CP15 elif CONFIG_CPU_V7M */
|
||||
ret lr
|
||||
ENDPROC(__after_proc_init)
|
||||
|
@ -462,8 +462,8 @@ static s8 dm365_queue_priority_mapping[][2] = {
|
||||
};
|
||||
|
||||
static const struct dma_slave_map dm365_edma_map[] = {
|
||||
{ "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
|
||||
{ "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
|
||||
{ "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
|
||||
{ "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
|
||||
{ "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) },
|
||||
{ "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) },
|
||||
{ "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
|
||||
|
@ -89,6 +89,13 @@ static struct iommu_platform_data omap3_iommu_pdata = {
|
||||
.reset_name = "mmu",
|
||||
.assert_reset = omap_device_assert_hardreset,
|
||||
.deassert_reset = omap_device_deassert_hardreset,
|
||||
.device_enable = omap_device_enable,
|
||||
.device_idle = omap_device_idle,
|
||||
};
|
||||
|
||||
static struct iommu_platform_data omap3_iommu_isp_pdata = {
|
||||
.device_enable = omap_device_enable,
|
||||
.device_idle = omap_device_idle,
|
||||
};
|
||||
|
||||
static int omap3_sbc_t3730_twl_callback(struct device *dev,
|
||||
@ -424,6 +431,8 @@ static struct iommu_platform_data omap4_iommu_pdata = {
|
||||
.reset_name = "mmu_cache",
|
||||
.assert_reset = omap_device_assert_hardreset,
|
||||
.deassert_reset = omap_device_deassert_hardreset,
|
||||
.device_enable = omap_device_enable,
|
||||
.device_idle = omap_device_idle,
|
||||
};
|
||||
#endif
|
||||
|
||||
@ -617,6 +626,8 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = {
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
OF_DEV_AUXDATA("ti,omap2-iommu", 0x5d000000, "5d000000.mmu",
|
||||
&omap3_iommu_pdata),
|
||||
OF_DEV_AUXDATA("ti,omap2-iommu", 0x480bd400, "480bd400.mmu",
|
||||
&omap3_iommu_isp_pdata),
|
||||
OF_DEV_AUXDATA("ti,omap3-smartreflex-core", 0x480cb000,
|
||||
"480cb000.smartreflex", &omap_sr_pdata[OMAP_SR_CORE]),
|
||||
OF_DEV_AUXDATA("ti,omap3-smartreflex-mpu-iva", 0x480c9000,
|
||||
|
@ -481,14 +481,18 @@ static void sunxi_mc_smp_cpu_die(unsigned int l_cpu)
|
||||
static int sunxi_cpu_powerdown(unsigned int cpu, unsigned int cluster)
|
||||
{
|
||||
u32 reg;
|
||||
int gating_bit = cpu;
|
||||
|
||||
pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu);
|
||||
if (cpu >= SUNXI_CPUS_PER_CLUSTER || cluster >= SUNXI_NR_CLUSTERS)
|
||||
return -EINVAL;
|
||||
|
||||
if (is_a83t && cpu == 0)
|
||||
gating_bit = 4;
|
||||
|
||||
/* gate processor power */
|
||||
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
|
||||
reg |= PRCM_PWROFF_GATING_REG_CORE(cpu);
|
||||
reg |= PRCM_PWROFF_GATING_REG_CORE(gating_bit);
|
||||
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
|
||||
udelay(20);
|
||||
|
||||
|
@ -324,7 +324,7 @@ union offset_union {
|
||||
__put32_unaligned_check("strbt", val, addr)
|
||||
|
||||
static void
|
||||
do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs *regs, union offset_union offset)
|
||||
do_alignment_finish_ldst(unsigned long addr, u32 instr, struct pt_regs *regs, union offset_union offset)
|
||||
{
|
||||
if (!LDST_U_BIT(instr))
|
||||
offset.un = -offset.un;
|
||||
@ -337,7 +337,7 @@ do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs
|
||||
}
|
||||
|
||||
static int
|
||||
do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *regs)
|
||||
do_alignment_ldrhstrh(unsigned long addr, u32 instr, struct pt_regs *regs)
|
||||
{
|
||||
unsigned int rd = RD_BITS(instr);
|
||||
|
||||
@ -386,8 +386,7 @@ do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *r
|
||||
}
|
||||
|
||||
static int
|
||||
do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
|
||||
struct pt_regs *regs)
|
||||
do_alignment_ldrdstrd(unsigned long addr, u32 instr, struct pt_regs *regs)
|
||||
{
|
||||
unsigned int rd = RD_BITS(instr);
|
||||
unsigned int rd2;
|
||||
@ -449,7 +448,7 @@ do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
|
||||
}
|
||||
|
||||
static int
|
||||
do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *regs)
|
||||
do_alignment_ldrstr(unsigned long addr, u32 instr, struct pt_regs *regs)
|
||||
{
|
||||
unsigned int rd = RD_BITS(instr);
|
||||
|
||||
@ -498,7 +497,7 @@ do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *reg
|
||||
* PU = 10 A B
|
||||
*/
|
||||
static int
|
||||
do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *regs)
|
||||
do_alignment_ldmstm(unsigned long addr, u32 instr, struct pt_regs *regs)
|
||||
{
|
||||
unsigned int rd, rn, correction, nr_regs, regbits;
|
||||
unsigned long eaddr, newaddr;
|
||||
@ -539,7 +538,7 @@ do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *reg
|
||||
* processor for us.
|
||||
*/
|
||||
if (addr != eaddr) {
|
||||
pr_err("LDMSTM: PC = %08lx, instr = %08lx, "
|
||||
pr_err("LDMSTM: PC = %08lx, instr = %08x, "
|
||||
"addr = %08lx, eaddr = %08lx\n",
|
||||
instruction_pointer(regs), instr, addr, eaddr);
|
||||
show_regs(regs);
|
||||
@ -716,10 +715,10 @@ thumb2arm(u16 tinstr)
|
||||
* 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt)
|
||||
*/
|
||||
static void *
|
||||
do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs,
|
||||
do_alignment_t32_to_handler(u32 *pinstr, struct pt_regs *regs,
|
||||
union offset_union *poffset)
|
||||
{
|
||||
unsigned long instr = *pinstr;
|
||||
u32 instr = *pinstr;
|
||||
u16 tinst1 = (instr >> 16) & 0xffff;
|
||||
u16 tinst2 = instr & 0xffff;
|
||||
|
||||
@ -767,17 +766,48 @@ do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs,
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int alignment_get_arm(struct pt_regs *regs, u32 *ip, u32 *inst)
|
||||
{
|
||||
u32 instr = 0;
|
||||
int fault;
|
||||
|
||||
if (user_mode(regs))
|
||||
fault = get_user(instr, ip);
|
||||
else
|
||||
fault = probe_kernel_address(ip, instr);
|
||||
|
||||
*inst = __mem_to_opcode_arm(instr);
|
||||
|
||||
return fault;
|
||||
}
|
||||
|
||||
static int alignment_get_thumb(struct pt_regs *regs, u16 *ip, u16 *inst)
|
||||
{
|
||||
u16 instr = 0;
|
||||
int fault;
|
||||
|
||||
if (user_mode(regs))
|
||||
fault = get_user(instr, ip);
|
||||
else
|
||||
fault = probe_kernel_address(ip, instr);
|
||||
|
||||
*inst = __mem_to_opcode_thumb16(instr);
|
||||
|
||||
return fault;
|
||||
}
|
||||
|
||||
static int
|
||||
do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
|
||||
{
|
||||
union offset_union uninitialized_var(offset);
|
||||
unsigned long instr = 0, instrptr;
|
||||
int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs);
|
||||
unsigned long instrptr;
|
||||
int (*handler)(unsigned long addr, u32 instr, struct pt_regs *regs);
|
||||
unsigned int type;
|
||||
unsigned int fault;
|
||||
u32 instr = 0;
|
||||
u16 tinstr = 0;
|
||||
int isize = 4;
|
||||
int thumb2_32b = 0;
|
||||
int fault;
|
||||
|
||||
if (interrupts_enabled(regs))
|
||||
local_irq_enable();
|
||||
@ -786,15 +816,14 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
|
||||
|
||||
if (thumb_mode(regs)) {
|
||||
u16 *ptr = (u16 *)(instrptr & ~1);
|
||||
fault = probe_kernel_address(ptr, tinstr);
|
||||
tinstr = __mem_to_opcode_thumb16(tinstr);
|
||||
|
||||
fault = alignment_get_thumb(regs, ptr, &tinstr);
|
||||
if (!fault) {
|
||||
if (cpu_architecture() >= CPU_ARCH_ARMv7 &&
|
||||
IS_T32(tinstr)) {
|
||||
/* Thumb-2 32-bit */
|
||||
u16 tinst2 = 0;
|
||||
fault = probe_kernel_address(ptr + 1, tinst2);
|
||||
tinst2 = __mem_to_opcode_thumb16(tinst2);
|
||||
u16 tinst2;
|
||||
fault = alignment_get_thumb(regs, ptr + 1, &tinst2);
|
||||
instr = __opcode_thumb32_compose(tinstr, tinst2);
|
||||
thumb2_32b = 1;
|
||||
} else {
|
||||
@ -803,8 +832,7 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
|
||||
}
|
||||
}
|
||||
} else {
|
||||
fault = probe_kernel_address((void *)instrptr, instr);
|
||||
instr = __mem_to_opcode_arm(instr);
|
||||
fault = alignment_get_arm(regs, (void *)instrptr, &instr);
|
||||
}
|
||||
|
||||
if (fault) {
|
||||
@ -926,7 +954,7 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
|
||||
* Oops, we didn't handle the instruction.
|
||||
*/
|
||||
pr_err("Alignment trap: not handling instruction "
|
||||
"%0*lx at [<%08lx>]\n",
|
||||
"%0*x at [<%08lx>]\n",
|
||||
isize << 1,
|
||||
isize == 2 ? tinstr : instr, instrptr);
|
||||
ai_skipped += 1;
|
||||
@ -936,7 +964,7 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
|
||||
ai_user += 1;
|
||||
|
||||
if (ai_usermode & UM_WARN)
|
||||
printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
|
||||
printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*x "
|
||||
"Address=0x%08lx FSR 0x%03x\n", current->comm,
|
||||
task_pid_nr(current), instrptr,
|
||||
isize << 1,
|
||||
|
@ -132,13 +132,11 @@ __v7m_setup_cont:
|
||||
dsb
|
||||
mov r6, lr @ save LR
|
||||
ldr sp, =init_thread_union + THREAD_START_SP
|
||||
stmia sp, {r0-r3, r12}
|
||||
cpsie i
|
||||
svc #0
|
||||
1: cpsid i
|
||||
ldr r0, =exc_ret
|
||||
orr lr, lr, #EXC_RET_THREADMODE_PROCESSSTACK
|
||||
str lr, [r0]
|
||||
/* Calculate exc_ret */
|
||||
orr r10, lr, #EXC_RET_THREADMODE_PROCESSSTACK
|
||||
ldmia sp, {r0-r3, r12}
|
||||
str r5, [r12, #11 * 4] @ restore the original SVC vector entry
|
||||
mov lr, r6 @ restore LR
|
||||
|
@ -63,3 +63,12 @@
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
®_dc1sw {
|
||||
/*
|
||||
* Ethernet PHY needs 30ms to properly power up and some more
|
||||
* to initialize. 100ms should be plenty of time to finish
|
||||
* whole process.
|
||||
*/
|
||||
regulator-enable-ramp-delay = <100000>;
|
||||
};
|
||||
|
@ -159,6 +159,12 @@
|
||||
};
|
||||
|
||||
®_dc1sw {
|
||||
/*
|
||||
* Ethernet PHY needs 30ms to properly power up and some more
|
||||
* to initialize. 100ms should be plenty of time to finish
|
||||
* whole process.
|
||||
*/
|
||||
regulator-enable-ramp-delay = <100000>;
|
||||
regulator-name = "vcc-phy";
|
||||
};
|
||||
|
||||
|
@ -142,15 +142,6 @@
|
||||
clock-output-names = "ext-osc32k";
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
|
@ -42,13 +42,14 @@
|
||||
|
||||
pinmux: pinmux@14029c {
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0x0014029c 0x250>;
|
||||
reg = <0x0014029c 0x26c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xf>;
|
||||
pinctrl-single,gpio-range = <
|
||||
&range 0 154 MODE_GPIO
|
||||
&range 0 91 MODE_GPIO
|
||||
&range 95 60 MODE_GPIO
|
||||
>;
|
||||
range: gpio-range {
|
||||
#pinctrl-single,gpio-range-cells = <3>;
|
||||
|
@ -464,8 +464,7 @@
|
||||
<&pinmux 108 16 27>,
|
||||
<&pinmux 135 77 6>,
|
||||
<&pinmux 141 67 4>,
|
||||
<&pinmux 145 149 6>,
|
||||
<&pinmux 151 91 4>;
|
||||
<&pinmux 145 149 6>;
|
||||
};
|
||||
|
||||
i2c1: i2c@e0000 {
|
||||
|
@ -127,7 +127,7 @@
|
||||
status = "okay";
|
||||
|
||||
i2c-mux@77 {
|
||||
compatible = "nxp,pca9847";
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x77>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
@ -33,7 +33,7 @@
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster0_l2>;
|
||||
cpu-idle-states = <&cpu_pw20>;
|
||||
cpu-idle-states = <&cpu_pw15>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
@ -49,7 +49,7 @@
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster0_l2>;
|
||||
cpu-idle-states = <&cpu_pw20>;
|
||||
cpu-idle-states = <&cpu_pw15>;
|
||||
};
|
||||
|
||||
cpu@100 {
|
||||
@ -65,7 +65,7 @@
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster1_l2>;
|
||||
cpu-idle-states = <&cpu_pw20>;
|
||||
cpu-idle-states = <&cpu_pw15>;
|
||||
};
|
||||
|
||||
cpu@101 {
|
||||
@ -81,7 +81,7 @@
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster1_l2>;
|
||||
cpu-idle-states = <&cpu_pw20>;
|
||||
cpu-idle-states = <&cpu_pw15>;
|
||||
};
|
||||
|
||||
cpu@200 {
|
||||
@ -97,7 +97,7 @@
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster2_l2>;
|
||||
cpu-idle-states = <&cpu_pw20>;
|
||||
cpu-idle-states = <&cpu_pw15>;
|
||||
};
|
||||
|
||||
cpu@201 {
|
||||
@ -113,7 +113,7 @@
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster2_l2>;
|
||||
cpu-idle-states = <&cpu_pw20>;
|
||||
cpu-idle-states = <&cpu_pw15>;
|
||||
};
|
||||
|
||||
cpu@300 {
|
||||
@ -129,7 +129,7 @@
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster3_l2>;
|
||||
cpu-idle-states = <&cpu_pw20>;
|
||||
cpu-idle-states = <&cpu_pw15>;
|
||||
};
|
||||
|
||||
cpu@301 {
|
||||
@ -145,7 +145,7 @@
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster3_l2>;
|
||||
cpu-idle-states = <&cpu_pw20>;
|
||||
cpu-idle-states = <&cpu_pw15>;
|
||||
};
|
||||
|
||||
cpu@400 {
|
||||
@ -161,7 +161,7 @@
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster4_l2>;
|
||||
cpu-idle-states = <&cpu_pw20>;
|
||||
cpu-idle-states = <&cpu_pw15>;
|
||||
};
|
||||
|
||||
cpu@401 {
|
||||
@ -177,7 +177,7 @@
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster4_l2>;
|
||||
cpu-idle-states = <&cpu_pw20>;
|
||||
cpu-idle-states = <&cpu_pw15>;
|
||||
};
|
||||
|
||||
cpu@500 {
|
||||
@ -193,7 +193,7 @@
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster5_l2>;
|
||||
cpu-idle-states = <&cpu_pw20>;
|
||||
cpu-idle-states = <&cpu_pw15>;
|
||||
};
|
||||
|
||||
cpu@501 {
|
||||
@ -209,7 +209,7 @@
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster5_l2>;
|
||||
cpu-idle-states = <&cpu_pw20>;
|
||||
cpu-idle-states = <&cpu_pw15>;
|
||||
};
|
||||
|
||||
cpu@600 {
|
||||
@ -225,7 +225,7 @@
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster6_l2>;
|
||||
cpu-idle-states = <&cpu_pw20>;
|
||||
cpu-idle-states = <&cpu_pw15>;
|
||||
};
|
||||
|
||||
cpu@601 {
|
||||
@ -241,7 +241,7 @@
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster6_l2>;
|
||||
cpu-idle-states = <&cpu_pw20>;
|
||||
cpu-idle-states = <&cpu_pw15>;
|
||||
};
|
||||
|
||||
cpu@700 {
|
||||
@ -257,7 +257,7 @@
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster7_l2>;
|
||||
cpu-idle-states = <&cpu_pw20>;
|
||||
cpu-idle-states = <&cpu_pw15>;
|
||||
};
|
||||
|
||||
cpu@701 {
|
||||
@ -273,7 +273,7 @@
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster7_l2>;
|
||||
cpu-idle-states = <&cpu_pw20>;
|
||||
cpu-idle-states = <&cpu_pw15>;
|
||||
};
|
||||
|
||||
cluster0_l2: l2-cache0 {
|
||||
@ -340,9 +340,9 @@
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
cpu_pw20: cpu-pw20 {
|
||||
cpu_pw15: cpu-pw15 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "PW20";
|
||||
idle-state-name = "PW15";
|
||||
arm,psci-suspend-param = <0x0>;
|
||||
entry-latency-us = <2000>;
|
||||
exit-latency-us = <2000>;
|
||||
|
@ -394,7 +394,7 @@
|
||||
};
|
||||
|
||||
sdma2: dma-controller@302c0000 {
|
||||
compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
|
||||
compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
|
||||
reg = <0x302c0000 0x10000>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
|
||||
@ -405,7 +405,7 @@
|
||||
};
|
||||
|
||||
sdma3: dma-controller@302b0000 {
|
||||
compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
|
||||
compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
|
||||
reg = <0x302b0000 0x10000>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
|
||||
@ -694,7 +694,7 @@
|
||||
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b40000 0x10000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_DUMMY>,
|
||||
clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
|
||||
<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MM_CLK_USDHC1_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
@ -710,7 +710,7 @@
|
||||
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b50000 0x10000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_DUMMY>,
|
||||
clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
|
||||
<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MM_CLK_USDHC2_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
@ -724,7 +724,7 @@
|
||||
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b60000 0x10000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_DUMMY>,
|
||||
clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
|
||||
<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MM_CLK_USDHC3_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
@ -737,7 +737,7 @@
|
||||
};
|
||||
|
||||
sdma1: dma-controller@30bd0000 {
|
||||
compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
|
||||
compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
|
||||
reg = <0x30bd0000 0x10000>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
|
||||
|
@ -288,7 +288,7 @@
|
||||
};
|
||||
|
||||
sdma3: dma-controller@302b0000 {
|
||||
compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
|
||||
compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
|
||||
reg = <0x302b0000 0x10000>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
|
||||
@ -299,7 +299,7 @@
|
||||
};
|
||||
|
||||
sdma2: dma-controller@302c0000 {
|
||||
compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
|
||||
compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
|
||||
reg = <0x302c0000 0x10000>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
|
||||
@ -569,7 +569,7 @@
|
||||
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b40000 0x10000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_DUMMY>,
|
||||
clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
|
||||
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MN_CLK_USDHC1_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
@ -585,7 +585,7 @@
|
||||
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b50000 0x10000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_DUMMY>,
|
||||
clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
|
||||
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MN_CLK_USDHC2_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
@ -599,7 +599,7 @@
|
||||
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b60000 0x10000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_DUMMY>,
|
||||
clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
|
||||
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MN_CLK_USDHC3_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
@ -612,7 +612,7 @@
|
||||
};
|
||||
|
||||
sdma1: dma-controller@30bd0000 {
|
||||
compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
|
||||
compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
|
||||
reg = <0x30bd0000 0x10000>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
|
||||
|
@ -88,9 +88,9 @@
|
||||
regulator-name = "0V9_ARM";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
|
||||
states = <1000000 0x0
|
||||
900000 0x1>;
|
||||
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
|
||||
states = <1000000 0x1
|
||||
900000 0x0>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
@ -850,7 +850,7 @@
|
||||
"fsl,imx7d-usdhc";
|
||||
reg = <0x30b40000 0x10000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_DUMMY>,
|
||||
clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
|
||||
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MQ_CLK_USDHC1_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
@ -867,7 +867,7 @@
|
||||
"fsl,imx7d-usdhc";
|
||||
reg = <0x30b50000 0x10000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_DUMMY>,
|
||||
clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
|
||||
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MQ_CLK_USDHC2_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
|
@ -60,11 +60,6 @@
|
||||
gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
usb3_phy: usb3-phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
vcc-supply = <&exp_usb3_vbus>;
|
||||
};
|
||||
|
||||
vsdc_reg: vsdc-reg {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "vsdc";
|
||||
@ -255,10 +250,16 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&comphy2 {
|
||||
connector {
|
||||
compatible = "usb-a-connector";
|
||||
phy-supply = <&exp_usb3_vbus>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb3 {
|
||||
status = "okay";
|
||||
phys = <&comphy2 0>;
|
||||
usb-phy = <&usb3_phy>;
|
||||
};
|
||||
|
||||
&mdio {
|
||||
|
@ -44,7 +44,7 @@
|
||||
power-supply = <&pp3300_disp>;
|
||||
|
||||
panel-timing {
|
||||
clock-frequency = <266604720>;
|
||||
clock-frequency = <266666667>;
|
||||
hactive = <2400>;
|
||||
hfront-porch = <48>;
|
||||
hback-porch = <84>;
|
||||
|
@ -644,7 +644,7 @@
|
||||
status = "okay";
|
||||
|
||||
u2phy0_host: host-port {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
phy-supply = <&vcc5v0_typec>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -712,7 +712,7 @@
|
||||
|
||||
&usbdrd_dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "otg";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usbdrd3_1 {
|
||||
|
@ -173,7 +173,7 @@
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-max-microvolt = <1700000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
};
|
||||
@ -247,8 +247,8 @@
|
||||
rk808: pmic@1b {
|
||||
compatible = "rockchip,rk808";
|
||||
reg = <0x1b>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "xin32k", "rk808-clkout2";
|
||||
pinctrl-names = "default";
|
||||
@ -574,7 +574,7 @@
|
||||
|
||||
pmic {
|
||||
pmic_int_l: pmic-int-l {
|
||||
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
vsel1_gpio: vsel1-gpio {
|
||||
@ -624,7 +624,6 @@
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
@ -636,8 +635,7 @@
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
mmc-hs200-1_8v;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -79,6 +79,7 @@
|
||||
#define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3
|
||||
#define CAVIUM_CPU_PART_THUNDERX2 0x0AF
|
||||
|
||||
#define BRCM_CPU_PART_BRAHMA_B53 0x100
|
||||
#define BRCM_CPU_PART_VULCAN 0x516
|
||||
|
||||
#define QCOM_CPU_PART_FALKOR_V1 0x800
|
||||
@ -105,6 +106,7 @@
|
||||
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
|
||||
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
|
||||
#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)
|
||||
#define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53)
|
||||
#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
|
||||
#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
|
||||
#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
|
||||
|
@ -32,11 +32,11 @@
|
||||
#define PROT_DEFAULT (_PROT_DEFAULT | PTE_MAYBE_NG)
|
||||
#define PROT_SECT_DEFAULT (_PROT_SECT_DEFAULT | PMD_MAYBE_NG)
|
||||
|
||||
#define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
|
||||
#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
|
||||
#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
|
||||
#define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
|
||||
#define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
|
||||
#define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
|
||||
#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
|
||||
#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
|
||||
#define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
|
||||
#define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
|
||||
|
||||
#define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
|
||||
#define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
|
||||
@ -80,8 +80,9 @@
|
||||
#define PAGE_S2_DEVICE __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_S2_XN)
|
||||
|
||||
#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
|
||||
#define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
|
||||
#define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
|
||||
/* shared+writable pages are clean by default, hence PTE_RDONLY|PTE_WRITE */
|
||||
#define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
|
||||
#define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_WRITE)
|
||||
#define PAGE_READONLY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
|
||||
#define PAGE_READONLY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN)
|
||||
#define PAGE_EXECONLY __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PTE_PXN)
|
||||
|
@ -283,23 +283,6 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
|
||||
set_pte(ptep, pte);
|
||||
}
|
||||
|
||||
#define __HAVE_ARCH_PTE_SAME
|
||||
static inline int pte_same(pte_t pte_a, pte_t pte_b)
|
||||
{
|
||||
pteval_t lhs, rhs;
|
||||
|
||||
lhs = pte_val(pte_a);
|
||||
rhs = pte_val(pte_b);
|
||||
|
||||
if (pte_present(pte_a))
|
||||
lhs &= ~PTE_RDONLY;
|
||||
|
||||
if (pte_present(pte_b))
|
||||
rhs &= ~PTE_RDONLY;
|
||||
|
||||
return (lhs == rhs);
|
||||
}
|
||||
|
||||
/*
|
||||
* Huge pte definitions.
|
||||
*/
|
||||
|
@ -30,13 +30,6 @@ int __arm64_get_clock_mode(struct timekeeper *tk)
|
||||
}
|
||||
#define __arch_get_clock_mode __arm64_get_clock_mode
|
||||
|
||||
static __always_inline
|
||||
int __arm64_use_vsyscall(struct vdso_data *vdata)
|
||||
{
|
||||
return !vdata[CS_HRES_COARSE].clock_mode;
|
||||
}
|
||||
#define __arch_use_vsyscall __arm64_use_vsyscall
|
||||
|
||||
static __always_inline
|
||||
void __arm64_update_vsyscall(struct vdso_data *vdata, struct timekeeper *tk)
|
||||
{
|
||||
|
@ -489,6 +489,7 @@ static const struct midr_range arm64_ssb_cpus[] = {
|
||||
MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
|
||||
MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
|
||||
MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
|
||||
MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
|
||||
{},
|
||||
};
|
||||
|
||||
@ -573,6 +574,7 @@ static const struct midr_range spectre_v2_safe_list[] = {
|
||||
MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
|
||||
MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
|
||||
MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
|
||||
MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
@ -659,17 +661,23 @@ static const struct midr_range arm64_harden_el2_vectors[] = {
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
|
||||
|
||||
static const struct midr_range arm64_repeat_tlbi_cpus[] = {
|
||||
static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
|
||||
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
|
||||
MIDR_RANGE(MIDR_QCOM_FALKOR_V1, 0, 0, 0, 0),
|
||||
{
|
||||
ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0)
|
||||
},
|
||||
{
|
||||
.midr_range.model = MIDR_QCOM_KRYO,
|
||||
.matches = is_kryo_midr,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARM64_ERRATUM_1286807
|
||||
MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
|
||||
{
|
||||
ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
|
||||
},
|
||||
#endif
|
||||
{},
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CAVIUM_ERRATUM_27456
|
||||
@ -737,6 +745,33 @@ static const struct midr_range erratum_1418040_list[] = {
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARM64_ERRATUM_845719
|
||||
static const struct midr_range erratum_845719_list[] = {
|
||||
/* Cortex-A53 r0p[01234] */
|
||||
MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
|
||||
/* Brahma-B53 r0p[0] */
|
||||
MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
|
||||
{},
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARM64_ERRATUM_843419
|
||||
static const struct arm64_cpu_capabilities erratum_843419_list[] = {
|
||||
{
|
||||
/* Cortex-A53 r0p[01234] */
|
||||
.matches = is_affected_midr_range,
|
||||
ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
|
||||
MIDR_FIXED(0x4, BIT(8)),
|
||||
},
|
||||
{
|
||||
/* Brahma-B53 r0p[0] */
|
||||
.matches = is_affected_midr_range,
|
||||
ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
|
||||
},
|
||||
{},
|
||||
};
|
||||
#endif
|
||||
|
||||
const struct arm64_cpu_capabilities arm64_errata[] = {
|
||||
#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
|
||||
{
|
||||
@ -768,19 +803,18 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
|
||||
#endif
|
||||
#ifdef CONFIG_ARM64_ERRATUM_843419
|
||||
{
|
||||
/* Cortex-A53 r0p[01234] */
|
||||
.desc = "ARM erratum 843419",
|
||||
.capability = ARM64_WORKAROUND_843419,
|
||||
ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
|
||||
MIDR_FIXED(0x4, BIT(8)),
|
||||
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
||||
.matches = cpucap_multi_entry_cap_matches,
|
||||
.match_list = erratum_843419_list,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARM64_ERRATUM_845719
|
||||
{
|
||||
/* Cortex-A53 r0p[01234] */
|
||||
.desc = "ARM erratum 845719",
|
||||
.capability = ARM64_WORKAROUND_845719,
|
||||
ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
|
||||
ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CAVIUM_ERRATUM_23154
|
||||
@ -816,6 +850,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
|
||||
{
|
||||
.desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
|
||||
.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
|
||||
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
||||
.matches = cpucap_multi_entry_cap_matches,
|
||||
.match_list = qcom_erratum_1003_list,
|
||||
},
|
||||
@ -824,7 +859,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
|
||||
{
|
||||
.desc = "Qualcomm erratum 1009, ARM erratum 1286807",
|
||||
.capability = ARM64_WORKAROUND_REPEAT_TLBI,
|
||||
ERRATA_MIDR_RANGE_LIST(arm64_repeat_tlbi_cpus),
|
||||
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
||||
.matches = cpucap_multi_entry_cap_matches,
|
||||
.match_list = arm64_repeat_tlbi_list,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARM64_ERRATUM_858921
|
||||
|
@ -632,6 +632,8 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
|
||||
*/
|
||||
val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
|
||||
| (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
|
||||
if (!system_supports_32bit_el0())
|
||||
val |= ARMV8_PMU_PMCR_LC;
|
||||
__vcpu_sys_reg(vcpu, r->reg) = val;
|
||||
}
|
||||
|
||||
@ -682,6 +684,8 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
|
||||
val = __vcpu_sys_reg(vcpu, PMCR_EL0);
|
||||
val &= ~ARMV8_PMU_PMCR_MASK;
|
||||
val |= p->regval & ARMV8_PMU_PMCR_MASK;
|
||||
if (!system_supports_32bit_el0())
|
||||
val |= ARMV8_PMU_PMCR_LC;
|
||||
__vcpu_sys_reg(vcpu, PMCR_EL0) = val;
|
||||
kvm_pmu_handle_pmcr(vcpu, val);
|
||||
kvm_vcpu_pmu_restore_guest(vcpu);
|
||||
|
@ -84,7 +84,7 @@ void __init prom_init(void)
|
||||
* Here we will start up CPU1 in the background and ask it to
|
||||
* reconfigure itself then go back to sleep.
|
||||
*/
|
||||
memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
|
||||
memcpy((void *)0xa0000200, bmips_smp_movevec, 0x20);
|
||||
__sync();
|
||||
set_c0_cause(C_SW0);
|
||||
cpumask_set_cpu(1, &bmips_booted_mask);
|
||||
|
@ -75,11 +75,11 @@ static inline int register_bmips_smp_ops(void)
|
||||
#endif
|
||||
}
|
||||
|
||||
extern char bmips_reset_nmi_vec;
|
||||
extern char bmips_reset_nmi_vec_end;
|
||||
extern char bmips_smp_movevec;
|
||||
extern char bmips_smp_int_vec;
|
||||
extern char bmips_smp_int_vec_end;
|
||||
extern char bmips_reset_nmi_vec[];
|
||||
extern char bmips_reset_nmi_vec_end[];
|
||||
extern char bmips_smp_movevec[];
|
||||
extern char bmips_smp_int_vec[];
|
||||
extern char bmips_smp_int_vec_end[];
|
||||
|
||||
extern int bmips_smp_enabled;
|
||||
extern int bmips_cpu_offset;
|
||||
|
@ -24,6 +24,8 @@
|
||||
|
||||
#define VDSO_HAS_CLOCK_GETRES 1
|
||||
|
||||
#define __VDSO_USE_SYSCALL ULLONG_MAX
|
||||
|
||||
#ifdef CONFIG_MIPS_CLOCK_VSYSCALL
|
||||
|
||||
static __always_inline long gettimeofday_fallback(
|
||||
@ -205,7 +207,7 @@ static __always_inline u64 __arch_get_hw_counter(s32 clock_mode)
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
cycle_now = 0;
|
||||
cycle_now = __VDSO_USE_SYSCALL;
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -28,13 +28,6 @@ int __mips_get_clock_mode(struct timekeeper *tk)
|
||||
}
|
||||
#define __arch_get_clock_mode __mips_get_clock_mode
|
||||
|
||||
static __always_inline
|
||||
int __mips_use_vsyscall(struct vdso_data *vdata)
|
||||
{
|
||||
return (vdata[CS_HRES_COARSE].clock_mode != VDSO_CLOCK_NONE);
|
||||
}
|
||||
#define __arch_use_vsyscall __mips_use_vsyscall
|
||||
|
||||
/* The asm-generic header needs to be included after the definitions above */
|
||||
#include <asm-generic/vdso/vsyscall.h>
|
||||
|
||||
|
@ -464,10 +464,10 @@ static void bmips_wr_vec(unsigned long dst, char *start, char *end)
|
||||
|
||||
static inline void bmips_nmi_handler_setup(void)
|
||||
{
|
||||
bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec,
|
||||
&bmips_reset_nmi_vec_end);
|
||||
bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec,
|
||||
&bmips_smp_int_vec_end);
|
||||
bmips_wr_vec(BMIPS_NMI_RESET_VEC, bmips_reset_nmi_vec,
|
||||
bmips_reset_nmi_vec_end);
|
||||
bmips_wr_vec(BMIPS_WARM_RESTART_VEC, bmips_smp_int_vec,
|
||||
bmips_smp_int_vec_end);
|
||||
}
|
||||
|
||||
struct reset_vec_info {
|
||||
|
@ -653,6 +653,13 @@ static void build_restore_pagemask(u32 **p, struct uasm_reloc **r,
|
||||
int restore_scratch)
|
||||
{
|
||||
if (restore_scratch) {
|
||||
/*
|
||||
* Ensure the MFC0 below observes the value written to the
|
||||
* KScratch register by the prior MTC0.
|
||||
*/
|
||||
if (scratch_reg >= 0)
|
||||
uasm_i_ehb(p);
|
||||
|
||||
/* Reset default page size */
|
||||
if (PM_DEFAULT_MASK >> 16) {
|
||||
uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
|
||||
@ -667,12 +674,10 @@ static void build_restore_pagemask(u32 **p, struct uasm_reloc **r,
|
||||
uasm_i_mtc0(p, 0, C0_PAGEMASK);
|
||||
uasm_il_b(p, r, lid);
|
||||
}
|
||||
if (scratch_reg >= 0) {
|
||||
uasm_i_ehb(p);
|
||||
if (scratch_reg >= 0)
|
||||
UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
|
||||
} else {
|
||||
else
|
||||
UASM_i_LW(p, 1, scratchpad_offset(0), 0);
|
||||
}
|
||||
} else {
|
||||
/* Reset default page size */
|
||||
if (PM_DEFAULT_MASK >> 16) {
|
||||
@ -921,6 +926,10 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
|
||||
}
|
||||
if (mode != not_refill && check_for_high_segbits) {
|
||||
uasm_l_large_segbits_fault(l, *p);
|
||||
|
||||
if (mode == refill_scratch && scratch_reg >= 0)
|
||||
uasm_i_ehb(p);
|
||||
|
||||
/*
|
||||
* We get here if we are an xsseg address, or if we are
|
||||
* an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
|
||||
@ -939,12 +948,10 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
|
||||
uasm_i_jr(p, ptr);
|
||||
|
||||
if (mode == refill_scratch) {
|
||||
if (scratch_reg >= 0) {
|
||||
uasm_i_ehb(p);
|
||||
if (scratch_reg >= 0)
|
||||
UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
|
||||
} else {
|
||||
else
|
||||
UASM_i_LW(p, 1, scratchpad_offset(0), 0);
|
||||
}
|
||||
} else {
|
||||
uasm_i_nop(p);
|
||||
}
|
||||
|
@ -2125,7 +2125,7 @@ ftrace_regs_caller:
|
||||
copy %rp, %r26
|
||||
LDREG -FTRACE_FRAME_SIZE-PT_SZ_ALGN(%sp), %r25
|
||||
ldo -8(%r25), %r25
|
||||
copy %r3, %arg2
|
||||
ldo -FTRACE_FRAME_SIZE(%r1), %arg2
|
||||
b,l ftrace_function_trampoline, %rp
|
||||
copy %r1, %arg3 /* struct pt_regs */
|
||||
|
||||
|
@ -91,6 +91,7 @@
|
||||
|
||||
static inline void kuap_update_sr(u32 sr, u32 addr, u32 end)
|
||||
{
|
||||
addr &= 0xf0000000; /* align addr to start of segment */
|
||||
barrier(); /* make sure thread.kuap is updated before playing with SRs */
|
||||
while (addr < end) {
|
||||
mtsrin(sr, addr);
|
||||
|
@ -175,4 +175,7 @@ do { \
|
||||
ARCH_DLINFO_CACHE_GEOMETRY; \
|
||||
} while (0)
|
||||
|
||||
/* Relocate the kernel image to @final_address */
|
||||
void relocate(unsigned long final_address);
|
||||
|
||||
#endif /* _ASM_POWERPC_ELF_H */
|
||||
|
@ -3249,7 +3249,20 @@ static void setup_secure_guest(unsigned long kbase, unsigned long fdt)
|
||||
/* Switch to secure mode. */
|
||||
prom_printf("Switching to secure mode.\n");
|
||||
|
||||
/*
|
||||
* The ultravisor will do an integrity check of the kernel image but we
|
||||
* relocated it so the check will fail. Restore the original image by
|
||||
* relocating it back to the kernel virtual base address.
|
||||
*/
|
||||
if (IS_ENABLED(CONFIG_RELOCATABLE))
|
||||
relocate(KERNELBASE);
|
||||
|
||||
ret = enter_secure_mode(kbase, fdt);
|
||||
|
||||
/* Relocate the kernel again. */
|
||||
if (IS_ENABLED(CONFIG_RELOCATABLE))
|
||||
relocate(kbase);
|
||||
|
||||
if (ret != U_SUCCESS) {
|
||||
prom_printf("Returned %d from switching to secure mode.\n", ret);
|
||||
prom_rtas_os_term("Switch to secure mode failed.\n");
|
||||
|
@ -26,7 +26,8 @@ _end enter_prom $MEM_FUNCS reloc_offset __secondary_hold
|
||||
__secondary_hold_acknowledge __secondary_hold_spinloop __start
|
||||
logo_linux_clut224 btext_prepare_BAT
|
||||
reloc_got2 kernstart_addr memstart_addr linux_banner _stext
|
||||
__prom_init_toc_start __prom_init_toc_end btext_setup_display TOC."
|
||||
__prom_init_toc_start __prom_init_toc_end btext_setup_display TOC.
|
||||
relocate"
|
||||
|
||||
NM="$1"
|
||||
OBJ="$2"
|
||||
|
@ -1217,6 +1217,7 @@ int kvmppc_xive_connect_vcpu(struct kvm_device *dev,
|
||||
struct kvmppc_xive *xive = dev->private;
|
||||
struct kvmppc_xive_vcpu *xc;
|
||||
int i, r = -EBUSY;
|
||||
u32 vp_id;
|
||||
|
||||
pr_devel("connect_vcpu(cpu=%d)\n", cpu);
|
||||
|
||||
@ -1228,25 +1229,32 @@ int kvmppc_xive_connect_vcpu(struct kvm_device *dev,
|
||||
return -EPERM;
|
||||
if (vcpu->arch.irq_type != KVMPPC_IRQ_DEFAULT)
|
||||
return -EBUSY;
|
||||
if (kvmppc_xive_find_server(vcpu->kvm, cpu)) {
|
||||
pr_devel("Duplicate !\n");
|
||||
return -EEXIST;
|
||||
}
|
||||
if (cpu >= (KVM_MAX_VCPUS * vcpu->kvm->arch.emul_smt_mode)) {
|
||||
pr_devel("Out of bounds !\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
xc = kzalloc(sizeof(*xc), GFP_KERNEL);
|
||||
if (!xc)
|
||||
return -ENOMEM;
|
||||
|
||||
/* We need to synchronize with queue provisioning */
|
||||
mutex_lock(&xive->lock);
|
||||
|
||||
vp_id = kvmppc_xive_vp(xive, cpu);
|
||||
if (kvmppc_xive_vp_in_use(xive->kvm, vp_id)) {
|
||||
pr_devel("Duplicate !\n");
|
||||
r = -EEXIST;
|
||||
goto bail;
|
||||
}
|
||||
|
||||
xc = kzalloc(sizeof(*xc), GFP_KERNEL);
|
||||
if (!xc) {
|
||||
r = -ENOMEM;
|
||||
goto bail;
|
||||
}
|
||||
|
||||
vcpu->arch.xive_vcpu = xc;
|
||||
xc->xive = xive;
|
||||
xc->vcpu = vcpu;
|
||||
xc->server_num = cpu;
|
||||
xc->vp_id = kvmppc_xive_vp(xive, cpu);
|
||||
xc->vp_id = vp_id;
|
||||
xc->mfrr = 0xff;
|
||||
xc->valid = true;
|
||||
|
||||
|
@ -220,6 +220,18 @@ static inline u32 kvmppc_xive_vp(struct kvmppc_xive *xive, u32 server)
|
||||
return xive->vp_base + kvmppc_pack_vcpu_id(xive->kvm, server);
|
||||
}
|
||||
|
||||
static inline bool kvmppc_xive_vp_in_use(struct kvm *kvm, u32 vp_id)
|
||||
{
|
||||
struct kvm_vcpu *vcpu = NULL;
|
||||
int i;
|
||||
|
||||
kvm_for_each_vcpu(i, vcpu, kvm) {
|
||||
if (vcpu->arch.xive_vcpu && vp_id == vcpu->arch.xive_vcpu->vp_id)
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
/*
|
||||
* Mapping between guest priorities and host priorities
|
||||
* is as follow.
|
||||
|
@ -106,6 +106,7 @@ int kvmppc_xive_native_connect_vcpu(struct kvm_device *dev,
|
||||
struct kvmppc_xive *xive = dev->private;
|
||||
struct kvmppc_xive_vcpu *xc = NULL;
|
||||
int rc;
|
||||
u32 vp_id;
|
||||
|
||||
pr_devel("native_connect_vcpu(server=%d)\n", server_num);
|
||||
|
||||
@ -124,7 +125,8 @@ int kvmppc_xive_native_connect_vcpu(struct kvm_device *dev,
|
||||
|
||||
mutex_lock(&xive->lock);
|
||||
|
||||
if (kvmppc_xive_find_server(vcpu->kvm, server_num)) {
|
||||
vp_id = kvmppc_xive_vp(xive, server_num);
|
||||
if (kvmppc_xive_vp_in_use(xive->kvm, vp_id)) {
|
||||
pr_devel("Duplicate !\n");
|
||||
rc = -EEXIST;
|
||||
goto bail;
|
||||
@ -141,7 +143,7 @@ int kvmppc_xive_native_connect_vcpu(struct kvm_device *dev,
|
||||
xc->vcpu = vcpu;
|
||||
xc->server_num = server_num;
|
||||
|
||||
xc->vp_id = kvmppc_xive_vp(xive, server_num);
|
||||
xc->vp_id = vp_id;
|
||||
xc->valid = true;
|
||||
vcpu->arch.irq_type = KVMPPC_IRQ_XIVE;
|
||||
|
||||
|
@ -1141,6 +1141,19 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp)
|
||||
goto out_addrs;
|
||||
}
|
||||
|
||||
/*
|
||||
* If we have seen a tail call, we need a second pass.
|
||||
* This is because bpf_jit_emit_common_epilogue() is called
|
||||
* from bpf_jit_emit_tail_call() with a not yet stable ctx->seen.
|
||||
*/
|
||||
if (cgctx.seen & SEEN_TAILCALL) {
|
||||
cgctx.idx = 0;
|
||||
if (bpf_jit_build_body(fp, 0, &cgctx, addrs, false)) {
|
||||
fp = org_fp;
|
||||
goto out_addrs;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Pretend to build prologue, given the features we've seen. This will
|
||||
* update ctgtx.idx as it pretends to output instructions, then we can
|
||||
|
@ -42,7 +42,7 @@ void pnv_pcibios_bus_add_device(struct pci_dev *pdev)
|
||||
{
|
||||
struct pci_dn *pdn = pci_get_pdn(pdev);
|
||||
|
||||
if (eeh_has_flag(EEH_FORCE_DISABLED))
|
||||
if (!pdn || eeh_has_flag(EEH_FORCE_DISABLED))
|
||||
return;
|
||||
|
||||
dev_dbg(&pdev->dev, "EEH: Setting up device\n");
|
||||
|
@ -146,20 +146,25 @@ static int pnv_smp_cpu_disable(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void pnv_flush_interrupts(void)
|
||||
{
|
||||
if (cpu_has_feature(CPU_FTR_ARCH_300)) {
|
||||
if (xive_enabled())
|
||||
xive_flush_interrupt();
|
||||
else
|
||||
icp_opal_flush_interrupt();
|
||||
} else {
|
||||
icp_native_flush_interrupt();
|
||||
}
|
||||
}
|
||||
|
||||
static void pnv_smp_cpu_kill_self(void)
|
||||
{
|
||||
unsigned long srr1, unexpected_mask, wmask;
|
||||
unsigned int cpu;
|
||||
unsigned long srr1, wmask;
|
||||
u64 lpcr_val;
|
||||
|
||||
/* Standard hot unplug procedure */
|
||||
/*
|
||||
* This hard disables local interurpts, ensuring we have no lazy
|
||||
* irqs pending.
|
||||
*/
|
||||
WARN_ON(irqs_disabled());
|
||||
hard_irq_disable();
|
||||
WARN_ON(lazy_irq_pending());
|
||||
|
||||
idle_task_exit();
|
||||
current->active_mm = NULL; /* for sanity */
|
||||
@ -172,6 +177,27 @@ static void pnv_smp_cpu_kill_self(void)
|
||||
if (cpu_has_feature(CPU_FTR_ARCH_207S))
|
||||
wmask = SRR1_WAKEMASK_P8;
|
||||
|
||||
/*
|
||||
* This turns the irq soft-disabled state we're called with, into a
|
||||
* hard-disabled state with pending irq_happened interrupts cleared.
|
||||
*
|
||||
* PACA_IRQ_DEC - Decrementer should be ignored.
|
||||
* PACA_IRQ_HMI - Can be ignored, processing is done in real mode.
|
||||
* PACA_IRQ_DBELL, EE, PMI - Unexpected.
|
||||
*/
|
||||
hard_irq_disable();
|
||||
if (generic_check_cpu_restart(cpu))
|
||||
goto out;
|
||||
|
||||
unexpected_mask = ~(PACA_IRQ_DEC | PACA_IRQ_HMI | PACA_IRQ_HARD_DIS);
|
||||
if (local_paca->irq_happened & unexpected_mask) {
|
||||
if (local_paca->irq_happened & PACA_IRQ_EE)
|
||||
pnv_flush_interrupts();
|
||||
DBG("CPU%d Unexpected exit while offline irq_happened=%lx!\n",
|
||||
cpu, local_paca->irq_happened);
|
||||
}
|
||||
local_paca->irq_happened = PACA_IRQ_HARD_DIS;
|
||||
|
||||
/*
|
||||
* We don't want to take decrementer interrupts while we are
|
||||
* offline, so clear LPCR:PECE1. We keep PECE2 (and
|
||||
@ -197,6 +223,7 @@ static void pnv_smp_cpu_kill_self(void)
|
||||
|
||||
srr1 = pnv_cpu_offline(cpu);
|
||||
|
||||
WARN_ON_ONCE(!irqs_disabled());
|
||||
WARN_ON(lazy_irq_pending());
|
||||
|
||||
/*
|
||||
@ -212,13 +239,7 @@ static void pnv_smp_cpu_kill_self(void)
|
||||
*/
|
||||
if (((srr1 & wmask) == SRR1_WAKEEE) ||
|
||||
((srr1 & wmask) == SRR1_WAKEHVI)) {
|
||||
if (cpu_has_feature(CPU_FTR_ARCH_300)) {
|
||||
if (xive_enabled())
|
||||
xive_flush_interrupt();
|
||||
else
|
||||
icp_opal_flush_interrupt();
|
||||
} else
|
||||
icp_native_flush_interrupt();
|
||||
pnv_flush_interrupts();
|
||||
} else if ((srr1 & wmask) == SRR1_WAKEHDBELL) {
|
||||
unsigned long msg = PPC_DBELL_TYPE(PPC_DBELL_SERVER);
|
||||
asm volatile(PPC_MSGCLR(%0) : : "r" (msg));
|
||||
@ -266,7 +287,7 @@ static void pnv_smp_cpu_kill_self(void)
|
||||
*/
|
||||
lpcr_val = mfspr(SPRN_LPCR) | (u64)LPCR_PECE1;
|
||||
pnv_program_cpu_hotplug_lpcr(cpu, lpcr_val);
|
||||
|
||||
out:
|
||||
DBG("CPU%d coming online...\n", cpu);
|
||||
}
|
||||
|
||||
|
@ -12,7 +12,6 @@
|
||||
|
||||
#include <asm/asm.h>
|
||||
|
||||
#ifdef CONFIG_GENERIC_BUG
|
||||
#define __INSN_LENGTH_MASK _UL(0x3)
|
||||
#define __INSN_LENGTH_32 _UL(0x3)
|
||||
#define __COMPRESSED_INSN_MASK _UL(0xffff)
|
||||
@ -20,7 +19,6 @@
|
||||
#define __BUG_INSN_32 _UL(0x00100073) /* ebreak */
|
||||
#define __BUG_INSN_16 _UL(0x9002) /* c.ebreak */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef u32 bug_insn_t;
|
||||
|
||||
#ifdef CONFIG_GENERIC_BUG_RELATIVE_POINTERS
|
||||
@ -43,6 +41,7 @@ typedef u32 bug_insn_t;
|
||||
RISCV_SHORT " %2"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_GENERIC_BUG
|
||||
#define __BUG_FLAGS(flags) \
|
||||
do { \
|
||||
__asm__ __volatile__ ( \
|
||||
@ -58,14 +57,10 @@ do { \
|
||||
"i" (flags), \
|
||||
"i" (sizeof(struct bug_entry))); \
|
||||
} while (0)
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
#else /* CONFIG_GENERIC_BUG */
|
||||
#ifndef __ASSEMBLY__
|
||||
#define __BUG_FLAGS(flags) do { \
|
||||
__asm__ __volatile__ ("ebreak\n"); \
|
||||
} while (0)
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
#endif /* CONFIG_GENERIC_BUG */
|
||||
|
||||
#define BUG() do { \
|
||||
@ -79,15 +74,10 @@ do { \
|
||||
|
||||
#include <asm-generic/bug.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
struct pt_regs;
|
||||
struct task_struct;
|
||||
|
||||
extern void die(struct pt_regs *regs, const char *str);
|
||||
extern void do_trap(struct pt_regs *regs, int signo, int code,
|
||||
unsigned long addr);
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
void die(struct pt_regs *regs, const char *str);
|
||||
void do_trap(struct pt_regs *regs, int signo, int code, unsigned long addr);
|
||||
|
||||
#endif /* _ASM_RISCV_BUG_H */
|
||||
|
@ -13,6 +13,7 @@
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <asm/mmiowb.h>
|
||||
#include <asm/pgtable.h>
|
||||
|
||||
extern void __iomem *ioremap(phys_addr_t offset, unsigned long size);
|
||||
|
||||
@ -161,6 +162,12 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
|
||||
#define writeq(v,c) ({ __io_bw(); writeq_cpu((v),(c)); __io_aw(); })
|
||||
#endif
|
||||
|
||||
/*
|
||||
* I/O port access constants.
|
||||
*/
|
||||
#define IO_SPACE_LIMIT (PCI_IO_SIZE - 1)
|
||||
#define PCI_IOBASE ((void __iomem *)PCI_IO_START)
|
||||
|
||||
/*
|
||||
* Emulation routines for the port-mapped IO space used by some PCI drivers.
|
||||
* These are defined as being "fully synchronous", but also "not guaranteed to
|
||||
|
@ -7,6 +7,9 @@
|
||||
#ifndef _ASM_RISCV_IRQ_H
|
||||
#define _ASM_RISCV_IRQ_H
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/linkage.h>
|
||||
|
||||
#define NR_IRQS 0
|
||||
|
||||
void riscv_timer_interrupt(void);
|
||||
|
@ -7,6 +7,7 @@
|
||||
#define _ASM_RISCV_PGTABLE_H
|
||||
|
||||
#include <linux/mmzone.h>
|
||||
#include <linux/sizes.h>
|
||||
|
||||
#include <asm/pgtable-bits.h>
|
||||
|
||||
@ -86,6 +87,7 @@ extern pgd_t swapper_pg_dir[];
|
||||
#define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1)
|
||||
#define VMALLOC_END (PAGE_OFFSET - 1)
|
||||
#define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE)
|
||||
#define PCI_IO_SIZE SZ_16M
|
||||
|
||||
/*
|
||||
* Roughly size the vmemmap space to be large enough to fit enough
|
||||
@ -100,7 +102,10 @@ extern pgd_t swapper_pg_dir[];
|
||||
|
||||
#define vmemmap ((struct page *)VMEMMAP_START)
|
||||
|
||||
#define FIXADDR_TOP (VMEMMAP_START)
|
||||
#define PCI_IO_END VMEMMAP_START
|
||||
#define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE)
|
||||
#define FIXADDR_TOP PCI_IO_START
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
#define FIXADDR_SIZE PMD_SIZE
|
||||
#else
|
||||
@ -184,10 +189,7 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
|
||||
return __pte((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
|
||||
}
|
||||
|
||||
static inline pte_t mk_pte(struct page *page, pgprot_t prot)
|
||||
{
|
||||
return pfn_pte(page_to_pfn(page), prot);
|
||||
}
|
||||
#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
|
||||
|
||||
#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
|
||||
|
||||
@ -428,9 +430,7 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
|
||||
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
|
||||
#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
|
||||
|
||||
#ifdef CONFIG_FLATMEM
|
||||
#define kern_addr_valid(addr) (1) /* FIXME */
|
||||
#endif
|
||||
|
||||
extern void *dtb_early_va;
|
||||
extern void setup_bootmem(void);
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user