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[ARM] add Marvell Loki (88RC8480) SoC support

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The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU
core running at between 400 MHz and 1.0 GHz, and features a 64 bit
DDR controller, 512K of internal SRAM, two x4 PCI-Express ports,
two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs,
two TWSI controllers, and IDMA/XOR engines.

This patch adds support for the Marvell LB88RC8480 Development
Board, enabling the use of the PCIe interfaces, the ethernet
interfaces, the TWSI interfaces and the UARTs.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
This commit is contained in:
Lennert Buytenhek 2008-06-22 22:45:02 +02:00
parent 1219715de7
commit 777f9bebad
23 changed files with 975 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/Kconfig
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@ -370,6 +370,14 @@ config ARCH_NS9XXX
<http://www.digi.com/products/microprocessors/index.jsp>
config ARCH_LOKI
bool "Marvell Loki (88RC8480)"
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select PLAT_ORION
help
Support for the Marvell Loki (88RC8480) SoC.
config ARCH_MXC
bool "Freescale MXC/iMX-based"
select ARCH_MTD_XIP
@ -508,6 +516,8 @@ source "arch/arm/mach-ixp2000/Kconfig"
source "arch/arm/mach-ixp23xx/Kconfig"
source "arch/arm/mach-loki/Kconfig"
source "arch/arm/mach-pxa/Kconfig"
source "arch/arm/mach-sa1100/Kconfig"

1
arch/arm/Makefile
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@ -140,6 +140,7 @@ endif
machine-$(CONFIG_ARCH_MX3) := mx3
machine-$(CONFIG_ARCH_ORION5X) := orion5x
machine-$(CONFIG_ARCH_MSM7X00A) := msm
machine-$(CONFIG_ARCH_LOKI) := loki
ifeq ($(CONFIG_ARCH_EBSA110),y)
# This is what happens if you forget the IOCS16 line.

13
arch/arm/mach-loki/Kconfig Normal file
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@ -0,0 +1,13 @@
if ARCH_LOKI
menu "Marvell Loki (88RC8480) Implementations"
config MACH_LB88RC8480
bool "Marvell LB88RC8480 Development Board"
help
Say 'Y' here if you want your kernel to support the
Marvell LB88RC8480 Development Board.
endmenu
endif

3
arch/arm/mach-loki/Makefile Normal file
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@ -0,0 +1,3 @@
obj-y += common.o addr-map.o irq.o
obj-$(CONFIG_MACH_LB88RC8480) += lb88rc8480-setup.o

3
arch/arm/mach-loki/Makefile.boot Normal file
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@ -0,0 +1,3 @@
zreladdr-y := 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000

121
arch/arm/mach-loki/addr-map.c Normal file
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@ -0,0 +1,121 @@
/*
* arch/arm/mach-loki/addr-map.c
*
* Address map functions for Marvell Loki (88RC8480) SoCs
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mbus.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include "common.h"
/*
* Generic Address Decode Windows bit settings
*/
#define TARGET_DDR 0
#define TARGET_DEV_BUS 1
#define TARGET_PCIE0 3
#define TARGET_PCIE1 4
#define ATTR_DEV_BOOT 0x0f
#define ATTR_DEV_CS2 0x1b
#define ATTR_DEV_CS1 0x1d
#define ATTR_DEV_CS0 0x1e
#define ATTR_PCIE_IO 0x51
#define ATTR_PCIE_MEM 0x59
/*
* Helpers to get DDR bank info
*/
#define DDR_SIZE_CS(n) DDR_REG(0x1500 + ((n) << 3))
#define DDR_BASE_CS(n) DDR_REG(0x1504 + ((n) << 3))
/*
* CPU Address Decode Windows registers
*/
#define CPU_WIN_CTRL(n) BRIDGE_REG(0x000 | ((n) << 4))
#define CPU_WIN_BASE(n) BRIDGE_REG(0x004 | ((n) << 4))
#define CPU_WIN_REMAP_LO(n) BRIDGE_REG(0x008 | ((n) << 4))
#define CPU_WIN_REMAP_HI(n) BRIDGE_REG(0x00c | ((n) << 4))
struct mbus_dram_target_info loki_mbus_dram_info;
static void __init setup_cpu_win(int win, u32 base, u32 size,
u8 target, u8 attr, int remap)
{
u32 ctrl;
base &= 0xffff0000;
ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (1 << 5) | target;
writel(base, CPU_WIN_BASE(win));
writel(ctrl, CPU_WIN_CTRL(win));
if (win < 2) {
if (remap < 0)
remap = base;
writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
writel(0, CPU_WIN_REMAP_HI(win));
}
}
void __init loki_setup_cpu_mbus(void)
{
int i;
int cs;
/*
* First, disable and clear windows.
*/
for (i = 0; i < 8; i++) {
writel(0, CPU_WIN_BASE(i));
writel(0, CPU_WIN_CTRL(i));
if (i < 2) {
writel(0, CPU_WIN_REMAP_LO(i));
writel(0, CPU_WIN_REMAP_HI(i));
}
}
/*
* Setup windows for PCIe IO+MEM space.
*/
setup_cpu_win(2, LOKI_PCIE0_MEM_PHYS_BASE, LOKI_PCIE0_MEM_SIZE,
TARGET_PCIE0, ATTR_PCIE_MEM, -1);
setup_cpu_win(3, LOKI_PCIE1_MEM_PHYS_BASE, LOKI_PCIE1_MEM_SIZE,
TARGET_PCIE1, ATTR_PCIE_MEM, -1);
/*
* Setup MBUS dram target info.
*/
loki_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
for (i = 0, cs = 0; i < 4; i++) {
u32 base = readl(DDR_BASE_CS(i));
u32 size = readl(DDR_SIZE_CS(i));
/*
* Chip select enabled?
*/
if (size & 1) {
struct mbus_dram_window *w;
w = &loki_mbus_dram_info.cs[cs++];
w->cs_index = i;
w->mbus_attr = 0xf & ~(1 << i);
w->base = base & 0xffff0000;
w->size = (size | 0x0000ffff) + 1;
}
}
loki_mbus_dram_info.num_cs = cs;
}
void __init loki_setup_dev_boot_win(u32 base, u32 size)
{
setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
}

305
arch/arm/mach-loki/common.c Normal file
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@ -0,0 +1,305 @@
/*
* arch/arm/mach-loki/common.c
*
* Core functions for Marvell Loki (88RC8480) SoCs
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/mbus.h>
#include <linux/mv643xx_eth.h>
#include <asm/page.h>
#include <asm/timex.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/arch/loki.h>
#include <asm/plat-orion/orion_nand.h>
#include <asm/plat-orion/time.h>
#include "common.h"
/*****************************************************************************
* I/O Address Mapping
****************************************************************************/
static struct map_desc loki_io_desc[] __initdata = {
{
.virtual = LOKI_REGS_VIRT_BASE,
.pfn = __phys_to_pfn(LOKI_REGS_PHYS_BASE),
.length = LOKI_REGS_SIZE,
.type = MT_DEVICE,
},
};
void __init loki_map_io(void)
{
iotable_init(loki_io_desc, ARRAY_SIZE(loki_io_desc));
}
/*****************************************************************************
* GE0
****************************************************************************/
struct mv643xx_eth_shared_platform_data loki_ge0_shared_data = {
.t_clk = LOKI_TCLK,
.dram = &loki_mbus_dram_info,
};
static struct resource loki_ge0_shared_resources[] = {
{
.name = "ge0 base",
.start = GE0_PHYS_BASE + 0x2000,
.end = GE0_PHYS_BASE + 0x3fff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device loki_ge0_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 0,
.dev = {
.platform_data = &loki_ge0_shared_data,
},
.num_resources = 1,
.resource = loki_ge0_shared_resources,
};
static struct resource loki_ge0_resources[] = {
{
.name = "ge0 irq",
.start = IRQ_LOKI_GBE_A_INT,
.end = IRQ_LOKI_GBE_A_INT,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device loki_ge0 = {
.name = MV643XX_ETH_NAME,
.id = 0,
.num_resources = 1,
.resource = loki_ge0_resources,
};
void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data)
{
eth_data->shared = &loki_ge0_shared;
loki_ge0.dev.platform_data = eth_data;
writel(0x00079220, GE0_VIRT_BASE + 0x20b0);
platform_device_register(&loki_ge0_shared);
platform_device_register(&loki_ge0);
}
/*****************************************************************************
* GE1
****************************************************************************/
struct mv643xx_eth_shared_platform_data loki_ge1_shared_data = {
.t_clk = LOKI_TCLK,
.dram = &loki_mbus_dram_info,
};
static struct resource loki_ge1_shared_resources[] = {
{
.name = "ge1 base",
.start = GE1_PHYS_BASE + 0x2000,
.end = GE1_PHYS_BASE + 0x3fff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device loki_ge1_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 1,
.dev = {
.platform_data = &loki_ge1_shared_data,
},
.num_resources = 1,
.resource = loki_ge1_shared_resources,
};
static struct resource loki_ge1_resources[] = {
{
.name = "ge1 irq",
.start = IRQ_LOKI_GBE_B_INT,
.end = IRQ_LOKI_GBE_B_INT,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device loki_ge1 = {
.name = MV643XX_ETH_NAME,
.id = 1,
.num_resources = 1,
.resource = loki_ge1_resources,
};
void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data)
{
eth_data->shared = &loki_ge1_shared;
loki_ge1.dev.platform_data = eth_data;
writel(0x00079220, GE1_VIRT_BASE + 0x20b0);
platform_device_register(&loki_ge1_shared);
platform_device_register(&loki_ge1);
}
/*****************************************************************************
* SAS/SATA
****************************************************************************/
static struct resource loki_sas_resources[] = {
{
.name = "mvsas0 mem",
.start = SAS0_PHYS_BASE,
.end = SAS0_PHYS_BASE + 0x01ff,
.flags = IORESOURCE_MEM,
}, {
.name = "mvsas0 irq",
.start = IRQ_LOKI_SAS_A,
.end = IRQ_LOKI_SAS_A,
.flags = IORESOURCE_IRQ,
}, {
.name = "mvsas1 mem",
.start = SAS1_PHYS_BASE,
.end = SAS1_PHYS_BASE + 0x01ff,
.flags = IORESOURCE_MEM,
}, {
.name = "mvsas1 irq",
.start = IRQ_LOKI_SAS_B,
.end = IRQ_LOKI_SAS_B,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device loki_sas = {
.name = "mvsas",
.id = 0,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(loki_sas_resources),
.resource = loki_sas_resources,
};
void __init loki_sas_init(void)
{
writel(0x8300f707, DDR_REG(0x1424));
platform_device_register(&loki_sas);
}
/*****************************************************************************
* UART0
****************************************************************************/
static struct plat_serial8250_port loki_uart0_data[] = {
{
.mapbase = UART0_PHYS_BASE,
.membase = (char *)UART0_VIRT_BASE,
.irq = IRQ_LOKI_UART0,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = LOKI_TCLK,
}, {
},
};
static struct resource loki_uart0_resources[] = {
{
.start = UART0_PHYS_BASE,
.end = UART0_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_LOKI_UART0,
.end = IRQ_LOKI_UART0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device loki_uart0 = {
.name = "serial8250",
.id = 0,
.dev = {
.platform_data = loki_uart0_data,
},
.resource = loki_uart0_resources,
.num_resources = ARRAY_SIZE(loki_uart0_resources),
};
void __init loki_uart0_init(void)
{
platform_device_register(&loki_uart0);
}
/*****************************************************************************
* UART1
****************************************************************************/
static struct plat_serial8250_port loki_uart1_data[] = {
{
.mapbase = UART1_PHYS_BASE,
.membase = (char *)UART1_VIRT_BASE,
.irq = IRQ_LOKI_UART1,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = LOKI_TCLK,
}, {
},
};
static struct resource loki_uart1_resources[] = {
{
.start = UART1_PHYS_BASE,
.end = UART1_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_LOKI_UART1,
.end = IRQ_LOKI_UART1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device loki_uart1 = {
.name = "serial8250",
.id = 1,
.dev = {
.platform_data = loki_uart1_data,
},
.resource = loki_uart1_resources,
.num_resources = ARRAY_SIZE(loki_uart1_resources),
};
void __init loki_uart1_init(void)
{
platform_device_register(&loki_uart1);
}
/*****************************************************************************
* Time handling
****************************************************************************/
static void loki_timer_init(void)
{
orion_time_init(IRQ_LOKI_BRIDGE, LOKI_TCLK);
}
struct sys_timer loki_timer = {
.init = loki_timer_init,
};
/*****************************************************************************
* General
****************************************************************************/
void __init loki_init(void)
{
printk(KERN_INFO "Loki ID: 88RC8480. TCLK=%d.\n", LOKI_TCLK);
loki_setup_cpu_mbus();
}

36
arch/arm/mach-loki/common.h Normal file
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@ -0,0 +1,36 @@
/*
* arch/arm/mach-loki/common.h
*
* Core functions for Marvell Loki (88RC8480) SoCs
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ARCH_LOKI_COMMON_H
#define __ARCH_LOKI_COMMON_H
struct mv643xx_eth_platform_data;
/*
* Basic Loki init functions used early by machine-setup.
*/
void loki_map_io(void);
void loki_init(void);
void loki_init_irq(void);
extern struct mbus_dram_target_info loki_mbus_dram_info;
void loki_setup_cpu_mbus(void);
void loki_setup_dev_boot_win(u32 base, u32 size);
void loki_ge0_init(struct mv643xx_eth_platform_data *eth_data);
void loki_ge1_init(struct mv643xx_eth_platform_data *eth_data);
void loki_sas_init(void);
void loki_uart0_init(void);
void loki_uart1_init(void);
extern struct sys_timer loki_timer;
#endif

21
arch/arm/mach-loki/irq.c Normal file
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@ -0,0 +1,21 @@
/*
* arch/arm/mach-loki/irq.c
*
* Marvell Loki (88RC8480) IRQ handling.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/io.h>
#include <asm/plat-orion/irq.h>
#include "common.h"
void __init loki_init_irq(void)
{
orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_OFF));
}

100
arch/arm/mach-loki/lb88rc8480-setup.c Normal file
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@ -0,0 +1,100 @@
/*
* arch/arm/mach-loki/lb88rc8480-setup.c
*
* Marvell LB88RC8480 Development Board Setup
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/nand.h>
#include <linux/timer.h>
#include <linux/ata_platform.h>
#include <linux/mv643xx_eth.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/arch/loki.h>
#include "common.h"
#define LB88RC8480_FLASH_BOOT_CS_BASE 0xf8000000
#define LB88RC8480_FLASH_BOOT_CS_SIZE SZ_128M
#define LB88RC8480_NOR_BOOT_BASE 0xff000000
#define LB88RC8480_NOR_BOOT_SIZE SZ_16M
static struct mtd_partition lb88rc8480_boot_flash_parts[] = {
{
.name = "kernel",
.offset = 0,
.size = SZ_2M,
}, {
.name = "root-fs",
.offset = SZ_2M,
.size = (SZ_8M + SZ_4M + SZ_1M),
}, {
.name = "u-boot",
.offset = (SZ_8M + SZ_4M + SZ_2M + SZ_1M),
.size = SZ_1M,
},
};
static struct physmap_flash_data lb88rc8480_boot_flash_data = {
.parts = lb88rc8480_boot_flash_parts,
.nr_parts = ARRAY_SIZE(lb88rc8480_boot_flash_parts),
.width = 1, /* 8 bit bus width */
};
static struct resource lb88rc8480_boot_flash_resource = {
.flags = IORESOURCE_MEM,
.start = LB88RC8480_NOR_BOOT_BASE,
.end = LB88RC8480_NOR_BOOT_BASE + LB88RC8480_NOR_BOOT_SIZE - 1,
};
static struct platform_device lb88rc8480_boot_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &lb88rc8480_boot_flash_data,
},
.num_resources = 1,
.resource = &lb88rc8480_boot_flash_resource,
};
static struct mv643xx_eth_platform_data lb88rc8480_ge0_data = {
.phy_addr = 1,
.mac_addr = { 0x00, 0x50, 0x43, 0x11, 0x22, 0x33 },
};
static void __init lb88rc8480_init(void)
{
/*
* Basic setup. Needs to be called early.
*/
loki_init();
loki_ge0_init(&lb88rc8480_ge0_data);
loki_sas_init();
loki_uart0_init();
loki_uart1_init();
loki_setup_dev_boot_win(LB88RC8480_FLASH_BOOT_CS_BASE,
LB88RC8480_FLASH_BOOT_CS_SIZE);
platform_device_register(&lb88rc8480_boot_flash);
}
MACHINE_START(LB88RC8480, "Marvell LB88RC8480 Development Board")
/* Maintainer: Ke Wei <kewei@marvell.com> */
.phys_io = LOKI_REGS_PHYS_BASE,
.io_pg_offst = ((LOKI_REGS_VIRT_BASE) >> 18) & 0xfffc,
.boot_params = 0x00000100,
.init_machine = lb88rc8480_init,
.map_io = loki_map_io,
.init_irq = loki_init_irq,
.timer = &loki_timer,
MACHINE_END

2
arch/arm/mm/Kconfig
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@ -365,7 +365,7 @@ config CPU_XSC3
# Feroceon
config CPU_FEROCEON
bool
depends on ARCH_ORION5X
depends on ARCH_ORION5X || ARCH_LOKI
default y
select CPU_32v5
select CPU_ABRT_EV5T

20
include/asm-arm/arch-loki/debug-macro.S Normal file
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@ -0,0 +1,20 @@
/*
* include/asm-arm/arch-loki/debug-macro.S
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <asm/arch/loki.h>
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
ldreq \rx, =LOKI_REGS_PHYS_BASE
ldrne \rx, =LOKI_REGS_VIRT_BASE
orr \rx, \rx, #0x00012000
.endm
#define UART_SHIFT 2
#include <asm/hardware/debug-8250.S>

1
include/asm-arm/arch-loki/dma.h Normal file
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@ -0,0 +1 @@
/* empty */

30
include/asm-arm/arch-loki/entry-macro.S Normal file
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@ -0,0 +1,30 @@
/*
* include/asm-arm/arch-loki/entry-macro.S
*
* Low-level IRQ helper macros for Marvell Loki (88RC8480) platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/arch/loki.h>
.macro disable_fiq
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_preamble, base, tmp
ldr \base, =IRQ_VIRT_BASE
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqstat, [\base, #IRQ_CAUSE_OFF]
ldr \tmp, [\base, #IRQ_MASK_OFF]
mov \irqnr, #0
ands \irqstat, \irqstat, \tmp
clzne \irqnr, \irqstat
rsbne \irqnr, \irqnr, #31
.endm

15
include/asm-arm/arch-loki/hardware.h Normal file
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@ -0,0 +1,15 @@
/*
* include/asm-arm/arch-loki/hardware.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include "loki.h"
#endif

26
include/asm-arm/arch-loki/io.h Normal file
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@ -0,0 +1,26 @@
/*
* include/asm-arm/arch-loki/io.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#include "loki.h"
#define IO_SPACE_LIMIT 0xffffffff
static inline void __iomem *__io(unsigned long addr)
{
return (void __iomem *)((addr - LOKI_PCIE0_IO_PHYS_BASE)
+ LOKI_PCIE0_IO_VIRT_BASE);
}
#define __io(a) __io(a)
#define __mem_pci(a) (a)
#endif

58
include/asm-arm/arch-loki/irqs.h Normal file
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/*
* include/asm-arm/arch-loki/irqs.h
*
* IRQ definitions for Marvell Loki (88RC8480) SoCs
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
#include "loki.h" /* need GPIO_MAX */
/*
* Interrupt Controller
*/
#define IRQ_LOKI_PCIE_A_CPU_DRBL 0
#define IRQ_LOKI_CPU_PCIE_A_DRBL 1
#define IRQ_LOKI_PCIE_B_CPU_DRBL 2
#define IRQ_LOKI_CPU_PCIE_B_DRBL 3
#define IRQ_LOKI_COM_A_ERR 6
#define IRQ_LOKI_COM_A_IN 7
#define IRQ_LOKI_COM_A_OUT 8
#define IRQ_LOKI_COM_B_ERR 9
#define IRQ_LOKI_COM_B_IN 10
#define IRQ_LOKI_COM_B_OUT 11
#define IRQ_LOKI_DMA_A 12
#define IRQ_LOKI_DMA_B 13
#define IRQ_LOKI_SAS_A 14
#define IRQ_LOKI_SAS_B 15
#define IRQ_LOKI_DDR 16
#define IRQ_LOKI_XOR 17
#define IRQ_LOKI_BRIDGE 18
#define IRQ_LOKI_PCIE_A_ERR 20
#define IRQ_LOKI_PCIE_A_INT 21
#define IRQ_LOKI_PCIE_B_ERR 22
#define IRQ_LOKI_PCIE_B_INT 23
#define IRQ_LOKI_GBE_A_INT 24
#define IRQ_LOKI_GBE_B_INT 25
#define IRQ_LOKI_DEV_ERR 26
#define IRQ_LOKI_UART0 27
#define IRQ_LOKI_UART1 28
#define IRQ_LOKI_TWSI 29
#define IRQ_LOKI_GPIO_23_0 30
#define IRQ_LOKI_GPIO_25_24 31
/*
* Loki General Purpose Pins
*/
#define IRQ_LOKI_GPIO_START 32
#define NR_GPIO_IRQS GPIO_MAX
#define NR_IRQS (IRQ_LOKI_GPIO_START + NR_GPIO_IRQS)
#endif

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/*
* include/asm-arm/arch-loki/loki.h
*
* Generic definitions for Marvell Loki (88RC8480) SoC flavors
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_LOKI_H
#define __ASM_ARCH_LOKI_H
/*
* Marvell Loki (88RC8480) address maps.
*
* phys
* d0000000 on-chip peripheral registers
* e0000000 PCIe 0 Memory space
* e8000000 PCIe 1 Memory space
* f0000000 PCIe 0 I/O space
* f0100000 PCIe 1 I/O space
*
* virt phys size
* fed00000 d0000000 1M on-chip peripheral registers
* fee00000 f0000000 64K PCIe 0 I/O space
* fef00000 f0100000 64K PCIe 1 I/O space
*/
#define LOKI_REGS_PHYS_BASE 0xd0000000
#define LOKI_REGS_VIRT_BASE 0xfed00000
#define LOKI_REGS_SIZE SZ_1M
#define LOKI_PCIE0_IO_PHYS_BASE 0xf0000000
#define LOKI_PCIE0_IO_VIRT_BASE 0xfee00000
#define LOKI_PCIE0_IO_BUS_BASE 0x00000000
#define LOKI_PCIE0_IO_SIZE SZ_64K
#define LOKI_PCIE1_IO_PHYS_BASE 0xf0100000
#define LOKI_PCIE1_IO_VIRT_BASE 0xfef00000
#define LOKI_PCIE1_IO_BUS_BASE 0x00000000
#define LOKI_PCIE1_IO_SIZE SZ_64K
#define LOKI_PCIE0_MEM_PHYS_BASE 0xe0000000
#define LOKI_PCIE0_MEM_SIZE SZ_128M
#define LOKI_PCIE1_MEM_PHYS_BASE 0xe8000000
#define LOKI_PCIE1_MEM_SIZE SZ_128M
/*
* Register Map
*/
#define DEV_BUS_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x10000)
#define DEV_BUS_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x10000)
#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
#define BRIDGE_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x20000)
#define BRIDGE_REG(x) (BRIDGE_VIRT_BASE | (x))
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
#define SOFT_RESET_OUT_EN 0x00000004
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
#define SOFT_RESET 0x00000001
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
#define BRIDGE_INT_TIMER0 0x0002
#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR 0x0004
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
#define IRQ_CAUSE_OFF 0x0000
#define IRQ_MASK_OFF 0x0004
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
#define PCIE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x30000)
#define PCIE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x40000)
#define SAS0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x80000)
#define SAS1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x90000)
#define GE0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xa0000)
#define GE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xa0000)
#define GE1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xb0000)
#define GE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xb0000)
#define DDR_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xf0000)
#define DDR_REG(x) (DDR_VIRT_BASE | (x))
#define GPIO_MAX 8
#endif

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/*
* include/asm-arm/arch-loki/memory.h
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#define PHYS_OFFSET UL(0x00000000)
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
#endif

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include/asm-arm/arch-loki/system.h Normal file
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/*
* include/asm-arm/arch-loki/system.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <asm/arch/hardware.h>
#include <asm/arch/loki.h>
static inline void arch_idle(void)
{
cpu_do_idle();
}
static inline void arch_reset(char mode)
{
/*
* Enable soft reset to assert RSTOUTn.
*/
writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
/*
* Assert soft reset.
*/
writel(SOFT_RESET, SYSTEM_SOFT_RESET);
while (1)
;
}
#endif

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include/asm-arm/arch-loki/timex.h Normal file
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/*
* include/asm-arm/arch-loki/timex.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#define CLOCK_TICK_RATE (100 * HZ)
#define LOKI_TCLK 180000000

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include/asm-arm/arch-loki/uncompress.h Normal file
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/*
* include/asm-arm/arch-loki/uncompress.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/serial_reg.h>
#include <asm/arch/loki.h>
#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE)
static void putc(const char c)
{
unsigned char *base = SERIAL_BASE;
int i;
for (i = 0; i < 0x1000; i++) {
if (base[UART_LSR << 2] & UART_LSR_THRE)
break;
barrier();
}
base[UART_TX << 2] = c;
}
static void flush(void)
{
unsigned char *base = SERIAL_BASE;
unsigned char mask;
int i;
mask = UART_LSR_TEMT | UART_LSR_THRE;
for (i = 0; i < 0x1000; i++) {
if ((base[UART_LSR << 2] & mask) == mask)
break;
barrier();
}
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()

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include/asm-arm/arch-loki/vmalloc.h Normal file
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/*
* include/asm-arm/arch-loki/vmalloc.h
*/
#define VMALLOC_END 0xfe800000