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ARM: dts: imx: specify the value of audmux pinctrl instead of 0x80000000

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We must specify the value of audmux pinctrl if we want to use pinctrl_pm().
Thus change bypass value 0x80000000 to what we exactly need.

This patch also seperately unset PUE bit for TXD so that IOMUX won't pull
up/down the pin after turning into tristate. When we use SSI normal mode to
playback monaural audio via I2S signal, there'd be a pulled curve occur to
its signal at the second slot if setting PUE bit for TXD. And it will make
the second channel to play a constant noise. So by keeping the signal level
in the second slot, we can get a constant high level signal (-1) or a low
level one (0).

Signed-off-by: Nicolin Chen <b42378@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Nicolin Chen 2014-02-08 10:14:28 +08:00 committed by Shawn Guo
parent 60e90acbca
commit 77112dd58a
3 changed files with 12 additions and 12 deletions
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8
arch/arm/boot/dts/imx6q-sabrelite.dts
View File

@ -133,10 +133,10 @@
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000
MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000
MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000
MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
>;
};

8
arch/arm/boot/dts/imx6qdl-sabresd.dtsi
View File

@ -192,10 +192,10 @@
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
>;
};

8
arch/arm/boot/dts/imx6qdl-wandboard.dtsi
View File

@ -98,10 +98,10 @@
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
>;
};