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[MIPS] Build blast_cache routines from template
Build blast_xxx, blast_xxx_page, blast_xxx_page_indexed from template. Easier to maintaina and saves 300 lines. Generated code should be unchanged. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
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3055acb07a
commit
76f072a46f
@ -166,123 +166,6 @@ static inline void invalidate_tcache_page(unsigned long addr)
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: "r" (base), \
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"i" (op));
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static inline void blast_dcache16(void)
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{
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unsigned long start = INDEX_BASE;
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unsigned long end = start + current_cpu_data.dcache.waysize;
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unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
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unsigned long ws_end = current_cpu_data.dcache.ways <<
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current_cpu_data.dcache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x200)
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cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
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}
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static inline void blast_dcache16_page(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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do {
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cache16_unroll32(start,Hit_Writeback_Inv_D);
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start += 0x200;
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} while (start < end);
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}
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static inline void blast_dcache16_page_indexed(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
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unsigned long ws_end = current_cpu_data.dcache.ways <<
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current_cpu_data.dcache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x200)
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cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
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}
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static inline void blast_icache16(void)
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{
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unsigned long start = INDEX_BASE;
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unsigned long end = start + current_cpu_data.icache.waysize;
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unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
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unsigned long ws_end = current_cpu_data.icache.ways <<
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current_cpu_data.icache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x200)
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cache16_unroll32(addr|ws,Index_Invalidate_I);
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}
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static inline void blast_icache16_page(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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do {
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cache16_unroll32(start,Hit_Invalidate_I);
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start += 0x200;
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} while (start < end);
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}
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static inline void blast_icache16_page_indexed(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
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unsigned long ws_end = current_cpu_data.icache.ways <<
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current_cpu_data.icache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x200)
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cache16_unroll32(addr|ws,Index_Invalidate_I);
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}
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static inline void blast_scache16(void)
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{
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unsigned long start = INDEX_BASE;
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unsigned long end = start + current_cpu_data.scache.waysize;
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unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
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unsigned long ws_end = current_cpu_data.scache.ways <<
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current_cpu_data.scache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x200)
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cache16_unroll32(addr|ws,Index_Writeback_Inv_SD);
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}
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static inline void blast_scache16_page(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = page + PAGE_SIZE;
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do {
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cache16_unroll32(start,Hit_Writeback_Inv_SD);
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start += 0x200;
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} while (start < end);
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}
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static inline void blast_scache16_page_indexed(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
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unsigned long ws_end = current_cpu_data.scache.ways <<
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current_cpu_data.scache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x200)
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cache16_unroll32(addr|ws,Index_Writeback_Inv_SD);
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}
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#define cache32_unroll32(base,op) \
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__asm__ __volatile__( \
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" .set push \n" \
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@ -309,123 +192,6 @@ static inline void blast_scache16_page_indexed(unsigned long page)
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: "r" (base), \
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"i" (op));
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static inline void blast_dcache32(void)
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{
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unsigned long start = INDEX_BASE;
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unsigned long end = start + current_cpu_data.dcache.waysize;
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unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
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unsigned long ws_end = current_cpu_data.dcache.ways <<
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current_cpu_data.dcache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x400)
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cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
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}
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static inline void blast_dcache32_page(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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do {
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cache32_unroll32(start,Hit_Writeback_Inv_D);
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start += 0x400;
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} while (start < end);
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}
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static inline void blast_dcache32_page_indexed(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
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unsigned long ws_end = current_cpu_data.dcache.ways <<
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current_cpu_data.dcache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x400)
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cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
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}
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static inline void blast_icache32(void)
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{
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unsigned long start = INDEX_BASE;
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unsigned long end = start + current_cpu_data.icache.waysize;
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unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
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unsigned long ws_end = current_cpu_data.icache.ways <<
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current_cpu_data.icache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x400)
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cache32_unroll32(addr|ws,Index_Invalidate_I);
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}
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static inline void blast_icache32_page(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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do {
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cache32_unroll32(start,Hit_Invalidate_I);
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start += 0x400;
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} while (start < end);
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}
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static inline void blast_icache32_page_indexed(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
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unsigned long ws_end = current_cpu_data.icache.ways <<
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current_cpu_data.icache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x400)
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cache32_unroll32(addr|ws,Index_Invalidate_I);
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}
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static inline void blast_scache32(void)
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{
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unsigned long start = INDEX_BASE;
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unsigned long end = start + current_cpu_data.scache.waysize;
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unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
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unsigned long ws_end = current_cpu_data.scache.ways <<
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current_cpu_data.scache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x400)
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cache32_unroll32(addr|ws,Index_Writeback_Inv_SD);
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}
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static inline void blast_scache32_page(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = page + PAGE_SIZE;
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do {
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cache32_unroll32(start,Hit_Writeback_Inv_SD);
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start += 0x400;
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} while (start < end);
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}
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static inline void blast_scache32_page_indexed(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
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unsigned long ws_end = current_cpu_data.scache.ways <<
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current_cpu_data.scache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x400)
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cache32_unroll32(addr|ws,Index_Writeback_Inv_SD);
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}
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#define cache64_unroll32(base,op) \
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__asm__ __volatile__( \
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" .set push \n" \
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@ -452,84 +218,6 @@ static inline void blast_scache32_page_indexed(unsigned long page)
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: "r" (base), \
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"i" (op));
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static inline void blast_icache64(void)
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{
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unsigned long start = INDEX_BASE;
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unsigned long end = start + current_cpu_data.icache.waysize;
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unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
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unsigned long ws_end = current_cpu_data.icache.ways <<
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current_cpu_data.icache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x800)
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cache64_unroll32(addr|ws,Index_Invalidate_I);
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}
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static inline void blast_icache64_page(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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do {
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cache64_unroll32(start,Hit_Invalidate_I);
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start += 0x800;
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} while (start < end);
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}
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static inline void blast_icache64_page_indexed(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
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unsigned long ws_end = current_cpu_data.icache.ways <<
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current_cpu_data.icache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x800)
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cache64_unroll32(addr|ws,Index_Invalidate_I);
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}
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static inline void blast_scache64(void)
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{
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unsigned long start = INDEX_BASE;
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unsigned long end = start + current_cpu_data.scache.waysize;
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unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
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unsigned long ws_end = current_cpu_data.scache.ways <<
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current_cpu_data.scache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x800)
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cache64_unroll32(addr|ws,Index_Writeback_Inv_SD);
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}
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static inline void blast_scache64_page(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = page + PAGE_SIZE;
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do {
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cache64_unroll32(start,Hit_Writeback_Inv_SD);
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start += 0x800;
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} while (start < end);
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}
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static inline void blast_scache64_page_indexed(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
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unsigned long ws_end = current_cpu_data.scache.ways <<
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current_cpu_data.scache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x800)
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cache64_unroll32(addr|ws,Index_Writeback_Inv_SD);
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}
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#define cache128_unroll32(base,op) \
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__asm__ __volatile__( \
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" .set push \n" \
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@ -556,43 +244,55 @@ static inline void blast_scache64_page_indexed(unsigned long page)
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: "r" (base), \
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"i" (op));
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static inline void blast_scache128(void)
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{
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unsigned long start = INDEX_BASE;
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unsigned long end = start + current_cpu_data.scache.waysize;
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unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
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unsigned long ws_end = current_cpu_data.scache.ways <<
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current_cpu_data.scache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x1000)
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cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
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/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
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#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
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static inline void blast_##pfx##cache##lsize(void) \
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{ \
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unsigned long start = INDEX_BASE; \
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unsigned long end = start + current_cpu_data.desc.waysize; \
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unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \
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unsigned long ws_end = current_cpu_data.desc.ways << \
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current_cpu_data.desc.waybit; \
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unsigned long ws, addr; \
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\
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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for (addr = start; addr < end; addr += lsize * 32) \
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cache##lsize##_unroll32(addr|ws,indexop); \
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} \
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\
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static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \
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{ \
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unsigned long start = page; \
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unsigned long end = page + PAGE_SIZE; \
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\
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do { \
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cache##lsize##_unroll32(start,hitop); \
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start += lsize * 32; \
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} while (start < end); \
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} \
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\
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static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
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{ \
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unsigned long start = page; \
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unsigned long end = start + PAGE_SIZE; \
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unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \
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unsigned long ws_end = current_cpu_data.desc.ways << \
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current_cpu_data.desc.waybit; \
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unsigned long ws, addr; \
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\
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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for (addr = start; addr < end; addr += lsize * 32) \
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cache##lsize##_unroll32(addr|ws,indexop); \
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}
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static inline void blast_scache128_page(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = page + PAGE_SIZE;
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do {
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cache128_unroll32(start,Hit_Writeback_Inv_SD);
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start += 0x1000;
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} while (start < end);
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}
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static inline void blast_scache128_page_indexed(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
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unsigned long ws_end = current_cpu_data.scache.ways <<
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current_cpu_data.scache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x1000)
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cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
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}
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__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
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__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
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__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
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__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
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__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
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__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
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__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
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__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
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__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
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#endif /* _ASM_R4KCACHE_H */
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