From 754ec43c0184aae48f5a8c917d8282449ab564a9 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Thu, 26 Mar 2015 16:30:24 -0700 Subject: [PATCH] spi/rockchip: Round up clock rate divisor to err on the safe side The Rockchip SPI driver currently calculates its clock rate divisor by integer dividing the parent rate by the target rate, and then rounding the result up to the next even number (since the divisor must be even). Clock rate divisors should always be rounded up, so that the resulting frequency is lower or equal to the target. This is correctly done in the second step here but not in the first, so we still have a risk of exceeding the desired target frequency (e.g. setting spi-max-frequency to 40000000 with a parent clock of 99000000 could lead to a divisor of 99000000 / 40000000 == 2 (which is even) that then results in an effective frequency of 99000000 / 2 == 49500000 (potentially exceeding the flash chip's specifications). This patch changes the division to round up to fix this problem. Signed-off-by: Julius Werner Signed-off-by: Mark Brown --- drivers/spi/spi-rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 1a777dc261d6..5e4e52cbe053 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -519,7 +519,7 @@ static void rockchip_spi_config(struct rockchip_spi *rs) } /* div doesn't support odd number */ - div = max_t(u32, rs->max_freq / rs->speed, 1); + div = DIV_ROUND_UP(rs->max_freq, rs->speed); div = (div + 1) & 0xfffe; writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);