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[media] smiapp: Constify the regs argument to smiapp_write_8s()
The data may now be const as well. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Reviewed-by: Sebastian Reichel <sre@kernel.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
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@ -26,7 +26,7 @@ static int smiapp_write_8(struct smiapp_sensor *sensor, u16 reg, u8 val)
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}
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static int smiapp_write_8s(struct smiapp_sensor *sensor,
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struct smiapp_reg_8 *regs, int len)
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const struct smiapp_reg_8 *regs, int len)
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{
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struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
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int rval;
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@ -71,7 +71,7 @@ static int jt8ew9_limits(struct smiapp_sensor *sensor)
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static int jt8ew9_post_poweron(struct smiapp_sensor *sensor)
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{
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struct smiapp_reg_8 regs[] = {
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const struct smiapp_reg_8 regs[] = {
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{ 0x30a3, 0xd8 }, /* Output port control : LVDS ports only */
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{ 0x30ae, 0x00 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */
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{ 0x30af, 0xd0 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */
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@ -115,7 +115,7 @@ const struct smiapp_quirk smiapp_jt8ew9_quirk = {
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static int imx125es_post_poweron(struct smiapp_sensor *sensor)
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{
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/* Taken from v02. No idea what the other two are. */
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struct smiapp_reg_8 regs[] = {
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const struct smiapp_reg_8 regs[] = {
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/*
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* 0x3302: clk during frame blanking:
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* 0x00 - HS mode, 0x01 - LP11
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@ -145,8 +145,7 @@ static int jt8ev1_post_poweron(struct smiapp_sensor *sensor)
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{
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struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
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int rval;
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struct smiapp_reg_8 regs[] = {
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const struct smiapp_reg_8 regs[] = {
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{ 0x3031, 0xcd }, /* For digital binning (EQ_MONI) */
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{ 0x30a3, 0xd0 }, /* FLASH STROBE enable */
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{ 0x3237, 0x00 }, /* For control of pulse timing for ADC */
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@ -167,8 +166,7 @@ static int jt8ev1_post_poweron(struct smiapp_sensor *sensor)
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{ 0x33cf, 0xec }, /* For Black sun */
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{ 0x3328, 0x80 }, /* Ugh. No idea what's this. */
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};
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struct smiapp_reg_8 regs_96[] = {
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const struct smiapp_reg_8 regs_96[] = {
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{ 0x30ae, 0x00 }, /* For control of ADC clock */
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{ 0x30af, 0xd0 },
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{ 0x30b0, 0x01 },
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