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crypto: arm64/aes-ce - implement 5 way interleave for ECB, CBC and CTR
This implements 5-way interleaving for ECB, CBC decryption and CTR, resulting in a speedup of ~11% on Marvell ThunderX2, which has a very deep pipeline and therefore a high issue latency for NEON instructions operating on the same registers. Note that XTS is left alone: implementing 5-way interleave there would either involve spilling of the calculated tweaks to the stack, or recalculating them after the encryption operation, and doing either of those would most likely penalize low end cores. For ECB, this is not a concern at all, given that we have plenty of spare registers. For CTR and CBC decryption, we take advantage of the fact that v16 is not used by the CE version of the code (which is the only one targeted by the optimization), and so we can reshuffle the code a bit and avoid having to spill to memory (with the exception of one extra reload in the CBC routine) Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Ard Biesheuvel
Herbert Xu
parent
e217413964
commit
7367bfeb2c
@ -18,6 +18,8 @@
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.arch armv8-a+crypto
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xtsmask .req v16
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cbciv .req v16
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vctr .req v16
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.macro xts_reload_mask, tmp
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.endm
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@ -17,6 +17,14 @@
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#define MAX_STRIDE 4
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#endif
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#if MAX_STRIDE == 4
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#define ST4(x...) x
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#define ST5(x...)
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#else
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#define ST4(x...)
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#define ST5(x...) x
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#endif
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aes_encrypt_block4x:
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encrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
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ret
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@ -53,14 +61,17 @@ AES_ENTRY(aes_ecb_encrypt)
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enc_prepare w3, x2, x5
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.LecbencloopNx:
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subs w4, w4, #4
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subs w4, w4, #MAX_STRIDE
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bmi .Lecbenc1x
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ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
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bl aes_encrypt_block4x
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ST4( bl aes_encrypt_block4x )
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ST5( ld1 {v4.16b}, [x1], #16 )
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ST5( bl aes_encrypt_block5x )
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st1 {v0.16b-v3.16b}, [x0], #64
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ST5( st1 {v4.16b}, [x0], #16 )
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b .LecbencloopNx
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.Lecbenc1x:
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adds w4, w4, #4
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adds w4, w4, #MAX_STRIDE
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beq .Lecbencout
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.Lecbencloop:
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ld1 {v0.16b}, [x1], #16 /* get next pt block */
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@ -81,14 +92,17 @@ AES_ENTRY(aes_ecb_decrypt)
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dec_prepare w3, x2, x5
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.LecbdecloopNx:
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subs w4, w4, #4
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subs w4, w4, #MAX_STRIDE
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bmi .Lecbdec1x
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ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 ct blocks */
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bl aes_decrypt_block4x
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ST4( bl aes_decrypt_block4x )
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ST5( ld1 {v4.16b}, [x1], #16 )
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ST5( bl aes_decrypt_block5x )
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st1 {v0.16b-v3.16b}, [x0], #64
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ST5( st1 {v4.16b}, [x0], #16 )
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b .LecbdecloopNx
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.Lecbdec1x:
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adds w4, w4, #4
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adds w4, w4, #MAX_STRIDE
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beq .Lecbdecout
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.Lecbdecloop:
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ld1 {v0.16b}, [x1], #16 /* get next ct block */
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@ -148,39 +162,56 @@ AES_ENTRY(aes_cbc_decrypt)
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stp x29, x30, [sp, #-16]!
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mov x29, sp
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ld1 {v7.16b}, [x5] /* get iv */
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ld1 {cbciv.16b}, [x5] /* get iv */
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dec_prepare w3, x2, x6
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.LcbcdecloopNx:
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subs w4, w4, #4
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subs w4, w4, #MAX_STRIDE
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bmi .Lcbcdec1x
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ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 ct blocks */
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#if MAX_STRIDE == 5
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ld1 {v4.16b}, [x1], #16 /* get 1 ct block */
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mov v5.16b, v0.16b
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mov v6.16b, v1.16b
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mov v7.16b, v2.16b
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bl aes_decrypt_block5x
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sub x1, x1, #32
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eor v0.16b, v0.16b, cbciv.16b
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eor v1.16b, v1.16b, v5.16b
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ld1 {v5.16b}, [x1], #16 /* reload 1 ct block */
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ld1 {cbciv.16b}, [x1], #16 /* reload 1 ct block */
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eor v2.16b, v2.16b, v6.16b
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eor v3.16b, v3.16b, v7.16b
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eor v4.16b, v4.16b, v5.16b
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#else
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mov v4.16b, v0.16b
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mov v5.16b, v1.16b
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mov v6.16b, v2.16b
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bl aes_decrypt_block4x
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sub x1, x1, #16
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eor v0.16b, v0.16b, v7.16b
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eor v0.16b, v0.16b, cbciv.16b
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eor v1.16b, v1.16b, v4.16b
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ld1 {v7.16b}, [x1], #16 /* reload 1 ct block */
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ld1 {cbciv.16b}, [x1], #16 /* reload 1 ct block */
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eor v2.16b, v2.16b, v5.16b
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eor v3.16b, v3.16b, v6.16b
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#endif
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st1 {v0.16b-v3.16b}, [x0], #64
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ST5( st1 {v4.16b}, [x0], #16 )
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b .LcbcdecloopNx
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.Lcbcdec1x:
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adds w4, w4, #4
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adds w4, w4, #MAX_STRIDE
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beq .Lcbcdecout
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.Lcbcdecloop:
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ld1 {v1.16b}, [x1], #16 /* get next ct block */
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mov v0.16b, v1.16b /* ...and copy to v0 */
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decrypt_block v0, w3, x2, x6, w7
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eor v0.16b, v0.16b, v7.16b /* xor with iv => pt */
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mov v7.16b, v1.16b /* ct is next iv */
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eor v0.16b, v0.16b, cbciv.16b /* xor with iv => pt */
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mov cbciv.16b, v1.16b /* ct is next iv */
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st1 {v0.16b}, [x0], #16
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subs w4, w4, #1
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bne .Lcbcdecloop
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.Lcbcdecout:
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st1 {v7.16b}, [x5] /* return iv */
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st1 {cbciv.16b}, [x5] /* return iv */
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ldp x29, x30, [sp], #16
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ret
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AES_ENDPROC(aes_cbc_decrypt)
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@ -274,51 +305,60 @@ AES_ENTRY(aes_ctr_encrypt)
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mov x29, sp
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enc_prepare w3, x2, x6
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ld1 {v4.16b}, [x5]
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ld1 {vctr.16b}, [x5]
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umov x6, v4.d[1] /* keep swabbed ctr in reg */
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umov x6, vctr.d[1] /* keep swabbed ctr in reg */
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rev x6, x6
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cmn w6, w4 /* 32 bit overflow? */
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bcs .Lctrloop
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.LctrloopNx:
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subs w4, w4, #4
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subs w4, w4, #MAX_STRIDE
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bmi .Lctr1x
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add w7, w6, #1
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mov v0.16b, v4.16b
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mov v0.16b, vctr.16b
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add w8, w6, #2
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mov v1.16b, v4.16b
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mov v1.16b, vctr.16b
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add w9, w6, #3
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mov v2.16b, vctr.16b
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add w9, w6, #3
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mov v2.16b, v4.16b
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rev w7, w7
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mov v3.16b, v4.16b
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mov v3.16b, vctr.16b
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rev w8, w8
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ST5( mov v4.16b, vctr.16b )
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mov v1.s[3], w7
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rev w9, w9
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ST5( add w10, w6, #4 )
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mov v2.s[3], w8
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ST5( rev w10, w10 )
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mov v3.s[3], w9
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ST5( mov v4.s[3], w10 )
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ld1 {v5.16b-v7.16b}, [x1], #48 /* get 3 input blocks */
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bl aes_encrypt_block4x
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ST4( bl aes_encrypt_block4x )
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ST5( bl aes_encrypt_block5x )
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eor v0.16b, v5.16b, v0.16b
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ld1 {v5.16b}, [x1], #16 /* get 1 input block */
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ST4( ld1 {v5.16b}, [x1], #16 )
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eor v1.16b, v6.16b, v1.16b
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ST5( ld1 {v5.16b-v6.16b}, [x1], #32 )
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eor v2.16b, v7.16b, v2.16b
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eor v3.16b, v5.16b, v3.16b
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ST5( eor v4.16b, v6.16b, v4.16b )
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st1 {v0.16b-v3.16b}, [x0], #64
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add x6, x6, #4
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ST5( st1 {v4.16b}, [x0], #16 )
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add x6, x6, #MAX_STRIDE
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rev x7, x6
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ins v4.d[1], x7
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ins vctr.d[1], x7
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cbz w4, .Lctrout
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b .LctrloopNx
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.Lctr1x:
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adds w4, w4, #4
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adds w4, w4, #MAX_STRIDE
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beq .Lctrout
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.Lctrloop:
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mov v0.16b, v4.16b
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mov v0.16b, vctr.16b
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encrypt_block v0, w3, x2, x8, w7
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adds x6, x6, #1 /* increment BE ctr */
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rev x7, x6
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ins v4.d[1], x7
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ins vctr.d[1], x7
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bcs .Lctrcarry /* overflow? */
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.Lctrcarrydone:
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@ -330,7 +370,7 @@ AES_ENTRY(aes_ctr_encrypt)
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bne .Lctrloop
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.Lctrout:
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st1 {v4.16b}, [x5] /* return next CTR value */
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st1 {vctr.16b}, [x5] /* return next CTR value */
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ldp x29, x30, [sp], #16
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ret
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@ -339,11 +379,11 @@ AES_ENTRY(aes_ctr_encrypt)
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b .Lctrout
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.Lctrcarry:
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umov x7, v4.d[0] /* load upper word of ctr */
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umov x7, vctr.d[0] /* load upper word of ctr */
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rev x7, x7 /* ... to handle the carry */
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add x7, x7, #1
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rev x7, x7
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ins v4.d[0], x7
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ins vctr.d[0], x7
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b .Lctrcarrydone
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AES_ENDPROC(aes_ctr_encrypt)
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@ -15,6 +15,8 @@
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#define AES_ENDPROC(func) ENDPROC(neon_ ## func)
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xtsmask .req v7
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cbciv .req v7
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vctr .req v4
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.macro xts_reload_mask, tmp
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xts_load_mask \tmp
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