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net: phy: Allow BCM5481x PHYs to setup internal TX/RX clock delay
This patch allows users to enable/disable internal TX and/or RX clock delay for BCM5481x series PHYs so as to satisfy RGMII timing specifications. On a particular platform, whether TX and/or RX clock delay is required depends on how PHY connected to the MAC IP. This requirement can be specified through "phy-mode" property in the platform device tree. Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -74,27 +74,40 @@ static int bcm54612e_config_init(struct phy_device *phydev)
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return 0;
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}
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static int bcm54810_config(struct phy_device *phydev)
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static int bcm5481x_config(struct phy_device *phydev)
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{
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int rc, val;
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val = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
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val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
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rc = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
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val);
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if (rc < 0)
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return rc;
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/* handling PHY's internal RX clock delay */
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val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
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val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
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val |= MII_BCM54XX_AUXCTL_MISC_WREN;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
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/* Disable RGMII RXC-RXD skew */
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val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
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}
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
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/* Enable RGMII RXC-RXD skew */
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val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
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}
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rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
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val);
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if (rc < 0)
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return rc;
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/* handling PHY's internal TX clock delay */
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val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
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val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
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/* Disable internal TX clock delay */
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val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
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}
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
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/* Enable internal TX clock delay */
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val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN;
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}
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rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
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if (rc < 0)
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return rc;
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@ -244,7 +257,7 @@ static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
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static int bcm54xx_config_init(struct phy_device *phydev)
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{
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int reg, err;
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int reg, err, val;
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reg = phy_read(phydev, MII_BCM54XX_ECR);
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if (reg < 0)
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@ -283,8 +296,14 @@ static int bcm54xx_config_init(struct phy_device *phydev)
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if (err)
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return err;
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} else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
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err = bcm54810_config(phydev);
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if (err)
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/* For BCM54810, we need to disable BroadR-Reach function */
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val = bcm_phy_read_exp(phydev,
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BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
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val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
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err = bcm_phy_write_exp(phydev,
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BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
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val);
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if (err < 0)
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return err;
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}
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@ -392,29 +411,7 @@ static int bcm5481_config_aneg(struct phy_device *phydev)
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ret = genphy_config_aneg(phydev);
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/* Then we can set up the delay. */
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
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u16 reg;
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/*
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* There is no BCM5481 specification available, so down
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* here is everything we know about "register 0x18". This
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* at least helps BCM5481 to successfully receive packets
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* on MPC8360E-RDK board. Peter Barada <peterb@logicpd.com>
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* says: "This sets delay between the RXD and RXC signals
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* instead of using trace lengths to achieve timing".
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*/
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/* Set RDX clk delay. */
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reg = 0x7 | (0x7 << 12);
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phy_write(phydev, 0x18, reg);
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reg = phy_read(phydev, 0x18);
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/* Set RDX-RXC skew. */
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reg |= (1 << 8);
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/* Write bits 14:0. */
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reg |= (1 << 15);
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phy_write(phydev, 0x18, reg);
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}
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bcm5481x_config(phydev);
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if (of_property_read_bool(np, "enet-phy-lane-swap")) {
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/* Lane Swap - Undocumented register...magic! */
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