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arm64: dts: r8a7796: Add Cortex-A57 CPU cores

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This patch adds Cortex-A57 CPU cores to R8A7796 SoC for a total of
2 x Cortex-A57.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Rebased]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Takeshi Kihara 2017-03-07 19:03:22 +01:00 committed by Simon Horman
parent b5a8ffad0e
commit 7328be4a03
1 changed files with 14 additions and 6 deletions
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20
arch/arm64/boot/dts/renesas/r8a7796.dtsi
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@ -37,7 +37,6 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
/* 1 core only at this point */
a57_0: cpu@0 { a57_0: cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8"; compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x0>; reg = <0x0>;
@ -47,6 +46,15 @@
enable-method = "psci"; enable-method = "psci";
}; };
a57_1: cpu@1 {
compatible = "arm,cortex-a57","arm,armv8";
reg = <0x1>;
device_type = "cpu";
power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
};
L2_CA57: cache-controller-0 { L2_CA57: cache-controller-0 {
compatible = "cache"; compatible = "cache";
power-domains = <&sysc R8A7796_PD_CA57_SCU>; power-domains = <&sysc R8A7796_PD_CA57_SCU>;
@ -100,7 +108,7 @@
<0x0 0xf1040000 0 0x20000>, <0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>; <0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9 interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>; clocks = <&cpg CPG_MOD 408>;
clock-names = "clk"; clock-names = "clk";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@ -109,13 +117,13 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 <GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 <GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 <GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
}; };
wdt0: watchdog@e6020000 { wdt0: watchdog@e6020000 {