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amd64_edac: clarify DRAM CTL debug reporting
Make debug info formulations about the DRAM and DCT configuration of the machine more human readable. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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parent
6ec22f9b03
commit
72381bd55e
@ -1402,27 +1402,36 @@ static void f10_read_dram_ctl_register(struct amd64_pvt *pvt)
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err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCTL_SEL_LOW,
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&pvt->dram_ctl_select_low);
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if (err) {
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debugf0("Reading F10_DCTL_SEL_LOW failed\n");
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debugf0("Reading F2x110 (DCTL Sel. Low) failed\n");
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} else {
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debugf0("DRAM_DCTL_SEL_LOW=0x%x DctSelBaseAddr=0x%x\n",
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pvt->dram_ctl_select_low, dct_sel_baseaddr(pvt));
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debugf0("F2x110 (DCTL Sel. Low): 0x%08x, "
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"High range addresses at: 0x%x\n",
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pvt->dram_ctl_select_low,
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dct_sel_baseaddr(pvt));
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debugf0(" DRAM DCTs are=%s DRAM Is=%s DRAM-Ctl-"
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"sel-hi-range=%s\n",
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(dct_ganging_enabled(pvt) ? "GANGED" : "NOT GANGED"),
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(dct_dram_enabled(pvt) ? "Enabled" : "Disabled"),
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(dct_high_range_enabled(pvt) ? "Enabled" : "Disabled"));
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debugf0(" DCT mode: %s, All DCTs on: %s\n",
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(dct_ganging_enabled(pvt) ? "ganged" : "unganged"),
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(dct_dram_enabled(pvt) ? "yes" : "no"));
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debugf0(" DctDatIntLv=%s MemCleared=%s DctSelIntLvAddr=0x%x\n",
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(dct_data_intlv_enabled(pvt) ? "Enabled" : "Disabled"),
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(dct_memory_cleared(pvt) ? "True " : "False "),
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if (!dct_ganging_enabled(pvt))
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debugf0(" Address range split per DCT: %s\n",
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(dct_high_range_enabled(pvt) ? "yes" : "no"));
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debugf0(" DCT data interleave for ECC: %s, "
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"DRAM cleared since last warm reset: %s\n",
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(dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"),
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(dct_memory_cleared(pvt) ? "yes" : "no"));
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debugf0(" DCT channel interleave: %s, "
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"DCT interleave bits selector: 0x%x\n",
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(dct_interleave_enabled(pvt) ? "enabled" : "disabled"),
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dct_sel_interleave_addr(pvt));
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}
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err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCTL_SEL_HIGH,
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&pvt->dram_ctl_select_high);
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if (err)
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debugf0("Reading F10_DCTL_SEL_HIGH failed\n");
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debugf0("Reading F2x114 (DCT Sel. High) failed\n");
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}
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/*
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