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sh: avoid using PCIBIOS_MIN_xxx
Replaces PCIBIOS_MIN_IO and PCIBIOS_MIN_MEM with direct struct pci_channel access. This allows us to have more than one pci channel. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -37,7 +37,7 @@ int pci_fixup_pcic(struct pci_channel *chan)
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#endif
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/* Set IOBR for windows containing area specified in pci.h */
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pci_write_reg(chan, (PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE - 1)),
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pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE-1),
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SH7780_PCIIOBR);
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pci_write_reg(chan, ((SH7780_PCI_IO_SIZE-1) & (7<<18)),
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SH7780_PCIIOBMR);
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@ -50,7 +50,7 @@ int pci_fixup_pcic(struct pci_channel *chan)
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pci_write_reg(chan, 0x00FC0000 , SH7780_PCIMBMR0); /* 16M */
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/* Set IOBR for window containing area specified in pci.h */
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pci_write_reg(chan, PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1),
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pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE-1),
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SH7780_PCIIOBR);
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pci_write_reg(chan, (SH7780_PCI_IO_SIZE-1) & (7 << 18),
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SH7780_PCIIOBMR);
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@ -51,7 +51,7 @@ int pci_fixup_pcic(struct pci_channel *chan)
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pci_write_reg(chan, 0x00FC0000 , SH7780_PCIMBMR0); /* 16M */
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/* Set IOBR for window containing area specified in pci.h */
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pci_write_reg(chan, PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1),
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pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE-1),
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SH7780_PCIIOBR);
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pci_write_reg(chan, (SH7780_PCI_IO_SIZE-1) & (7 << 18),
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SH7780_PCIIOBMR);
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@ -206,6 +206,9 @@ int __init sh5pci_init(unsigned long memStart, unsigned long memSize)
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return 0;
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}
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#define xPCIBIOS_MIN_IO board_pci_channels->io_resource->start
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#define xPCIBIOS_MIN_MEM board_pci_channels->mem_resource->start
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void __devinit pcibios_fixup_bus(struct pci_bus *bus)
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{
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struct pci_dev *dev = bus->self;
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@ -223,9 +226,9 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus)
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/* For now, propagate host limits to the bus;
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* we'll adjust them later. */
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bus->resource[0]->end = 64*1024 - 1 ;
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bus->resource[1]->end = PCIBIOS_MIN_MEM+(256*1024*1024)-1;
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bus->resource[0]->start = PCIBIOS_MIN_IO;
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bus->resource[1]->start = PCIBIOS_MIN_MEM;
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bus->resource[1]->end = xPCIBIOS_MIN_MEM+(256*1024*1024)-1;
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bus->resource[0]->start = xPCIBIOS_MIN_IO;
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bus->resource[1]->start = xPCIBIOS_MIN_MEM;
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/* Turn off downstream PF memory address range by default */
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bus->resource[2]->start = 1024*1024;
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@ -144,22 +144,20 @@ int __init sh7751_pcic_init(struct pci_channel *chan,
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/* Set the local 16MB PCI memory space window to
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* the lowest PCI mapped address
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*/
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word = PCIBIOS_MIN_MEM & SH4_PCIMBR_MASK;
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word = chan->mem_resource->start & SH4_PCIMBR_MASK;
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pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word);
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pci_write_reg(chan, word , SH4_PCIMBR);
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/* Map IO space into PCI IO window
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* The IO window is 64K-PCIBIOS_MIN_IO in size
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* IO addresses will be translated to the
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* PCI IO window base address
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/* Map IO space into PCI IO window:
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* IO addresses will be translated to the PCI IO window base address
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*/
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pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n",
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PCIBIOS_MIN_IO, (64 << 10),
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SH7751_PCI_IO_BASE + PCIBIOS_MIN_IO);
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chan->io_resource->start, chan->io_resource->end,
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SH7751_PCI_IO_BASE + chan->io_resource->start);
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/* Make sure the MSB's of IO window are set to access PCI space
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* correctly */
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word = PCIBIOS_MIN_IO & SH4_PCIIOBR_MASK;
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word = chan->io_resource->start & SH4_PCIIOBR_MASK;
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pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word);
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pci_write_reg(chan, word, SH4_PCIIOBR);
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@ -130,14 +130,12 @@ int __init sh7780_pcic_init(struct pci_channel *chan,
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pci_write_reg(chan, map->window1.base, SH4_PCILAR1);
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pci_write_reg(chan, map->window1.base, SH7780_PCIMBAR1);
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/* Map IO space into PCI IO window
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* The IO window is 64K-PCIBIOS_MIN_IO in size
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* IO addresses will be translated to the
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* PCI IO window base address
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/* Map IO space into PCI IO window:
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* IO addresses will be translated to the PCI IO window base address
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*/
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pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n",
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PCIBIOS_MIN_IO, (64 << 10),
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SH7780_PCI_IO_BASE + PCIBIOS_MIN_IO);
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chan->io_resource->start, chan->io_resource->end,
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SH7780_PCI_IO_BASE + chan->io_resource->start);
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/* NOTE: I'm ignoring the PCI error IRQs for now..
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* TODO: add support for the internal error interrupts and
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