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V4L/DVB (6194): Changes to support interrupts on VIDB
Changes to support interrupts on VIDB Signed-off-by: Steven Toth <stoth@hauppauge.com> Reviewed-by: Michael Krufky <mkrufky@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
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@ -1252,20 +1252,23 @@ static irqreturn_t cx23885_irq(int irq, void *dev_id)
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struct cx23885_dev *dev = dev_id;
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struct cx23885_tsport *port = &dev->ts2;
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u32 pci_status, pci_mask;
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u32 ts1_status, ts1_mask;
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u32 ts2_status, ts2_mask;
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int count = 0, handled = 0;
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pci_status = cx_read(PCI_INT_STAT);
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pci_mask = cx_read(PCI_INT_MSK);
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ts1_status = cx_read(VID_B_INT_STAT);
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ts1_mask = cx_read(VID_B_INT_MSK);
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ts2_status = cx_read(VID_C_INT_STAT);
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ts2_mask = cx_read(VID_C_INT_MSK);
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if ( (pci_status == 0) && (ts2_status == 0) )
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if ( (pci_status == 0) && (ts2_status == 0) && (ts1_status == 0) )
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goto out;
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count = cx_read(port->reg_gpcnt);
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dprintk(7, "pci_status: 0x%08x pci_mask: 0x%08x\n", pci_status, pci_mask );
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dprintk(7, "ts1_status: 0x%08x ts1_mask: 0x%08x count: 0x%x\n", ts1_status, ts1_mask, count );
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dprintk(7, "ts2_status: 0x%08x ts2_mask: 0x%08x count: 0x%x\n", ts2_status, ts2_mask, count );
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if ( (pci_status & PCI_MSK_RISC_RD) ||
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@ -1303,6 +1306,48 @@ static irqreturn_t cx23885_irq(int irq, void *dev_id)
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}
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if ( (ts1_status & VID_B_MSK_OPC_ERR) ||
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(ts1_status & VID_B_MSK_BAD_PKT) ||
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(ts1_status & VID_B_MSK_SYNC) ||
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(ts1_status & VID_B_MSK_OF))
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{
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if (ts1_status & VID_B_MSK_OPC_ERR)
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dprintk(7, " (VID_B_MSK_OPC_ERR 0x%08x)\n", VID_B_MSK_OPC_ERR);
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if (ts1_status & VID_B_MSK_BAD_PKT)
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dprintk(7, " (VID_B_MSK_BAD_PKT 0x%08x)\n", VID_B_MSK_BAD_PKT);
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if (ts1_status & VID_B_MSK_SYNC)
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dprintk(7, " (VID_B_MSK_SYNC 0x%08x)\n", VID_B_MSK_SYNC);
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if (ts1_status & VID_B_MSK_OF)
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dprintk(7, " (VID_B_MSK_OF 0x%08x)\n", VID_B_MSK_OF);
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printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
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cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
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cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
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} else if (ts1_status & VID_B_MSK_RISCI1) {
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dprintk(7, " (RISCI1 0x%08x)\n", VID_B_MSK_RISCI1);
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spin_lock(&port->slock);
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count = cx_read(port->reg_gpcnt);
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cx23885_wakeup(port, &port->mpegq, count);
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spin_unlock(&port->slock);
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} else if (ts1_status & VID_B_MSK_RISCI2) {
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dprintk(7, " (RISCI2 0x%08x)\n", VID_B_MSK_RISCI2);
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spin_lock(&port->slock);
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cx23885_restart_queue(port, &port->mpegq);
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spin_unlock(&port->slock);
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}
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if (ts1_status) {
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cx_write(VID_B_INT_STAT, ts1_status);
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handled = 1;
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}
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if ( (ts2_status & VID_C_MSK_OPC_ERR) ||
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(ts2_status & VID_C_MSK_BAD_PKT) ||
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(ts2_status & VID_C_MSK_SYNC) ||
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@ -1341,9 +1386,13 @@ static irqreturn_t cx23885_irq(int irq, void *dev_id)
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}
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cx_write(VID_C_INT_STAT, ts2_status);
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cx_write(PCI_INT_STAT, pci_status);
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handled = 1;
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if (ts2_status) {
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cx_write(VID_C_INT_STAT, ts2_status);
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handled = 1;
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}
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if (handled)
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cx_write(PCI_INT_STAT, pci_status);
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out:
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return IRQ_RETVAL(handled);
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}
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