mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-23 04:34:11 +08:00
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "Regression fixers for the big 3: - nouveau: hdmi audio, dac load detect, s/r regressions fixed - radeon: long standing system hang fixed, hdmi audio and rs780 fast fb fixes - intel: one old regression, a WARN removal, and a stop X dying fix Otherwise one mgag200 fix, a couple of arm build fixes, and a core use after free fix." * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/nv50/kms: use dac loadval from vbios, where it's available drm/nv50/disp: force dac power state during load detect drm/nv50-nv84/fifo: fix resume regression introduced by playlist race fix drm/nv84/disp: Fix HDMI audio regression drm/i915/sdvo: Use &intel_sdvo->ddc instead of intel_sdvo->i2c for DDC. drm/radeon: don't allow audio on DCE6 drm/radeon: Use direct mapping for fast fb access on RS780/RS880 (v2) radeon: Fix system hang issue when using KMS with older cards drm/i915: no lvds quirk for hp t5740 drm/i915: Quirk the pipe A quirk in the modeset state checker drm/i915: Fix spurious -EIO/SIGBUS on wedged gpus drm/mgag200: Add missing write to index before accessing data register drm/nouveau: use mdelay instead of large udelay constants drm/tilcd: select BACKLIGHT_LCD_SUPPORT drm: fix a use-after-free when GPU acceleration disabled
This commit is contained in:
commit
6ea31c56a5
drivers/gpu/drm
@ -1054,7 +1054,7 @@ EXPORT_SYMBOL(drm_vblank_off);
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*/
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void drm_vblank_pre_modeset(struct drm_device *dev, int crtc)
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{
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/* vblank is not initialized (IRQ not installed ?) */
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/* vblank is not initialized (IRQ not installed ?), or has been freed */
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if (!dev->num_crtcs)
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return;
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/*
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@ -1076,6 +1076,10 @@ void drm_vblank_post_modeset(struct drm_device *dev, int crtc)
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{
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unsigned long irqflags;
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/* vblank is not initialized (IRQ not installed ?), or has been freed */
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if (!dev->num_crtcs)
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return;
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if (dev->vblank_inmodeset[crtc]) {
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spin_lock_irqsave(&dev->vbl_lock, irqflags);
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dev->vblank_disable_allowed = 1;
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|
@ -91,14 +91,11 @@ i915_gem_wait_for_error(struct i915_gpu_error *error)
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{
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int ret;
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#define EXIT_COND (!i915_reset_in_progress(error))
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#define EXIT_COND (!i915_reset_in_progress(error) || \
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i915_terminally_wedged(error))
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if (EXIT_COND)
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return 0;
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/* GPU is already declared terminally dead, give up. */
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if (i915_terminally_wedged(error))
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return -EIO;
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/*
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* Only wait 10 seconds for the gpu reset to complete to avoid hanging
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* userspace. If it takes that long something really bad is going on and
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@ -7937,6 +7937,11 @@ intel_modeset_check_state(struct drm_device *dev)
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memset(&pipe_config, 0, sizeof(pipe_config));
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active = dev_priv->display.get_pipe_config(crtc,
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&pipe_config);
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/* hw state is inconsistent with the pipe A quirk */
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if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
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active = crtc->active;
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WARN(crtc->active != active,
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"crtc active state doesn't match with hw state "
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"(expected %i, found %i)\n", crtc->active, active);
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|
@ -815,10 +815,10 @@ static const struct dmi_system_id intel_no_lvds[] = {
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},
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{
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.callback = intel_no_lvds_dmi_callback,
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.ident = "Hewlett-Packard HP t5740e Thin Client",
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.ident = "Hewlett-Packard HP t5740",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
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DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"),
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DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
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},
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},
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{
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|
@ -1776,7 +1776,7 @@ static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
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* Assume that the preferred modes are
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* arranged in priority order.
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*/
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intel_ddc_get_modes(connector, intel_sdvo->i2c);
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intel_ddc_get_modes(connector, &intel_sdvo->ddc);
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if (list_empty(&connector->probed_modes) == false)
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goto end;
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@ -1034,13 +1034,14 @@ static int mga_crtc_mode_set(struct drm_crtc *crtc,
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else
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hi_pri_lvl = 5;
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WREG8(0x1fde, 0x06);
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WREG8(0x1fdf, hi_pri_lvl);
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WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
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WREG8(MGAREG_CRTCEXT_DATA, hi_pri_lvl);
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} else {
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WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
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if (mdev->reg_1e24 >= 0x01)
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WREG8(0x1fdf, 0x03);
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WREG8(MGAREG_CRTCEXT_DATA, 0x03);
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else
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WREG8(0x1fdf, 0x04);
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WREG8(MGAREG_CRTCEXT_DATA, 0x04);
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}
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}
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return 0;
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|
@ -50,11 +50,16 @@ nv50_dac_sense(struct nv50_disp_priv *priv, int or, u32 loadval)
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{
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const u32 doff = (or * 0x800);
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int load = -EINVAL;
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nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80150000);
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nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
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nv_wr32(priv, 0x61a00c + doff, 0x00100000 | loadval);
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udelay(9500);
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mdelay(9);
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udelay(500);
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nv_wr32(priv, 0x61a00c + doff, 0x80000000);
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load = (nv_rd32(priv, 0x61a00c + doff) & 0x38000000) >> 27;
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nv_wr32(priv, 0x61a00c + doff, 0x00000000);
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nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80550000);
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nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
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return load;
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}
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|
@ -55,6 +55,10 @@ nv84_hdmi_ctrl(struct nv50_disp_priv *priv, int head, int or, u32 data)
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nv_wr32(priv, 0x616510 + hoff, 0x00000000);
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nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000001);
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nv_mask(priv, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
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nv_mask(priv, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
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nv_mask(priv, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
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/* ??? */
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nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
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nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
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|
@ -40,14 +40,13 @@
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* FIFO channel objects
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******************************************************************************/
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void
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nv50_fifo_playlist_update(struct nv50_fifo_priv *priv)
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static void
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nv50_fifo_playlist_update_locked(struct nv50_fifo_priv *priv)
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{
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struct nouveau_bar *bar = nouveau_bar(priv);
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struct nouveau_gpuobj *cur;
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int i, p;
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mutex_lock(&nv_subdev(priv)->mutex);
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cur = priv->playlist[priv->cur_playlist];
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priv->cur_playlist = !priv->cur_playlist;
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@ -61,6 +60,13 @@ nv50_fifo_playlist_update(struct nv50_fifo_priv *priv)
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nv_wr32(priv, 0x0032f4, cur->addr >> 12);
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nv_wr32(priv, 0x0032ec, p);
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nv_wr32(priv, 0x002500, 0x00000101);
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}
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void
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nv50_fifo_playlist_update(struct nv50_fifo_priv *priv)
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{
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mutex_lock(&nv_subdev(priv)->mutex);
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nv50_fifo_playlist_update_locked(priv);
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mutex_unlock(&nv_subdev(priv)->mutex);
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}
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@ -489,7 +495,7 @@ nv50_fifo_init(struct nouveau_object *object)
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for (i = 0; i < 128; i++)
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nv_wr32(priv, 0x002600 + (i * 4), 0x00000000);
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nv50_fifo_playlist_update(priv);
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nv50_fifo_playlist_update_locked(priv);
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nv_wr32(priv, 0x003200, 0x00000001);
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nv_wr32(priv, 0x003250, 0x00000001);
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@ -218,7 +218,7 @@ struct nv04_display_class {
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#define NV50_DISP_DAC_PWR_STATE 0x00000040
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#define NV50_DISP_DAC_PWR_STATE_ON 0x00000000
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#define NV50_DISP_DAC_PWR_STATE_OFF 0x00000040
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#define NV50_DISP_DAC_LOAD 0x0002000c
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#define NV50_DISP_DAC_LOAD 0x00020100
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#define NV50_DISP_DAC_LOAD_VALUE 0x00000007
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#define NV50_DISP_PIOR_MTHD 0x00030000
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@ -1554,7 +1554,9 @@ nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
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{
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struct nv50_disp *disp = nv50_disp(encoder->dev);
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int ret, or = nouveau_encoder(encoder)->or;
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u32 load = 0;
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u32 load = nouveau_drm(encoder->dev)->vbios.dactestval;
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if (load == 0)
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load = 340;
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ret = nv_exec(disp->core, NV50_DISP_DAC_LOAD + or, &load, sizeof(load));
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if (ret || load != 7)
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@ -667,6 +667,8 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
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int
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atombios_get_encoder_mode(struct drm_encoder *encoder)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct drm_connector *connector;
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struct radeon_connector *radeon_connector;
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@ -693,7 +695,8 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
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case DRM_MODE_CONNECTOR_DVII:
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case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
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if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
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radeon_audio)
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radeon_audio &&
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!ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
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return ATOM_ENCODER_MODE_HDMI;
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else if (radeon_connector->use_digital)
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return ATOM_ENCODER_MODE_DVI;
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@ -704,7 +707,8 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
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case DRM_MODE_CONNECTOR_HDMIA:
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default:
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if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
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radeon_audio)
|
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radeon_audio &&
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!ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
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return ATOM_ENCODER_MODE_HDMI;
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else
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return ATOM_ENCODER_MODE_DVI;
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@ -718,7 +722,8 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
|
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(dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
|
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return ATOM_ENCODER_MODE_DP;
|
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else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
|
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radeon_audio)
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radeon_audio &&
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!ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
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return ATOM_ENCODER_MODE_HDMI;
|
||||
else
|
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return ATOM_ENCODER_MODE_DVI;
|
||||
|
@ -4754,6 +4754,12 @@ static int evergreen_startup(struct radeon_device *rdev)
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||||
rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
|
||||
|
||||
/* Enable IRQ */
|
||||
if (!rdev->irq.installed) {
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
r = r600_irq_init(rdev);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: IH init failed (%d).\n", r);
|
||||
@ -4923,10 +4929,6 @@ int evergreen_init(struct radeon_device *rdev)
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
|
||||
r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
|
||||
|
||||
|
@ -2025,6 +2025,12 @@ static int cayman_startup(struct radeon_device *rdev)
|
||||
}
|
||||
|
||||
/* Enable IRQ */
|
||||
if (!rdev->irq.installed) {
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
r = r600_irq_init(rdev);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: IH init failed (%d).\n", r);
|
||||
@ -2190,10 +2196,6 @@ int cayman_init(struct radeon_device *rdev)
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
ring->ring_obj = NULL;
|
||||
r600_ring_init(rdev, ring, 1024 * 1024);
|
||||
|
||||
|
@ -3869,6 +3869,12 @@ static int r100_startup(struct radeon_device *rdev)
|
||||
}
|
||||
|
||||
/* Enable IRQ */
|
||||
if (!rdev->irq.installed) {
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
r100_irq_set(rdev);
|
||||
rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
|
||||
/* 1M ring buffer */
|
||||
@ -4022,9 +4028,6 @@ int r100_init(struct radeon_device *rdev)
|
||||
r100_mc_init(rdev);
|
||||
/* Fence driver */
|
||||
r = radeon_fence_driver_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
/* Memory manager */
|
||||
|
@ -1382,6 +1382,12 @@ static int r300_startup(struct radeon_device *rdev)
|
||||
}
|
||||
|
||||
/* Enable IRQ */
|
||||
if (!rdev->irq.installed) {
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
r100_irq_set(rdev);
|
||||
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
|
||||
/* 1M ring buffer */
|
||||
@ -1514,9 +1520,6 @@ int r300_init(struct radeon_device *rdev)
|
||||
r300_mc_init(rdev);
|
||||
/* Fence driver */
|
||||
r = radeon_fence_driver_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
/* Memory manager */
|
||||
|
@ -265,6 +265,12 @@ static int r420_startup(struct radeon_device *rdev)
|
||||
}
|
||||
|
||||
/* Enable IRQ */
|
||||
if (!rdev->irq.installed) {
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
r100_irq_set(rdev);
|
||||
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
|
||||
/* 1M ring buffer */
|
||||
@ -411,10 +417,6 @@ int r420_init(struct radeon_device *rdev)
|
||||
if (r) {
|
||||
return r;
|
||||
}
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r) {
|
||||
return r;
|
||||
}
|
||||
/* Memory manager */
|
||||
r = radeon_bo_init(rdev);
|
||||
if (r) {
|
||||
|
@ -194,6 +194,12 @@ static int r520_startup(struct radeon_device *rdev)
|
||||
}
|
||||
|
||||
/* Enable IRQ */
|
||||
if (!rdev->irq.installed) {
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
rs600_irq_set(rdev);
|
||||
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
|
||||
/* 1M ring buffer */
|
||||
@ -295,9 +301,6 @@ int r520_init(struct radeon_device *rdev)
|
||||
rv515_debugfs(rdev);
|
||||
/* Fence driver */
|
||||
r = radeon_fence_driver_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
/* Memory manager */
|
||||
|
@ -1046,6 +1046,24 @@ int r600_mc_wait_for_idle(struct radeon_device *rdev)
|
||||
return -1;
|
||||
}
|
||||
|
||||
uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
|
||||
{
|
||||
uint32_t r;
|
||||
|
||||
WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
|
||||
r = RREG32(R_0028FC_MC_DATA);
|
||||
WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
|
||||
return r;
|
||||
}
|
||||
|
||||
void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
|
||||
{
|
||||
WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
|
||||
S_0028F8_MC_IND_WR_EN(1));
|
||||
WREG32(R_0028FC_MC_DATA, v);
|
||||
WREG32(R_0028F8_MC_INDEX, 0x7F);
|
||||
}
|
||||
|
||||
static void r600_mc_program(struct radeon_device *rdev)
|
||||
{
|
||||
struct rv515_mc_save save;
|
||||
@ -1181,6 +1199,8 @@ static int r600_mc_init(struct radeon_device *rdev)
|
||||
{
|
||||
u32 tmp;
|
||||
int chansize, numchan;
|
||||
uint32_t h_addr, l_addr;
|
||||
unsigned long long k8_addr;
|
||||
|
||||
/* Get VRAM informations */
|
||||
rdev->mc.vram_is_ddr = true;
|
||||
@ -1221,7 +1241,30 @@ static int r600_mc_init(struct radeon_device *rdev)
|
||||
if (rdev->flags & RADEON_IS_IGP) {
|
||||
rs690_pm_info(rdev);
|
||||
rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
|
||||
|
||||
if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
|
||||
/* Use K8 direct mapping for fast fb access. */
|
||||
rdev->fastfb_working = false;
|
||||
h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
|
||||
l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
|
||||
k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
|
||||
#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
|
||||
if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
|
||||
#endif
|
||||
{
|
||||
/* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
|
||||
* memory is present.
|
||||
*/
|
||||
if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
|
||||
DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
|
||||
(unsigned long long)rdev->mc.aper_base, k8_addr);
|
||||
rdev->mc.aper_base = (resource_size_t)k8_addr;
|
||||
rdev->fastfb_working = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
radeon_update_bandwidth_info(rdev);
|
||||
return 0;
|
||||
}
|
||||
@ -3202,6 +3245,12 @@ static int r600_startup(struct radeon_device *rdev)
|
||||
}
|
||||
|
||||
/* Enable IRQ */
|
||||
if (!rdev->irq.installed) {
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
r = r600_irq_init(rdev);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: IH init failed (%d).\n", r);
|
||||
@ -3356,10 +3405,6 @@ int r600_init(struct radeon_device *rdev)
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
|
||||
r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
|
||||
|
||||
|
@ -1342,6 +1342,14 @@
|
||||
#define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */
|
||||
#define PACKET3_SURFACE_BASE_UPDATE 0x73
|
||||
|
||||
#define R_000011_K8_FB_LOCATION 0x11
|
||||
#define R_000012_MC_MISC_UMA_CNTL 0x12
|
||||
#define G_000012_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF)
|
||||
#define R_0028F8_MC_INDEX 0x28F8
|
||||
#define S_0028F8_MC_IND_ADDR(x) (((x) & 0x1FF) << 0)
|
||||
#define C_0028F8_MC_IND_ADDR 0xFFFFFE00
|
||||
#define S_0028F8_MC_IND_WR_EN(x) (((x) & 0x1) << 9)
|
||||
#define R_0028FC_MC_DATA 0x28FC
|
||||
|
||||
#define R_008020_GRBM_SOFT_RESET 0x8020
|
||||
#define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0)
|
||||
|
@ -122,6 +122,10 @@ static void radeon_register_accessor_init(struct radeon_device *rdev)
|
||||
rdev->mc_rreg = &rs600_mc_rreg;
|
||||
rdev->mc_wreg = &rs600_mc_wreg;
|
||||
}
|
||||
if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
|
||||
rdev->mc_rreg = &rs780_mc_rreg;
|
||||
rdev->mc_wreg = &rs780_mc_wreg;
|
||||
}
|
||||
if (rdev->family >= CHIP_R600) {
|
||||
rdev->pciep_rreg = &r600_pciep_rreg;
|
||||
rdev->pciep_wreg = &r600_pciep_wreg;
|
||||
|
@ -347,6 +347,8 @@ extern bool r600_gui_idle(struct radeon_device *rdev);
|
||||
extern void r600_pm_misc(struct radeon_device *rdev);
|
||||
extern void r600_pm_init_profile(struct radeon_device *rdev);
|
||||
extern void rs780_pm_init_profile(struct radeon_device *rdev);
|
||||
extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
|
||||
extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
|
||||
extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
|
||||
extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
|
||||
extern int r600_get_pcie_lanes(struct radeon_device *rdev);
|
||||
|
@ -417,6 +417,12 @@ static int rs400_startup(struct radeon_device *rdev)
|
||||
}
|
||||
|
||||
/* Enable IRQ */
|
||||
if (!rdev->irq.installed) {
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
r100_irq_set(rdev);
|
||||
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
|
||||
/* 1M ring buffer */
|
||||
@ -533,9 +539,6 @@ int rs400_init(struct radeon_device *rdev)
|
||||
rs400_mc_init(rdev);
|
||||
/* Fence driver */
|
||||
r = radeon_fence_driver_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
/* Memory manager */
|
||||
|
@ -923,6 +923,12 @@ static int rs600_startup(struct radeon_device *rdev)
|
||||
}
|
||||
|
||||
/* Enable IRQ */
|
||||
if (!rdev->irq.installed) {
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
rs600_irq_set(rdev);
|
||||
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
|
||||
/* 1M ring buffer */
|
||||
@ -1045,9 +1051,6 @@ int rs600_init(struct radeon_device *rdev)
|
||||
rs600_debugfs(rdev);
|
||||
/* Fence driver */
|
||||
r = radeon_fence_driver_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
/* Memory manager */
|
||||
|
@ -651,6 +651,12 @@ static int rs690_startup(struct radeon_device *rdev)
|
||||
}
|
||||
|
||||
/* Enable IRQ */
|
||||
if (!rdev->irq.installed) {
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
rs600_irq_set(rdev);
|
||||
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
|
||||
/* 1M ring buffer */
|
||||
@ -774,9 +780,6 @@ int rs690_init(struct radeon_device *rdev)
|
||||
rv515_debugfs(rdev);
|
||||
/* Fence driver */
|
||||
r = radeon_fence_driver_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
/* Memory manager */
|
||||
|
@ -532,6 +532,12 @@ static int rv515_startup(struct radeon_device *rdev)
|
||||
}
|
||||
|
||||
/* Enable IRQ */
|
||||
if (!rdev->irq.installed) {
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
rs600_irq_set(rdev);
|
||||
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
|
||||
/* 1M ring buffer */
|
||||
@ -660,9 +666,6 @@ int rv515_init(struct radeon_device *rdev)
|
||||
rv515_debugfs(rdev);
|
||||
/* Fence driver */
|
||||
r = radeon_fence_driver_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
/* Memory manager */
|
||||
|
@ -1887,6 +1887,12 @@ static int rv770_startup(struct radeon_device *rdev)
|
||||
rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
|
||||
|
||||
/* Enable IRQ */
|
||||
if (!rdev->irq.installed) {
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
r = r600_irq_init(rdev);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: IH init failed (%d).\n", r);
|
||||
@ -2045,10 +2051,6 @@ int rv770_init(struct radeon_device *rdev)
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
|
||||
r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
|
||||
|
||||
|
@ -5350,6 +5350,12 @@ static int si_startup(struct radeon_device *rdev)
|
||||
}
|
||||
|
||||
/* Enable IRQ */
|
||||
if (!rdev->irq.installed) {
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
r = si_irq_init(rdev);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: IH init failed (%d).\n", r);
|
||||
@ -5533,10 +5539,6 @@ int si_init(struct radeon_device *rdev)
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = radeon_irq_kms_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
||||
ring->ring_obj = NULL;
|
||||
r600_ring_init(rdev, ring, 1024 * 1024);
|
||||
|
@ -6,6 +6,7 @@ config DRM_TILCDC
|
||||
select DRM_GEM_CMA_HELPER
|
||||
select VIDEOMODE_HELPERS
|
||||
select BACKLIGHT_CLASS_DEVICE
|
||||
select BACKLIGHT_LCD_SUPPORT
|
||||
help
|
||||
Choose this option if you have an TI SoC with LCDC display
|
||||
controller, for example AM33xx in beagle-bone, DA8xx, or
|
||||
|
Loading…
Reference in New Issue
Block a user