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drm/amd/display: update DCN2 uclk switch time
[why] value commited to by HW team is going to be higher than pre-silicon, and will cause underflow if driver not updated [how] update hardcoded value, update pstate switching logic to fix case where with long uclk time we won't allow switch even when we should Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -195,12 +195,10 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
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pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000);
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}
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if (!safe_to_lower && pp_smu && pp_smu->set_pstate_handshake_support) {
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clk_mgr_base->clks.p_state_change_support = false;
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pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, false);
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} else if (safe_to_lower && pp_smu && pp_smu->set_pstate_handshake_support) {
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if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
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clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support;
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pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support);
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if (pp_smu && pp_smu->set_pstate_handshake_support)
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pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support);
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}
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if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
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@ -274,6 +274,12 @@ static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_cl
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return ((safe_to_lower && calc_clk < cur_clk) || calc_clk > cur_clk);
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}
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static inline bool should_update_pstate_support(bool safe_to_lower, bool calc_support, bool cur_support)
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{
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// Whenever we are transitioning pstate support, we always want to notify prior to committing state
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return (calc_support != cur_support) ? !safe_to_lower : false;
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}
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int clk_mgr_helper_get_active_display_cnt(
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struct dc *dc,
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struct dc_state *context);
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