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drivers: net: cpsw: fix cpsw clock gating issue across suspend/resume

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Due to some hardware integration issue, CPSW sliver modules requires a
reset across suspend/resume cycle for a successful clock gating to
CPGMAC (CPSW and Davinci MDIO) in AM335x PG1.0.
This issue is fixed in PG2.x, though to support suspend/resume on PG1.0
this reset is required.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Mugunthan V N 2013-06-18 15:04:35 +05:30 committed by David S. Miller
parent 2bd470fc08
commit 6d3d76f877
1 changed files with 2 additions and 0 deletions
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2
drivers/net/ethernet/ti/cpsw.c
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@ -1976,6 +1976,8 @@ static int cpsw_suspend(struct device *dev)
if (netif_running(ndev))
cpsw_ndo_stop(ndev);
soft_reset("sliver 0", &priv->slaves[0].sliver->soft_reset);
soft_reset("sliver 1", &priv->slaves[1].sliver->soft_reset);
pm_runtime_put_sync(&pdev->dev);
return 0;