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drm/bridge: ti-sn65dsi86: Fixup register names
Order registers by offset and rename bits & masks to match the datasheet. This makes the driver a bit easier to grok and cross-reference with the datasheet. Changes in v3: - Added to the set Cc: Sandeep Panda <spanda@codeaurora.org> Reviewed-by: Sandeep Panda <spanda@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180813213058.184821-3-sean@poorly.run
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Sean Paul
parent
ea24a6221c
commit
6c76c0eb03
@ -18,36 +18,51 @@
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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/* Link Training specific registers */
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#define SN_DEVICE_REV_REG 0x08
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#define SN_HPD_DISABLE_REG 0x5C
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#define SN_DPPLL_SRC_REG 0x0A
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#define SN_DSI_LANES_REG 0x10
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#define SN_DSIA_CLK_FREQ_REG 0x12
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#define SN_ENH_FRAME_REG 0x5A
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#define SN_SSC_CONFIG_REG 0x93
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#define SN_DATARATE_CONFIG_REG 0x94
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#define DPPLL_CLK_SRC_DSICLK BIT(0)
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#define REFCLK_FREQ_MASK GENMASK(3, 1)
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#define REFCLK_FREQ(x) ((x) << 1)
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#define DPPLL_SRC_DP_PLL_LOCK BIT(7)
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#define SN_PLL_ENABLE_REG 0x0D
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#define SN_SCRAMBLE_CONFIG_REG 0x95
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#define SN_DSI_LANES_REG 0x10
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#define CHA_DSI_LANES_MASK GENMASK(4, 3)
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#define CHA_DSI_LANES(x) ((x) << 3)
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#define SN_DSIA_CLK_FREQ_REG 0x12
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#define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20
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#define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24
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#define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C
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#define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D
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#define CHA_HSYNC_POLARITY BIT(7)
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#define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30
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#define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31
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#define CHA_VSYNC_POLARITY BIT(7)
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#define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34
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#define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36
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#define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38
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#define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A
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#define SN_ENH_FRAME_REG 0x5A
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#define VSTREAM_ENABLE BIT(3)
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#define SN_DATA_FORMAT_REG 0x5B
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#define SN_HPD_DISABLE_REG 0x5C
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#define HPD_DISABLE BIT(0)
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#define SN_AUX_WDATA0_REG 0x64
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#define SN_AUX_ADDR_19_16_REG 0x74
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#define SN_AUX_ADDR_15_8_REG 0x75
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#define SN_AUX_ADDR_7_0_REG 0x76
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#define SN_AUX_LENGTH_REG 0x77
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#define SN_AUX_CMD_REG 0x78
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#define AUX_CMD_SEND BIT(1)
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#define AUX_CMD_REQ(x) ((x) << 4)
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#define SN_SSC_CONFIG_REG 0x93
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#define DP_NUM_LANES_MASK GENMASK(5, 4)
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#define DP_NUM_LANES(x) ((x) << 4)
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#define SN_DATARATE_CONFIG_REG 0x94
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#define DP_DATARATE_MASK GENMASK(7, 5)
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#define DP_DATARATE(x) ((x) << 5)
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#define SN_ML_TX_MODE_REG 0x96
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/* video config specific registers */
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#define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20
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#define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24
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#define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C
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#define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D
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#define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30
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#define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31
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#define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34
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#define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36
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#define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38
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#define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A
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#define SN_DATA_FORMAT_REG 0x5B
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#define ML_TX_MAIN_LINK_OFF 0
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#define ML_TX_NORMAL_MODE BIT(0)
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#define MIN_DSI_CLK_FREQ_MHZ 40
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@ -55,22 +70,6 @@
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#define DP_CLK_FUDGE_NUM 10
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#define DP_CLK_FUDGE_DEN 8
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#define DPPLL_CLK_SRC_REFCLK 0
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#define DPPLL_CLK_SRC_DSICLK 1
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#define SN_REFCLK_FREQ_OFFSET 1
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#define SN_DSIA_LANE_OFFSET 3
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#define SN_DP_LANE_OFFSET 4
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#define SN_DP_DATA_RATE_OFFSET 5
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#define SN_SYNC_POLARITY_OFFSET 7
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#define SN_ENABLE_VID_STREAM_BIT BIT(3)
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#define SN_REFCLK_FREQ_BITS GENMASK(3, 1)
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#define SN_DSIA_NUM_LANES_BITS GENMASK(4, 3)
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#define SN_DP_NUM_LANES_BITS GENMASK(5, 4)
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#define SN_DP_DATA_RATE_BITS GENMASK(7, 5)
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#define SN_HPD_DISABLE_BIT BIT(0)
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#define SN_REGULATOR_SUPPLY_NUM 4
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struct ti_sn_bridge {
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@ -299,8 +298,7 @@ static void ti_sn_bridge_disable(struct drm_bridge *bridge)
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drm_panel_disable(pdata->panel);
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/* disable video stream */
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regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG,
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SN_ENABLE_VID_STREAM_BIT, 0);
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regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
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/* semi auto link training mode OFF */
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regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
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/* disable DP PLL */
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@ -363,8 +361,8 @@ static void ti_sn_bridge_set_refclk_freq(struct ti_sn_bridge *pdata)
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if (refclk_lut[i] == refclk_rate)
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break;
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regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG,
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SN_REFCLK_FREQ_BITS, i << SN_REFCLK_FREQ_OFFSET);
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regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
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REFCLK_FREQ(i));
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}
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/**
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@ -401,7 +399,7 @@ static void ti_sn_bridge_set_dsi_dp_rate(struct ti_sn_bridge *pdata)
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break;
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regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
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SN_DP_DATA_RATE_BITS, i << SN_DP_DATA_RATE_OFFSET);
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DP_DATARATE_MASK, DP_DATARATE(i));
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}
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static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata)
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@ -411,9 +409,9 @@ static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata)
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u8 hsync_polarity = 0, vsync_polarity = 0;
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if (mode->flags & DRM_MODE_FLAG_PHSYNC)
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hsync_polarity = BIT(SN_SYNC_POLARITY_OFFSET);
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hsync_polarity = CHA_HSYNC_POLARITY;
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if (mode->flags & DRM_MODE_FLAG_PVSYNC)
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vsync_polarity = BIT(SN_SYNC_POLARITY_OFFSET);
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vsync_polarity = CHA_VSYNC_POLARITY;
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ti_sn_bridge_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
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mode->hdisplay);
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@ -451,14 +449,14 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge)
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drm_panel_prepare(pdata->panel);
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/* DSI_A lane config */
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val = (4 - pdata->dsi->lanes) << SN_DSIA_LANE_OFFSET;
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val = CHA_DSI_LANES(4 - pdata->dsi->lanes);
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regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
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SN_DSIA_NUM_LANES_BITS, val);
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CHA_DSI_LANES_MASK, val);
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/* DP lane config */
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val = (pdata->dsi->lanes - 1) << SN_DP_LANE_OFFSET;
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regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG,
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SN_DP_NUM_LANES_BITS, val);
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val = DP_NUM_LANES(pdata->dsi->lanes - 1);
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regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
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val);
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/* set dsi/dp clk frequency value */
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ti_sn_bridge_set_dsi_dp_rate(pdata);
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@ -489,8 +487,8 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge)
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ti_sn_bridge_set_video_timings(pdata);
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/* enable video stream */
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regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG,
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SN_ENABLE_VID_STREAM_BIT, SN_ENABLE_VID_STREAM_BIT);
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regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
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VSTREAM_ENABLE);
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drm_panel_enable(pdata->panel);
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}
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@ -505,8 +503,8 @@ static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge)
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ti_sn_bridge_set_refclk_freq(pdata);
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/* in case drm_panel is connected then HPD is not supported */
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regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG,
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SN_HPD_DISABLE_BIT, SN_HPD_DISABLE_BIT);
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regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
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HPD_DISABLE);
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}
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static void ti_sn_bridge_post_disable(struct drm_bridge *bridge)
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