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synced 2024-12-22 12:14:01 +08:00
IB/ipath: Fix up error handling
This patch makes chip reset more robust and reduces lock contention between user and kernel TID register updates. Signed-off-by: Ralph Campbell <ralph.campbell@qlogic.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
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@ -558,12 +558,40 @@ static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
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dd->ipath_hwerrmask);
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}
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if (*msg)
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ipath_dev_err(dd, "%s hardware error\n", msg);
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if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) {
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if (hwerrs) {
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/*
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* for /sys status file ; if no trailing } is copied, we'll
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* know it was truncated.
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* if any set that we aren't ignoring; only
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* make the complaint once, in case it's stuck
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* or recurring, and we get here multiple
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* times.
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*/
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ipath_dev_err(dd, "%s hardware error\n", msg);
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if (dd->ipath_flags & IPATH_INITTED) {
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ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
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ipath_setup_pe_setextled(dd,
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INFINIPATH_IBCS_L_STATE_DOWN,
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INFINIPATH_IBCS_LT_STATE_DISABLED);
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ipath_dev_err(dd, "Fatal Hardware Error (freeze "
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"mode), no longer usable, SN %.16s\n",
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dd->ipath_serial);
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isfatal = 1;
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}
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*dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
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/* mark as having had error */
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*dd->ipath_statusp |= IPATH_STATUS_HWERROR;
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/*
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* mark as not usable, at a minimum until driver
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* is reloaded, probably until reboot, since no
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* other reset is possible.
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*/
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dd->ipath_flags &= ~IPATH_INITTED;
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} else
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*msg = 0; /* recovered from all of them */
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if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg && msg) {
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/*
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* for /sys status file ; if no trailing brace is copied,
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* we'll know it was truncated.
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*/
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snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
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"{%s}", msg);
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@ -1127,10 +1155,7 @@ static void ipath_init_pe_variables(struct ipath_devdata *dd)
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INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
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INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
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dd->ipath_eep_st_masks[2].errs_to_log =
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INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET;
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dd->ipath_eep_st_masks[2].errs_to_log = INFINIPATH_E_RESET;
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dd->delay_mult = 2; /* SDR, 4X, can't change */
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}
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@ -1204,6 +1229,9 @@ static int ipath_setup_pe_reset(struct ipath_devdata *dd)
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u64 val;
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int i;
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int ret;
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u16 cmdval;
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pci_read_config_word(dd->pcidev, PCI_COMMAND, &cmdval);
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/* Use ERROR so it shows up in logs, etc. */
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ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
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@ -1231,10 +1259,14 @@ static int ipath_setup_pe_reset(struct ipath_devdata *dd)
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ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n",
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r);
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/* now re-enable memory access */
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pci_write_config_word(dd->pcidev, PCI_COMMAND, cmdval);
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if ((r = pci_enable_device(dd->pcidev)))
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ipath_dev_err(dd, "pci_enable_device failed after "
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"reset: %d\n", r);
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/* whether it worked or not, mark as present, again */
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/*
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* whether it fully enabled or not, mark as present,
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* again (but not INITTED)
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*/
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dd->ipath_flags |= IPATH_PRESENT;
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val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
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if (val == dd->ipath_revision) {
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@ -1273,6 +1305,11 @@ static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
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{
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u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
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unsigned long flags = 0; /* keep gcc quiet */
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int tidx;
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spinlock_t *tidlockp;
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if (!dd->ipath_kregbase)
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return;
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if (pa != dd->ipath_tidinvalid) {
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if (pa & ((1U << 11) - 1)) {
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@ -1302,14 +1339,22 @@ static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
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* call can be done from interrupt level for the port 0 eager TIDs,
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* so we have to use irqsave locks.
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*/
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spin_lock_irqsave(&dd->ipath_tid_lock, flags);
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/*
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* Assumes tidptr always > ipath_egrtidbase
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* if type == RCVHQ_RCV_TYPE_EAGER.
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*/
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tidx = tidptr - dd->ipath_egrtidbase;
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tidlockp = (type == RCVHQ_RCV_TYPE_EAGER && tidx < dd->ipath_rcvegrcnt)
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? &dd->ipath_kernel_tid_lock : &dd->ipath_user_tid_lock;
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spin_lock_irqsave(tidlockp, flags);
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ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf);
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if (dd->ipath_kregbase)
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writel(pa, tidp32);
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writel(pa, tidp32);
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ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef);
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mmiowb();
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spin_unlock_irqrestore(&dd->ipath_tid_lock, flags);
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spin_unlock_irqrestore(tidlockp, flags);
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}
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/**
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* ipath_pe_put_tid_2 - write a TID in chip, Revision 2 or higher
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* @dd: the infinipath device
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@ -1325,6 +1370,10 @@ static void ipath_pe_put_tid_2(struct ipath_devdata *dd, u64 __iomem *tidptr,
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u32 type, unsigned long pa)
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{
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u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
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u32 tidx;
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if (!dd->ipath_kregbase)
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return;
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if (pa != dd->ipath_tidinvalid) {
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if (pa & ((1U << 11) - 1)) {
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@ -1344,8 +1393,8 @@ static void ipath_pe_put_tid_2(struct ipath_devdata *dd, u64 __iomem *tidptr,
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else /* for now, always full 4KB page */
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pa |= 2 << 29;
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}
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if (dd->ipath_kregbase)
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writel(pa, tidp32);
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tidx = tidptr - dd->ipath_egrtidbase;
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writel(pa, tidp32);
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mmiowb();
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}
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@ -319,7 +319,7 @@ static int init_chip_first(struct ipath_devdata *dd)
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else ipath_dbg("%u 2k piobufs @ %p\n",
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dd->ipath_piobcnt2k, dd->ipath_pio2kbase);
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spin_lock_init(&dd->ipath_tid_lock);
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spin_lock_init(&dd->ipath_user_tid_lock);
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spin_lock_init(&dd->ipath_sendctrl_lock);
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spin_lock_init(&dd->ipath_gpio_lock);
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spin_lock_init(&dd->ipath_eep_st_lock);
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@ -407,7 +407,7 @@ struct ipath_devdata {
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u64 __iomem *ipath_egrtidbase;
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/* lock to workaround chip bug 9437 and others */
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spinlock_t ipath_kernel_tid_lock;
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spinlock_t ipath_tid_lock;
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spinlock_t ipath_user_tid_lock;
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spinlock_t ipath_sendctrl_lock;
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/*
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