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ath9k: move PCI code into separate file
Now that we have converted all bus specific routines to replaceable, we can move the PCI specific codes into a separate file. Changes-licensed-under: ISC Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Tested-by: Pavel Roskin <proski@gnu.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Gabor Juhos
John W. Linville
parent
39c3c2f2de
commit
6baff7f9a6
@ -11,6 +11,7 @@ ath9k-y += hw.o \
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xmit.o \
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rc.o
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ath9k-$(CONFIG_PCI) += pci.o
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ath9k-$(CONFIG_ATH9K_DEBUG) += debug.o
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obj-$(CONFIG_ATH9K) += ath9k.o
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@ -18,7 +18,7 @@
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#define CORE_H
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#include <linux/etherdevice.h>
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#include <linux/pci.h>
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#include <linux/device.h>
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#include <net/mac80211.h>
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#include <linux/leds.h>
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#include <linux/rfkill.h>
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@ -767,4 +767,21 @@ static inline void ath_bus_cleanup(struct ath_softc *sc)
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sc->bus_ops->cleanup(sc);
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}
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extern struct ieee80211_ops ath9k_ops;
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irqreturn_t ath_isr(int irq, void *dev);
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void ath_cleanup(struct ath_softc *sc);
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int ath_attach(u16 devid, struct ath_softc *sc);
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void ath_detach(struct ath_softc *sc);
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const char *ath_mac_bb_name(u32 mac_bb_version);
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const char *ath_rf_name(u16 rf_version);
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#ifdef CONFIG_PCI
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int ath_pci_init(void);
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void ath_pci_exit(void);
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#else
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static inline int ath_pci_init(void) { return 0; };
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static inline void ath_pci_exit(void) {};
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#endif
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#endif /* CORE_H */
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@ -28,39 +28,6 @@ MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
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MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
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MODULE_LICENSE("Dual BSD/GPL");
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static struct pci_device_id ath_pci_id_table[] __devinitdata = {
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{ PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
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{ PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
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{ PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
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{ PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
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{ PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
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{ PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
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{ 0 }
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};
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static void ath_detach(struct ath_softc *sc);
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static void ath_cleanup(struct ath_softc *sc);
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/* return bus cachesize in 4B word units */
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static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz)
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{
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u8 u8tmp;
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pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE,
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(u8 *)&u8tmp);
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*csz = (int)u8tmp;
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/*
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* This check was put in to avoid "unplesant" consequences if
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* the bootrom has not fully initialized all PCI devices.
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* Sometimes the cache line size register is not set
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*/
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if (*csz == 0)
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*csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
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}
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static void ath_cache_conf_rate(struct ath_softc *sc,
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struct ieee80211_conf *conf)
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{
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@ -500,7 +467,7 @@ static void ath9k_tasklet(unsigned long data)
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ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
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}
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static irqreturn_t ath_isr(int irq, void *dev)
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irqreturn_t ath_isr(int irq, void *dev)
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{
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struct ath_softc *sc = dev;
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struct ath_hal *ah = sc->sc_ah;
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@ -1279,7 +1246,7 @@ static int ath_start_rfkill_poll(struct ath_softc *sc)
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}
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#endif /* CONFIG_RFKILL */
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static void ath_cleanup(struct ath_softc *sc)
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void ath_cleanup(struct ath_softc *sc)
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{
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ath_detach(sc);
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free_irq(sc->irq, sc);
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@ -1287,7 +1254,7 @@ static void ath_cleanup(struct ath_softc *sc)
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ieee80211_free_hw(sc->hw);
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}
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static void ath_detach(struct ath_softc *sc)
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void ath_detach(struct ath_softc *sc)
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{
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struct ieee80211_hw *hw = sc->hw;
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int i = 0;
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@ -1541,7 +1508,7 @@ bad:
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return error;
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}
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static int ath_attach(u16 devid, struct ath_softc *sc)
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int ath_attach(u16 devid, struct ath_softc *sc)
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{
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struct ieee80211_hw *hw = sc->hw;
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int error = 0;
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@ -2462,7 +2429,7 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
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return ret;
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}
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static struct ieee80211_ops ath9k_ops = {
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struct ieee80211_ops ath9k_ops = {
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.tx = ath9k_tx,
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.start = ath9k_start,
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.stop = ath9k_stop,
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@ -2506,7 +2473,7 @@ static struct {
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/*
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* Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
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*/
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static const char *
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const char *
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ath_mac_bb_name(u32 mac_bb_version)
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{
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int i;
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@ -2523,7 +2490,7 @@ ath_mac_bb_name(u32 mac_bb_version)
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/*
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* Return the RF name. "????" is returned if the RF is unknown.
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*/
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static const char *
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const char *
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ath_rf_name(u16 rf_version)
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{
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int i;
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@ -2537,234 +2504,7 @@ ath_rf_name(u16 rf_version)
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return "????";
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}
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static void ath_pci_cleanup(struct ath_softc *sc)
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{
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struct pci_dev *pdev = to_pci_dev(sc->dev);
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pci_iounmap(pdev, sc->mem);
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pci_release_region(pdev, 0);
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pci_disable_device(pdev);
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}
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static struct ath_bus_ops ath_pci_bus_ops = {
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.read_cachesize = ath_pci_read_cachesize,
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.cleanup = ath_pci_cleanup,
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};
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static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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void __iomem *mem;
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struct ath_softc *sc;
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struct ieee80211_hw *hw;
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u8 csz;
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u32 val;
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int ret = 0;
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struct ath_hal *ah;
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if (pci_enable_device(pdev))
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return -EIO;
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ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
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if (ret) {
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printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
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goto bad;
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}
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ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
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if (ret) {
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printk(KERN_ERR "ath9k: 32-bit DMA consistent "
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"DMA enable failed\n");
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goto bad;
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}
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/*
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* Cache line size is used to size and align various
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* structures used to communicate with the hardware.
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*/
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pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
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if (csz == 0) {
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/*
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* Linux 2.4.18 (at least) writes the cache line size
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* register as a 16-bit wide register which is wrong.
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* We must have this setup properly for rx buffer
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* DMA to work so force a reasonable value here if it
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* comes up zero.
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*/
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csz = L1_CACHE_BYTES / sizeof(u32);
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pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
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}
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/*
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* The default setting of latency timer yields poor results,
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* set it to the value used by other systems. It may be worth
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* tweaking this setting more.
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*/
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pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
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pci_set_master(pdev);
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/*
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* Disable the RETRY_TIMEOUT register (0x41) to keep
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* PCI Tx retries from interfering with C3 CPU state.
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*/
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pci_read_config_dword(pdev, 0x40, &val);
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if ((val & 0x0000ff00) != 0)
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pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
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ret = pci_request_region(pdev, 0, "ath9k");
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if (ret) {
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dev_err(&pdev->dev, "PCI memory region reserve error\n");
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ret = -ENODEV;
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goto bad;
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}
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mem = pci_iomap(pdev, 0, 0);
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if (!mem) {
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printk(KERN_ERR "PCI memory map error\n") ;
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ret = -EIO;
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goto bad1;
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}
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hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
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if (hw == NULL) {
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printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
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goto bad2;
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}
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SET_IEEE80211_DEV(hw, &pdev->dev);
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pci_set_drvdata(pdev, hw);
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sc = hw->priv;
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sc->hw = hw;
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sc->dev = &pdev->dev;
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sc->mem = mem;
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sc->bus_ops = &ath_pci_bus_ops;
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if (ath_attach(id->device, sc) != 0) {
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ret = -ENODEV;
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goto bad3;
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}
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/* setup interrupt service routine */
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if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
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printk(KERN_ERR "%s: request_irq failed\n",
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wiphy_name(hw->wiphy));
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ret = -EIO;
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goto bad4;
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}
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sc->irq = pdev->irq;
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ah = sc->sc_ah;
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printk(KERN_INFO
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"%s: Atheros AR%s MAC/BB Rev:%x "
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"AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
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wiphy_name(hw->wiphy),
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ath_mac_bb_name(ah->ah_macVersion),
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ah->ah_macRev,
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ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
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ah->ah_phyRev,
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(unsigned long)mem, pdev->irq);
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return 0;
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bad4:
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ath_detach(sc);
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bad3:
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ieee80211_free_hw(hw);
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bad2:
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pci_iounmap(pdev, mem);
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bad1:
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pci_release_region(pdev, 0);
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bad:
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pci_disable_device(pdev);
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return ret;
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}
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static void ath_pci_remove(struct pci_dev *pdev)
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{
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struct ieee80211_hw *hw = pci_get_drvdata(pdev);
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struct ath_softc *sc = hw->priv;
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ath_cleanup(sc);
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}
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#ifdef CONFIG_PM
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static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
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{
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struct ieee80211_hw *hw = pci_get_drvdata(pdev);
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struct ath_softc *sc = hw->priv;
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ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
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#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
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if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
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cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
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#endif
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pci_save_state(pdev);
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pci_disable_device(pdev);
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pci_set_power_state(pdev, PCI_D3hot);
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return 0;
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}
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static int ath_pci_resume(struct pci_dev *pdev)
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{
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struct ieee80211_hw *hw = pci_get_drvdata(pdev);
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struct ath_softc *sc = hw->priv;
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u32 val;
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int err;
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err = pci_enable_device(pdev);
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if (err)
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return err;
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pci_restore_state(pdev);
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/*
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* Suspend/Resume resets the PCI configuration space, so we have to
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* re-disable the RETRY_TIMEOUT register (0x41) to keep
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* PCI Tx retries from interfering with C3 CPU state
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*/
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pci_read_config_dword(pdev, 0x40, &val);
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if ((val & 0x0000ff00) != 0)
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pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
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/* Enable LED */
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ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
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AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
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ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
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#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
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/*
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* check the h/w rfkill state on resume
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* and start the rfkill poll timer
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*/
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if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
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queue_delayed_work(sc->hw->workqueue,
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&sc->rf_kill.rfkill_poll, 0);
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#endif
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return 0;
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}
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#endif /* CONFIG_PM */
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MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
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static struct pci_driver ath_pci_driver = {
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.name = "ath9k",
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.id_table = ath_pci_id_table,
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.probe = ath_pci_probe,
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.remove = ath_pci_remove,
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#ifdef CONFIG_PM
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.suspend = ath_pci_suspend,
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.resume = ath_pci_resume,
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#endif /* CONFIG_PM */
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};
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static int __init init_ath_pci(void)
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static int __init ath9k_init(void)
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{
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int error;
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@ -2776,26 +2516,30 @@ static int __init init_ath_pci(void)
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printk(KERN_ERR
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"Unable to register rate control algorithm: %d\n",
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error);
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ath_rate_control_unregister();
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return error;
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goto err_out;
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}
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if (pci_register_driver(&ath_pci_driver) < 0) {
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error = ath_pci_init();
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if (error < 0) {
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printk(KERN_ERR
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"ath_pci: No devices found, driver not installed.\n");
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ath_rate_control_unregister();
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pci_unregister_driver(&ath_pci_driver);
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return -ENODEV;
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error = -ENODEV;
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goto err_rate_unregister;
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}
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return 0;
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}
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module_init(init_ath_pci);
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static void __exit exit_ath_pci(void)
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{
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err_rate_unregister:
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ath_rate_control_unregister();
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err_out:
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return error;
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}
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module_init(ath9k_init);
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static void __exit ath9k_exit(void)
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{
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ath_pci_exit();
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ath_rate_control_unregister();
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pci_unregister_driver(&ath_pci_driver);
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printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
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}
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module_exit(exit_ath_pci);
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module_exit(ath9k_exit);
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287
drivers/net/wireless/ath9k/pci.c
Normal file
287
drivers/net/wireless/ath9k/pci.c
Normal file
@ -0,0 +1,287 @@
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/*
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* Copyright (c) 2008 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <linux/nl80211.h>
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#include <linux/pci.h>
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#include "core.h"
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#include "reg.h"
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#include "hw.h"
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static struct pci_device_id ath_pci_id_table[] __devinitdata = {
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{ PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
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{ PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
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{ PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
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{ PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
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{ PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
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{ PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
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{ 0 }
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};
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/* return bus cachesize in 4B word units */
|
||||
static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz)
|
||||
{
|
||||
u8 u8tmp;
|
||||
|
||||
pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE,
|
||||
(u8 *)&u8tmp);
|
||||
*csz = (int)u8tmp;
|
||||
|
||||
/*
|
||||
* This check was put in to avoid "unplesant" consequences if
|
||||
* the bootrom has not fully initialized all PCI devices.
|
||||
* Sometimes the cache line size register is not set
|
||||
*/
|
||||
|
||||
if (*csz == 0)
|
||||
*csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
|
||||
}
|
||||
|
||||
static void ath_pci_cleanup(struct ath_softc *sc)
|
||||
{
|
||||
struct pci_dev *pdev = to_pci_dev(sc->dev);
|
||||
|
||||
pci_iounmap(pdev, sc->mem);
|
||||
pci_release_region(pdev, 0);
|
||||
pci_disable_device(pdev);
|
||||
}
|
||||
|
||||
static struct ath_bus_ops ath_pci_bus_ops = {
|
||||
.read_cachesize = ath_pci_read_cachesize,
|
||||
.cleanup = ath_pci_cleanup,
|
||||
};
|
||||
|
||||
static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
{
|
||||
void __iomem *mem;
|
||||
struct ath_softc *sc;
|
||||
struct ieee80211_hw *hw;
|
||||
u8 csz;
|
||||
u32 val;
|
||||
int ret = 0;
|
||||
struct ath_hal *ah;
|
||||
|
||||
if (pci_enable_device(pdev))
|
||||
return -EIO;
|
||||
|
||||
ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
|
||||
|
||||
if (ret) {
|
||||
printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
|
||||
goto bad;
|
||||
}
|
||||
|
||||
ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
|
||||
|
||||
if (ret) {
|
||||
printk(KERN_ERR "ath9k: 32-bit DMA consistent "
|
||||
"DMA enable failed\n");
|
||||
goto bad;
|
||||
}
|
||||
|
||||
/*
|
||||
* Cache line size is used to size and align various
|
||||
* structures used to communicate with the hardware.
|
||||
*/
|
||||
pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
|
||||
if (csz == 0) {
|
||||
/*
|
||||
* Linux 2.4.18 (at least) writes the cache line size
|
||||
* register as a 16-bit wide register which is wrong.
|
||||
* We must have this setup properly for rx buffer
|
||||
* DMA to work so force a reasonable value here if it
|
||||
* comes up zero.
|
||||
*/
|
||||
csz = L1_CACHE_BYTES / sizeof(u32);
|
||||
pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
|
||||
}
|
||||
/*
|
||||
* The default setting of latency timer yields poor results,
|
||||
* set it to the value used by other systems. It may be worth
|
||||
* tweaking this setting more.
|
||||
*/
|
||||
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
|
||||
|
||||
pci_set_master(pdev);
|
||||
|
||||
/*
|
||||
* Disable the RETRY_TIMEOUT register (0x41) to keep
|
||||
* PCI Tx retries from interfering with C3 CPU state.
|
||||
*/
|
||||
pci_read_config_dword(pdev, 0x40, &val);
|
||||
if ((val & 0x0000ff00) != 0)
|
||||
pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
|
||||
|
||||
ret = pci_request_region(pdev, 0, "ath9k");
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "PCI memory region reserve error\n");
|
||||
ret = -ENODEV;
|
||||
goto bad;
|
||||
}
|
||||
|
||||
mem = pci_iomap(pdev, 0, 0);
|
||||
if (!mem) {
|
||||
printk(KERN_ERR "PCI memory map error\n") ;
|
||||
ret = -EIO;
|
||||
goto bad1;
|
||||
}
|
||||
|
||||
hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
|
||||
if (hw == NULL) {
|
||||
printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
|
||||
goto bad2;
|
||||
}
|
||||
|
||||
SET_IEEE80211_DEV(hw, &pdev->dev);
|
||||
pci_set_drvdata(pdev, hw);
|
||||
|
||||
sc = hw->priv;
|
||||
sc->hw = hw;
|
||||
sc->dev = &pdev->dev;
|
||||
sc->mem = mem;
|
||||
sc->bus_ops = &ath_pci_bus_ops;
|
||||
|
||||
if (ath_attach(id->device, sc) != 0) {
|
||||
ret = -ENODEV;
|
||||
goto bad3;
|
||||
}
|
||||
|
||||
/* setup interrupt service routine */
|
||||
|
||||
if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
|
||||
printk(KERN_ERR "%s: request_irq failed\n",
|
||||
wiphy_name(hw->wiphy));
|
||||
ret = -EIO;
|
||||
goto bad4;
|
||||
}
|
||||
|
||||
sc->irq = pdev->irq;
|
||||
|
||||
ah = sc->sc_ah;
|
||||
printk(KERN_INFO
|
||||
"%s: Atheros AR%s MAC/BB Rev:%x "
|
||||
"AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
|
||||
wiphy_name(hw->wiphy),
|
||||
ath_mac_bb_name(ah->ah_macVersion),
|
||||
ah->ah_macRev,
|
||||
ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
|
||||
ah->ah_phyRev,
|
||||
(unsigned long)mem, pdev->irq);
|
||||
|
||||
return 0;
|
||||
bad4:
|
||||
ath_detach(sc);
|
||||
bad3:
|
||||
ieee80211_free_hw(hw);
|
||||
bad2:
|
||||
pci_iounmap(pdev, mem);
|
||||
bad1:
|
||||
pci_release_region(pdev, 0);
|
||||
bad:
|
||||
pci_disable_device(pdev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void ath_pci_remove(struct pci_dev *pdev)
|
||||
{
|
||||
struct ieee80211_hw *hw = pci_get_drvdata(pdev);
|
||||
struct ath_softc *sc = hw->priv;
|
||||
|
||||
ath_cleanup(sc);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
||||
static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
|
||||
{
|
||||
struct ieee80211_hw *hw = pci_get_drvdata(pdev);
|
||||
struct ath_softc *sc = hw->priv;
|
||||
|
||||
ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
|
||||
|
||||
#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
|
||||
if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
|
||||
cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
|
||||
#endif
|
||||
|
||||
pci_save_state(pdev);
|
||||
pci_disable_device(pdev);
|
||||
pci_set_power_state(pdev, PCI_D3hot);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ath_pci_resume(struct pci_dev *pdev)
|
||||
{
|
||||
struct ieee80211_hw *hw = pci_get_drvdata(pdev);
|
||||
struct ath_softc *sc = hw->priv;
|
||||
u32 val;
|
||||
int err;
|
||||
|
||||
err = pci_enable_device(pdev);
|
||||
if (err)
|
||||
return err;
|
||||
pci_restore_state(pdev);
|
||||
/*
|
||||
* Suspend/Resume resets the PCI configuration space, so we have to
|
||||
* re-disable the RETRY_TIMEOUT register (0x41) to keep
|
||||
* PCI Tx retries from interfering with C3 CPU state
|
||||
*/
|
||||
pci_read_config_dword(pdev, 0x40, &val);
|
||||
if ((val & 0x0000ff00) != 0)
|
||||
pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
|
||||
|
||||
/* Enable LED */
|
||||
ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
|
||||
AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
|
||||
ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
|
||||
|
||||
#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
|
||||
/*
|
||||
* check the h/w rfkill state on resume
|
||||
* and start the rfkill poll timer
|
||||
*/
|
||||
if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
|
||||
queue_delayed_work(sc->hw->workqueue,
|
||||
&sc->rf_kill.rfkill_poll, 0);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
|
||||
|
||||
static struct pci_driver ath_pci_driver = {
|
||||
.name = "ath9k",
|
||||
.id_table = ath_pci_id_table,
|
||||
.probe = ath_pci_probe,
|
||||
.remove = ath_pci_remove,
|
||||
#ifdef CONFIG_PM
|
||||
.suspend = ath_pci_suspend,
|
||||
.resume = ath_pci_resume,
|
||||
#endif /* CONFIG_PM */
|
||||
};
|
||||
|
||||
int __init ath_pci_init(void)
|
||||
{
|
||||
return pci_register_driver(&ath_pci_driver);
|
||||
}
|
||||
|
||||
void ath_pci_exit(void)
|
||||
{
|
||||
pci_unregister_driver(&ath_pci_driver);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user