mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-16 01:04:08 +08:00
This is the bulk of pin control changes for the v5.6 kernel cycle:
Core changes: - Dropped the chained IRQ setup callback into GPIOLIB as we got rid of the last users of that in this changeset. New drivers: - New driver for Ingenic X1830. - New driver for Freescale i.MX8MP. Driver enhancements: - Fix all remaining Intel drivers to pass their IRQ chips along with the GPIO chips. - Intel Baytrail allocates its irqchip dynamically. - Intel Lynxpoint is thoroughly rewritten and modernized. - Aspeed AST2600 pin muxing and configuration is much improved. - Qualcomm SC7180 functions are updated and wakeup interrupt map is provided. - A whole slew of Renesas SH-PFC cleanups and improvements. - Fix up the Intel DT bindings to use the generic YAML DT bindings schema. (A first user of this.) -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAl4xQIkACgkQQRCzN7AZ XXNchQ/8C4+SAMMcDQm4sIWV1duebynrXuebISqWMhAtYDRjCsRpGCqVSt+iSWod z29pJ/sm0xpG1Bz0bmDZ4oFv7u7+J89a/0Kl4OqI1pbO97Uadu2qGmYxZf2tMtlH CwWVOUAldU9scogRD6Z+qixYdRRpKufpaVaU7ooubHocmgRtzd/VCT2MX76c3w7j 1+yHjoAKM59jpOD/8oEucEYB+5ngyTiMXo3Nms/6ciq52GdtMLE8nK+t7dM+xNLL hMQP95iQ2Xb+cM/bv+vdMyKF6vRxKkkeQ/hWcivGWgdI/BSFg0vCq0mWdc8qWp8k VeIBaTVh5wuaAdkir9dHX/zt6TsRV8ktv88jW773/z4jHr/8PmQUyFMyEA1u1haP yrC/vm4eL6QWCAZeATra5+5FoH2ljzwaY2rgeU0hNixjaF/aIp3GPci7+YmKHTIr 5zZTXKAeuC/nV7g77w4O9iwn+SHWPytWBrfNZ7unyV5fl4XHckY2vNBa/g8xkYyb FBk642EwHRGCULb8m40+cB7TMUzk9aluXge1detJDbqlr2i+tSOWp1c3GSavLl1L 4qRAAS2j6de1H/EaoO7EcArVrSMdPgLdpRmwCMc2xvL0HOprl6y+5iL7x86ZtQHu NHvgnjtw6Z6t9n28f5ZI1iEXUA6EHOHHc/sPPUqScCj4v85B25A= =PnK5 -----END PGP SIGNATURE----- Merge tag 'pinctrl-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes, nothing too exciting about this. Some changes hit arch/sh and arch/arm but are well isolated and acknowledged by the respective arch maintainers. Core changes: - Dropped the chained IRQ setup callback into GPIOLIB as we got rid of the last users of that in this changeset. New drivers: - New driver for Ingenic X1830. - New driver for Freescale i.MX8MP. Driver enhancements: - Fix all remaining Intel drivers to pass their IRQ chips along with the GPIO chips. - Intel Baytrail allocates its irqchip dynamically. - Intel Lynxpoint is thoroughly rewritten and modernized. - Aspeed AST2600 pin muxing and configuration is much improved. - Qualcomm SC7180 functions are updated and wakeup interrupt map is provided. - A whole slew of Renesas SH-PFC cleanups and improvements. - Fix up the Intel DT bindings to use the generic YAML DT bindings schema (a first user of this)" * tag 'pinctrl-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits) pinctrl: madera: Remove extra blank line pinctrl: qcom: Don't lock around irq_set_irq_wake() pinctrl: mvebu: armada-37xx: use use platform api gpio: Drop the chained IRQ handler assign function pinctrl: freescale: Add i.MX8MP pinctrl driver support dt-bindings: imx: Add pinctrl binding doc for i.MX8MP pinctrl: tigerlake: Tiger Lake uses _HID enumeration pinctrl: sunrisepoint: Add Coffee Lake-S ACPI ID pinctrl: iproc: Use platform_get_irq_optional() to avoid error message pinctrl: dt-bindings: Fix some errors in the lgm and pinmux schema pinctrl: intel: Pass irqchip when adding gpiochip pinctrl: intel: Add GPIO <-> pin mapping ranges via callback pinctrl: baytrail: Replace WARN with dev_info_once when setting direct-irq pin to output pinctrl: baytrail: Do not clear IRQ flags on direct-irq enabled pins pinctrl: sunrisepoint: Add missing Interrupt Status register offset pinctrl: sh-pfc: Split R-Car H3 support in two independent drivers pinctrl: artpec6: fix __iomem on reg in set pinctrl: ingenic: Use devm_platform_ioremap_resource() pinctrl: ingenic: Factorize irq_set_type function pinctrl: ingenic: Remove duplicated ingenic_chip_info structures ...
This commit is contained in:
commit
6ba3d7066c
@ -54,8 +54,9 @@ patternProperties:
|
||||
TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3,
|
||||
TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2,
|
||||
THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13,
|
||||
UART6, UART7, UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2,
|
||||
WDTRST3, WDTRST4, ]
|
||||
UART6, UART7, UART8, UART9, USBAD, USBADP, USB2AH, USB2AHP,
|
||||
USB2BD, USB2BH, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3,
|
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WDTRST4, ]
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||||
groups:
|
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allOf:
|
||||
- $ref: "/schemas/types.yaml#/definitions/string"
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||||
@ -85,8 +86,8 @@ patternProperties:
|
||||
TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3,
|
||||
TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2,
|
||||
THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12G0,
|
||||
UART12G1, UART13G0, UART13G1, UART6, UART7, UART8, UART9, VB,
|
||||
VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4, ]
|
||||
UART12G1, UART13G0, UART13G1, UART6, UART7, UART8, UART9, USBA,
|
||||
USBB, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4, ]
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||||
|
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required:
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||||
- compatible
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||||
|
@ -0,0 +1,69 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
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||||
%YAML 1.2
|
||||
---
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||||
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mp-pinctrl.yaml#
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||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
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||||
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||||
title: Freescale IMX8MP IOMUX Controller
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
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|
||||
description:
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||||
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
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for common binding part and usage.
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|
||||
properties:
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compatible:
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const: fsl,imx8mp-iomuxc
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||||
|
||||
reg:
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maxItems: 1
|
||||
|
||||
# Client device subnode's properties
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||||
patternProperties:
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||||
'grp$':
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||||
type: object
|
||||
description:
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||||
Pinctrl node's client devices use subnodes for desired pin configuration.
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||||
Client device subnodes use below standard properties.
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||||
|
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properties:
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fsl,pins:
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allOf:
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||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
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||||
description:
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each entry consists of 6 integers and represents the mux and config
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setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
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mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
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be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last
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integer CONFIG is the pad setting value like pull-up on this pin. Please
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refer to i.MX8M Plus Reference Manual for detailed CONFIG settings.
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||||
required:
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- fsl,pins
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additionalProperties: false
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||||
|
||||
required:
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||||
- compatible
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||||
- reg
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additionalProperties: false
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|
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examples:
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# Pinmux controller node
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- |
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iomuxc: pinctrl@30330000 {
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compatible = "fsl,imx8mp-iomuxc";
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reg = <0x30330000 0x10000>;
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||||
|
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pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
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0x228 0x488 0x5F0 0x0 0x6 0x49
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0x228 0x488 0x000 0x0 0x0 0x49
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||||
>;
|
||||
};
|
||||
};
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||||
|
||||
...
|
@ -10,9 +10,9 @@ GPIO port configuration registers and it is typical to refer to pins using the
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||||
naming scheme "PxN" where x is a character identifying the GPIO port with
|
||||
which the pin is associated and N is an integer from 0 to 31 identifying the
|
||||
pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
|
||||
PB31 is the last pin in GPIO port B. The jz4740 and the x1000 contains 4 GPIO
|
||||
ports, PA to PD, for a total of 128 pins. The jz4760, the jz4770 and the jz4780
|
||||
contains 6 GPIO ports, PA to PF, for a total of 192 pins.
|
||||
PB31 is the last pin in GPIO port B. The jz4740, the x1000 and the x1830
|
||||
contains 4 GPIO ports, PA to PD, for a total of 128 pins. The jz4760, the
|
||||
jz4770 and the jz4780 contains 6 GPIO ports, PA to PF, for a total of 192 pins.
|
||||
|
||||
|
||||
Required properties:
|
||||
@ -28,6 +28,7 @@ Required properties:
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||||
- "ingenic,x1000-pinctrl"
|
||||
- "ingenic,x1000e-pinctrl"
|
||||
- "ingenic,x1500-pinctrl"
|
||||
- "ingenic,x1830-pinctrl"
|
||||
- reg: Address range of the pinctrl registers.
|
||||
|
||||
|
||||
@ -40,6 +41,7 @@ Required properties for sub-nodes (GPIO chips):
|
||||
- "ingenic,jz4770-gpio"
|
||||
- "ingenic,jz4780-gpio"
|
||||
- "ingenic,x1000-gpio"
|
||||
- "ingenic,x1830-gpio"
|
||||
- reg: The GPIO bank number.
|
||||
- interrupt-controller: Marks the device node as an interrupt controller.
|
||||
- interrupts: Interrupt specifier for the controllers interrupt.
|
||||
|
75
Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml
Normal file
75
Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml
Normal file
@ -0,0 +1,75 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/intel,lgm-io.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel Lightning Mountain SoC pinmux & GPIO controller binding
|
||||
|
||||
maintainers:
|
||||
- Rahul Tanwar <rahul.tanwar@linux.intel.com>
|
||||
|
||||
description: |
|
||||
Pinmux & GPIO controller controls pin multiplexing & configuration including
|
||||
GPIO function selection & GPIO attributes configuration.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: intel,lgm-io
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
# Client device subnode's properties
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
type: object
|
||||
allOf:
|
||||
- $ref: pincfg-node.yaml#
|
||||
- $ref: pinmux-node.yaml#
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
|
||||
properties:
|
||||
function: true
|
||||
groups: true
|
||||
pins: true
|
||||
pinmux: true
|
||||
bias-pull-up: true
|
||||
bias-pull-down: true
|
||||
drive-strength: true
|
||||
slew-rate: true
|
||||
drive-open-drain: true
|
||||
output-enable: true
|
||||
|
||||
required:
|
||||
- function
|
||||
- groups
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Pinmux controller node
|
||||
- |
|
||||
pinctrl: pinctrl@e2880000 {
|
||||
compatible = "intel,lgm-io";
|
||||
reg = <0xe2880000 0x100000>;
|
||||
|
||||
uart0-pins {
|
||||
pins = <64>, /* UART_RX0 */
|
||||
<65>; /* UART_TX0 */
|
||||
function = "CONSOLE_UART0";
|
||||
pinmux = <1>,
|
||||
<1>;
|
||||
groups = "CONSOLE_UART0";
|
||||
};
|
||||
};
|
||||
|
||||
...
|
@ -1,116 +0,0 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bindings/pinctrl/intel,lgm-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel Lightning Mountain SoC pinmux & GPIO controller binding
|
||||
|
||||
maintainers:
|
||||
- Rahul Tanwar <rahul.tanwar@linux.intel.com>
|
||||
|
||||
description: |
|
||||
Pinmux & GPIO controller controls pin multiplexing & configuration including
|
||||
GPIO function selection & GPIO attributes configuration.
|
||||
|
||||
Please refer to [1] for details of the common pinctrl bindings used by the
|
||||
client devices.
|
||||
|
||||
[1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: intel,lgm-io
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
# Client device subnode's properties
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
|
||||
properties:
|
||||
function:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
description:
|
||||
A string containing the name of the function to mux to the group.
|
||||
|
||||
groups:
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
description:
|
||||
An array of strings identifying the list of groups.
|
||||
|
||||
pins:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description:
|
||||
List of pins to select with this function.
|
||||
|
||||
pinmux:
|
||||
description: The applicable mux group.
|
||||
allOf:
|
||||
- $ref: "/schemas/types.yaml#/definitions/uint32-array"
|
||||
|
||||
bias-pull-up:
|
||||
type: boolean
|
||||
|
||||
bias-pull-down:
|
||||
type: boolean
|
||||
|
||||
drive-strength:
|
||||
description: |
|
||||
Selects the drive strength for the specified pins in mA.
|
||||
0: 2 mA
|
||||
1: 4 mA
|
||||
2: 8 mA
|
||||
3: 12 mA
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [0, 1, 2, 3]
|
||||
|
||||
slew-rate:
|
||||
type: boolean
|
||||
description: |
|
||||
Sets slew rate for specified pins.
|
||||
0: slow slew
|
||||
1: fast slew
|
||||
|
||||
drive-open-drain:
|
||||
type: boolean
|
||||
|
||||
output-enable:
|
||||
type: boolean
|
||||
|
||||
required:
|
||||
- function
|
||||
- groups
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Pinmux controller node
|
||||
- |
|
||||
pinctrl: pinctrl@e2880000 {
|
||||
compatible = "intel,lgm-pinctrl";
|
||||
reg = <0xe2880000 0x100000>;
|
||||
|
||||
uart0-pins {
|
||||
pins = <64>, /* UART_RX0 */
|
||||
<65>; /* UART_TX0 */
|
||||
function = "CONSOLE_UART0";
|
||||
pinmux = <1>,
|
||||
<1>;
|
||||
groups = "CONSOLE_UART0";
|
||||
};
|
||||
};
|
||||
|
||||
...
|
@ -114,7 +114,7 @@ properties:
|
||||
specific binding for the hardware defines whether the entries are integers
|
||||
or strings, and their meaning.
|
||||
|
||||
group:
|
||||
groups:
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
description:
|
||||
the group to apply the properties to, if the driver supports
|
||||
|
@ -125,8 +125,9 @@ to specify in a pin configuration subnode:
|
||||
mi2s_1, mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag,
|
||||
PLL_BIST, pll_bypassnl, pll_reset, prng_rosc, qdss,
|
||||
qdss_cti, qlink_enable, qlink_request, qspi_clk, qspi_cs,
|
||||
qspi_data, qup00, qup01, qup02, qup03, qup04, qup05,
|
||||
qup10, qup11, qup12, qup13, qup14, qup15, sdc1_tb,
|
||||
qspi_data, qup00, qup01, qup02_i2c, qup02_uart, qup03,
|
||||
qup04_i2c, qup04_uart, qup05, qup10, qup11_i2c, qup11_uart,
|
||||
qup12, qup13_i2c, qup13_uart, qup14, qup15, sdc1_tb,
|
||||
sdc2_tb, sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2,
|
||||
tgu_ch3, tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt,
|
||||
usb_phy, vfr_1, _V_GPIO, _V_PPS_IN, _V_PPS_OUT,
|
||||
|
@ -507,11 +507,6 @@ available but we try to move away from this:
|
||||
cascaded irq has to be handled by a threaded interrupt handler.
|
||||
Apart from that it works exactly like the chained irqchip.
|
||||
|
||||
- DEPRECATED: gpiochip_set_chained_irqchip(): sets up a chained cascaded irq
|
||||
handler for a gpio_chip from a parent IRQ and passes the struct gpio_chip*
|
||||
as handler data. Notice that we pass is as the handler data, since the
|
||||
irqchip data is likely used by the parent irqchip.
|
||||
|
||||
- gpiochip_set_nested_irqchip(): sets up a nested cascaded irq handler for a
|
||||
gpio_chip from a parent IRQ. As the parent IRQ has usually been
|
||||
explicitly requested by the driver, this does very little more than
|
||||
|
@ -8383,7 +8383,6 @@ S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel.git
|
||||
F: drivers/gpio/gpio-ich.c
|
||||
F: drivers/gpio/gpio-intel-mid.c
|
||||
F: drivers/gpio/gpio-lynxpoint.c
|
||||
F: drivers/gpio/gpio-merrifield.c
|
||||
F: drivers/gpio/gpio-ml-ioh.c
|
||||
F: drivers/gpio/gpio-pch.c
|
||||
|
@ -201,7 +201,7 @@ static unsigned long pin_highz_conf[] = {
|
||||
};
|
||||
|
||||
/* Pin control settings */
|
||||
static struct pinctrl_map __initdata u300_pinmux_map[] = {
|
||||
static const struct pinctrl_map u300_pinmux_map[] = {
|
||||
/* anonymous maps for chip power and EMIFs */
|
||||
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
|
||||
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
|
||||
|
@ -112,12 +112,6 @@ enum {
|
||||
GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A,
|
||||
GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA,
|
||||
|
||||
/* SSU */
|
||||
GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD,
|
||||
GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF,
|
||||
GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD,
|
||||
GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF,
|
||||
|
||||
/* SCIF */
|
||||
GPIO_FN_SCK0, GPIO_FN_SCK1, GPIO_FN_SCK2, GPIO_FN_SCK3,
|
||||
GPIO_FN_RXD0, GPIO_FN_RXD1, GPIO_FN_RXD2, GPIO_FN_RXD3,
|
||||
|
@ -78,8 +78,15 @@ enum {
|
||||
GPIO_FN_WDTOVF,
|
||||
|
||||
/* CAN */
|
||||
GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1,
|
||||
GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1, GPIO_FN_CRX0_CRX1_CRX2,
|
||||
GPIO_FN_CTX2, GPIO_FN_CRX2,
|
||||
GPIO_FN_CTX1, GPIO_FN_CRX1,
|
||||
GPIO_FN_CTX0, GPIO_FN_CRX0,
|
||||
GPIO_FN_CTX0_CTX1, GPIO_FN_CRX0_CRX1,
|
||||
GPIO_FN_CTX0_CTX1_CTX2, GPIO_FN_CRX0_CRX1_CRX2,
|
||||
GPIO_FN_CTX2_PJ21, GPIO_FN_CRX2_PJ20,
|
||||
GPIO_FN_CTX1_PJ23, GPIO_FN_CRX1_PJ22,
|
||||
GPIO_FN_CTX0_CTX1_PJ23, GPIO_FN_CRX0_CRX1_PJ22,
|
||||
GPIO_FN_CTX0_CTX1_CTX2_PJ21, GPIO_FN_CRX0_CRX1_CRX2_PJ20,
|
||||
|
||||
/* DMAC */
|
||||
GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0,
|
||||
@ -119,12 +126,6 @@ enum {
|
||||
GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A,
|
||||
GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA,
|
||||
|
||||
/* SSU */
|
||||
GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD,
|
||||
GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF,
|
||||
GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD,
|
||||
GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF,
|
||||
|
||||
/* SCIF */
|
||||
GPIO_FN_SCK0, GPIO_FN_RXD0, GPIO_FN_TXD0,
|
||||
GPIO_FN_SCK1, GPIO_FN_RXD1, GPIO_FN_TXD1, GPIO_FN_RTS1, GPIO_FN_CTS1,
|
||||
|
@ -341,14 +341,6 @@ config GPIO_LPC32XX
|
||||
Select this option to enable GPIO driver for
|
||||
NXP LPC32XX devices.
|
||||
|
||||
config GPIO_LYNXPOINT
|
||||
tristate "Intel Lynxpoint GPIO support"
|
||||
depends on ACPI && X86
|
||||
select GPIOLIB_IRQCHIP
|
||||
help
|
||||
driver for GPIO functionality on Intel Lynxpoint PCH chipset
|
||||
Requires ACPI device enumeration code to set up a platform device.
|
||||
|
||||
config GPIO_MB86S7X
|
||||
tristate "GPIO support for Fujitsu MB86S7x Platforms"
|
||||
help
|
||||
|
@ -77,7 +77,6 @@ obj-$(CONFIG_GPIO_LP873X) += gpio-lp873x.o
|
||||
obj-$(CONFIG_GPIO_LP87565) += gpio-lp87565.o
|
||||
obj-$(CONFIG_GPIO_LPC18XX) += gpio-lpc18xx.o
|
||||
obj-$(CONFIG_GPIO_LPC32XX) += gpio-lpc32xx.o
|
||||
obj-$(CONFIG_GPIO_LYNXPOINT) += gpio-lynxpoint.o
|
||||
obj-$(CONFIG_GPIO_MADERA) += gpio-madera.o
|
||||
obj-$(CONFIG_GPIO_MAX3191X) += gpio-max3191x.o
|
||||
obj-$(CONFIG_GPIO_MAX7300) += gpio-max7300.o
|
||||
|
@ -1,471 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* GPIO controller driver for Intel Lynxpoint PCH chipset>
|
||||
* Copyright (c) 2012, Intel Corporation.
|
||||
*
|
||||
* Author: Mathias Nyman <mathias.nyman@linux.intel.com>
|
||||
*/
|
||||
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/gpio/driver.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
/* LynxPoint chipset has support for 94 gpio pins */
|
||||
|
||||
#define LP_NUM_GPIO 94
|
||||
|
||||
/* Bitmapped register offsets */
|
||||
#define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */
|
||||
#define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */
|
||||
#define LP_INT_STAT 0x80
|
||||
#define LP_INT_ENABLE 0x90
|
||||
|
||||
/* Each pin has two 32 bit config registers, starting at 0x100 */
|
||||
#define LP_CONFIG1 0x100
|
||||
#define LP_CONFIG2 0x104
|
||||
|
||||
/* LP_CONFIG1 reg bits */
|
||||
#define OUT_LVL_BIT BIT(31)
|
||||
#define IN_LVL_BIT BIT(30)
|
||||
#define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */
|
||||
#define INT_INV_BIT BIT(3) /* Invert interrupt triggering */
|
||||
#define DIR_BIT BIT(2) /* 0: Output, 1: Input */
|
||||
#define USE_SEL_BIT BIT(0) /* 0: Native, 1: GPIO */
|
||||
|
||||
/* LP_CONFIG2 reg bits */
|
||||
#define GPINDIS_BIT BIT(2) /* disable input sensing */
|
||||
#define GPIWP_BIT (BIT(0) | BIT(1)) /* weak pull options */
|
||||
|
||||
struct lp_gpio {
|
||||
struct gpio_chip chip;
|
||||
struct platform_device *pdev;
|
||||
spinlock_t lock;
|
||||
unsigned long reg_base;
|
||||
};
|
||||
|
||||
/*
|
||||
* Lynxpoint gpios are controlled through both bitmapped registers and
|
||||
* per gpio specific registers. The bitmapped registers are in chunks of
|
||||
* 3 x 32bit registers to cover all 94 gpios
|
||||
*
|
||||
* per gpio specific registers consist of two 32bit registers per gpio
|
||||
* (LP_CONFIG1 and LP_CONFIG2), with 94 gpios there's a total of
|
||||
* 188 config registers.
|
||||
*
|
||||
* A simplified view of the register layout look like this:
|
||||
*
|
||||
* LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers)
|
||||
* LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63
|
||||
* LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94
|
||||
* ...
|
||||
* LP_INT_ENABLE[31:0] ...
|
||||
* LP_INT_ENABLE[63:31] ...
|
||||
* LP_INT_ENABLE[94:64] ...
|
||||
* LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers)
|
||||
* LP0_CONFIG2 (gpio 0) config2 reg for gpio 0
|
||||
* LP1_CONFIG1 (gpio 1) config1 reg for gpio 1
|
||||
* LP1_CONFIG2 (gpio 1) config2 reg for gpio 1
|
||||
* LP2_CONFIG1 (gpio 2) ...
|
||||
* LP2_CONFIG2 (gpio 2) ...
|
||||
* ...
|
||||
* LP94_CONFIG1 (gpio 94) ...
|
||||
* LP94_CONFIG2 (gpio 94) ...
|
||||
*/
|
||||
|
||||
static unsigned long lp_gpio_reg(struct gpio_chip *chip, unsigned offset,
|
||||
int reg)
|
||||
{
|
||||
struct lp_gpio *lg = gpiochip_get_data(chip);
|
||||
int reg_offset;
|
||||
|
||||
if (reg == LP_CONFIG1 || reg == LP_CONFIG2)
|
||||
/* per gpio specific config registers */
|
||||
reg_offset = offset * 8;
|
||||
else
|
||||
/* bitmapped registers */
|
||||
reg_offset = (offset / 32) * 4;
|
||||
|
||||
return lg->reg_base + reg + reg_offset;
|
||||
}
|
||||
|
||||
static int lp_gpio_request(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
struct lp_gpio *lg = gpiochip_get_data(chip);
|
||||
unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
|
||||
unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
|
||||
unsigned long acpi_use = lp_gpio_reg(chip, offset, LP_ACPI_OWNED);
|
||||
|
||||
pm_runtime_get(&lg->pdev->dev); /* should we put if failed */
|
||||
|
||||
/* Fail if BIOS reserved pin for ACPI use */
|
||||
if (!(inl(acpi_use) & BIT(offset % 32))) {
|
||||
dev_err(&lg->pdev->dev, "gpio %d reserved for ACPI\n", offset);
|
||||
return -EBUSY;
|
||||
}
|
||||
/* Fail if pin is in alternate function mode (not GPIO mode) */
|
||||
if (!(inl(reg) & USE_SEL_BIT))
|
||||
return -ENODEV;
|
||||
|
||||
/* enable input sensing */
|
||||
outl(inl(conf2) & ~GPINDIS_BIT, conf2);
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void lp_gpio_free(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
struct lp_gpio *lg = gpiochip_get_data(chip);
|
||||
unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
|
||||
|
||||
/* disable input sensing */
|
||||
outl(inl(conf2) | GPINDIS_BIT, conf2);
|
||||
|
||||
pm_runtime_put(&lg->pdev->dev);
|
||||
}
|
||||
|
||||
static int lp_irq_type(struct irq_data *d, unsigned type)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct lp_gpio *lg = gpiochip_get_data(gc);
|
||||
u32 hwirq = irqd_to_hwirq(d);
|
||||
unsigned long flags;
|
||||
u32 value;
|
||||
unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1);
|
||||
|
||||
if (hwirq >= lg->chip.ngpio)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&lg->lock, flags);
|
||||
value = inl(reg);
|
||||
|
||||
/* set both TRIG_SEL and INV bits to 0 for rising edge */
|
||||
if (type & IRQ_TYPE_EDGE_RISING)
|
||||
value &= ~(TRIG_SEL_BIT | INT_INV_BIT);
|
||||
|
||||
/* TRIG_SEL bit 0, INV bit 1 for falling edge */
|
||||
if (type & IRQ_TYPE_EDGE_FALLING)
|
||||
value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT;
|
||||
|
||||
/* TRIG_SEL bit 1, INV bit 0 for level low */
|
||||
if (type & IRQ_TYPE_LEVEL_LOW)
|
||||
value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT;
|
||||
|
||||
/* TRIG_SEL bit 1, INV bit 1 for level high */
|
||||
if (type & IRQ_TYPE_LEVEL_HIGH)
|
||||
value |= TRIG_SEL_BIT | INT_INV_BIT;
|
||||
|
||||
outl(value, reg);
|
||||
|
||||
if (type & IRQ_TYPE_EDGE_BOTH)
|
||||
irq_set_handler_locked(d, handle_edge_irq);
|
||||
else if (type & IRQ_TYPE_LEVEL_MASK)
|
||||
irq_set_handler_locked(d, handle_level_irq);
|
||||
|
||||
spin_unlock_irqrestore(&lg->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lp_gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
|
||||
return !!(inl(reg) & IN_LVL_BIT);
|
||||
}
|
||||
|
||||
static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
{
|
||||
struct lp_gpio *lg = gpiochip_get_data(chip);
|
||||
unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&lg->lock, flags);
|
||||
|
||||
if (value)
|
||||
outl(inl(reg) | OUT_LVL_BIT, reg);
|
||||
else
|
||||
outl(inl(reg) & ~OUT_LVL_BIT, reg);
|
||||
|
||||
spin_unlock_irqrestore(&lg->lock, flags);
|
||||
}
|
||||
|
||||
static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
struct lp_gpio *lg = gpiochip_get_data(chip);
|
||||
unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&lg->lock, flags);
|
||||
outl(inl(reg) | DIR_BIT, reg);
|
||||
spin_unlock_irqrestore(&lg->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lp_gpio_direction_output(struct gpio_chip *chip,
|
||||
unsigned offset, int value)
|
||||
{
|
||||
struct lp_gpio *lg = gpiochip_get_data(chip);
|
||||
unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
|
||||
unsigned long flags;
|
||||
|
||||
lp_gpio_set(chip, offset, value);
|
||||
|
||||
spin_lock_irqsave(&lg->lock, flags);
|
||||
outl(inl(reg) & ~DIR_BIT, reg);
|
||||
spin_unlock_irqrestore(&lg->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void lp_gpio_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
struct irq_data *data = irq_desc_get_irq_data(desc);
|
||||
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
|
||||
struct lp_gpio *lg = gpiochip_get_data(gc);
|
||||
struct irq_chip *chip = irq_data_get_irq_chip(data);
|
||||
unsigned long reg, ena, pending;
|
||||
u32 base, pin;
|
||||
|
||||
/* check from GPIO controller which pin triggered the interrupt */
|
||||
for (base = 0; base < lg->chip.ngpio; base += 32) {
|
||||
reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
|
||||
ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
|
||||
|
||||
/* Only interrupts that are enabled */
|
||||
pending = inl(reg) & inl(ena);
|
||||
|
||||
for_each_set_bit(pin, &pending, 32) {
|
||||
unsigned irq;
|
||||
|
||||
/* Clear before handling so we don't lose an edge */
|
||||
outl(BIT(pin), reg);
|
||||
|
||||
irq = irq_find_mapping(lg->chip.irq.domain, base + pin);
|
||||
generic_handle_irq(irq);
|
||||
}
|
||||
}
|
||||
chip->irq_eoi(data);
|
||||
}
|
||||
|
||||
static void lp_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
}
|
||||
|
||||
static void lp_irq_mask(struct irq_data *d)
|
||||
{
|
||||
}
|
||||
|
||||
static void lp_irq_enable(struct irq_data *d)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct lp_gpio *lg = gpiochip_get_data(gc);
|
||||
u32 hwirq = irqd_to_hwirq(d);
|
||||
unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&lg->lock, flags);
|
||||
outl(inl(reg) | BIT(hwirq % 32), reg);
|
||||
spin_unlock_irqrestore(&lg->lock, flags);
|
||||
}
|
||||
|
||||
static void lp_irq_disable(struct irq_data *d)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct lp_gpio *lg = gpiochip_get_data(gc);
|
||||
u32 hwirq = irqd_to_hwirq(d);
|
||||
unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&lg->lock, flags);
|
||||
outl(inl(reg) & ~BIT(hwirq % 32), reg);
|
||||
spin_unlock_irqrestore(&lg->lock, flags);
|
||||
}
|
||||
|
||||
static struct irq_chip lp_irqchip = {
|
||||
.name = "LP-GPIO",
|
||||
.irq_mask = lp_irq_mask,
|
||||
.irq_unmask = lp_irq_unmask,
|
||||
.irq_enable = lp_irq_enable,
|
||||
.irq_disable = lp_irq_disable,
|
||||
.irq_set_type = lp_irq_type,
|
||||
.flags = IRQCHIP_SKIP_SET_WAKE,
|
||||
};
|
||||
|
||||
static int lp_gpio_irq_init_hw(struct gpio_chip *chip)
|
||||
{
|
||||
struct lp_gpio *lg = gpiochip_get_data(chip);
|
||||
unsigned long reg;
|
||||
unsigned base;
|
||||
|
||||
for (base = 0; base < lg->chip.ngpio; base += 32) {
|
||||
/* disable gpio pin interrupts */
|
||||
reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
|
||||
outl(0, reg);
|
||||
/* Clear interrupt status register */
|
||||
reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
|
||||
outl(0xffffffff, reg);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lp_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct lp_gpio *lg;
|
||||
struct gpio_chip *gc;
|
||||
struct resource *io_rc, *irq_rc;
|
||||
struct device *dev = &pdev->dev;
|
||||
unsigned long reg_len;
|
||||
int ret = -ENODEV;
|
||||
|
||||
lg = devm_kzalloc(dev, sizeof(struct lp_gpio), GFP_KERNEL);
|
||||
if (!lg)
|
||||
return -ENOMEM;
|
||||
|
||||
lg->pdev = pdev;
|
||||
platform_set_drvdata(pdev, lg);
|
||||
|
||||
io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0);
|
||||
irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
|
||||
if (!io_rc) {
|
||||
dev_err(dev, "missing IO resources\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
lg->reg_base = io_rc->start;
|
||||
reg_len = resource_size(io_rc);
|
||||
|
||||
if (!devm_request_region(dev, lg->reg_base, reg_len, "lp-gpio")) {
|
||||
dev_err(dev, "failed requesting IO region 0x%x\n",
|
||||
(unsigned int)lg->reg_base);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
spin_lock_init(&lg->lock);
|
||||
|
||||
gc = &lg->chip;
|
||||
gc->label = dev_name(dev);
|
||||
gc->owner = THIS_MODULE;
|
||||
gc->request = lp_gpio_request;
|
||||
gc->free = lp_gpio_free;
|
||||
gc->direction_input = lp_gpio_direction_input;
|
||||
gc->direction_output = lp_gpio_direction_output;
|
||||
gc->get = lp_gpio_get;
|
||||
gc->set = lp_gpio_set;
|
||||
gc->base = -1;
|
||||
gc->ngpio = LP_NUM_GPIO;
|
||||
gc->can_sleep = false;
|
||||
gc->parent = dev;
|
||||
|
||||
/* set up interrupts */
|
||||
if (irq_rc && irq_rc->start) {
|
||||
struct gpio_irq_chip *girq;
|
||||
|
||||
girq = &gc->irq;
|
||||
girq->chip = &lp_irqchip;
|
||||
girq->init_hw = lp_gpio_irq_init_hw;
|
||||
girq->parent_handler = lp_gpio_irq_handler;
|
||||
girq->num_parents = 1;
|
||||
girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
|
||||
sizeof(*girq->parents),
|
||||
GFP_KERNEL);
|
||||
if (!girq->parents)
|
||||
return -ENOMEM;
|
||||
girq->parents[0] = (unsigned)irq_rc->start;
|
||||
girq->default_type = IRQ_TYPE_NONE;
|
||||
girq->handler = handle_bad_irq;
|
||||
}
|
||||
|
||||
ret = devm_gpiochip_add_data(dev, gc, lg);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed adding lp-gpio chip\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pm_runtime_enable(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lp_gpio_runtime_suspend(struct device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lp_gpio_runtime_resume(struct device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lp_gpio_resume(struct device *dev)
|
||||
{
|
||||
struct lp_gpio *lg = dev_get_drvdata(dev);
|
||||
unsigned long reg;
|
||||
int i;
|
||||
|
||||
/* on some hardware suspend clears input sensing, re-enable it here */
|
||||
for (i = 0; i < lg->chip.ngpio; i++) {
|
||||
if (gpiochip_is_requested(&lg->chip, i) != NULL) {
|
||||
reg = lp_gpio_reg(&lg->chip, i, LP_CONFIG2);
|
||||
outl(inl(reg) & ~GPINDIS_BIT, reg);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops lp_gpio_pm_ops = {
|
||||
.runtime_suspend = lp_gpio_runtime_suspend,
|
||||
.runtime_resume = lp_gpio_runtime_resume,
|
||||
.resume = lp_gpio_resume,
|
||||
};
|
||||
|
||||
static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = {
|
||||
{ "INT33C7", 0 },
|
||||
{ "INT3437", 0 },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match);
|
||||
|
||||
static int lp_gpio_remove(struct platform_device *pdev)
|
||||
{
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver lp_gpio_driver = {
|
||||
.probe = lp_gpio_probe,
|
||||
.remove = lp_gpio_remove,
|
||||
.driver = {
|
||||
.name = "lp_gpio",
|
||||
.pm = &lp_gpio_pm_ops,
|
||||
.acpi_match_table = ACPI_PTR(lynxpoint_gpio_acpi_match),
|
||||
},
|
||||
};
|
||||
|
||||
static int __init lp_gpio_init(void)
|
||||
{
|
||||
return platform_driver_register(&lp_gpio_driver);
|
||||
}
|
||||
|
||||
static void __exit lp_gpio_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&lp_gpio_driver);
|
||||
}
|
||||
|
||||
subsys_initcall(lp_gpio_init);
|
||||
module_exit(lp_gpio_exit);
|
||||
|
||||
MODULE_AUTHOR("Mathias Nyman (Intel)");
|
||||
MODULE_DESCRIPTION("GPIO interface for Intel Lynxpoint");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:lp_gpio");
|
@ -253,8 +253,7 @@ mediatek_gpio_bank_probe(struct device *dev,
|
||||
|
||||
/*
|
||||
* Directly request the irq here instead of passing
|
||||
* a flow-handler to gpiochip_set_chained_irqchip,
|
||||
* because the irq is shared.
|
||||
* a flow-handler because the irq is shared.
|
||||
*/
|
||||
ret = devm_request_irq(dev, mtk->gpio_irq,
|
||||
mediatek_gpio_irq_handler, IRQF_SHARED,
|
||||
|
@ -251,8 +251,7 @@ static int iproc_gpio_probe(struct platform_device *pdev)
|
||||
|
||||
/*
|
||||
* Directly request the irq here instead of passing
|
||||
* a flow-handler to gpiochip_set_chained_irqchip,
|
||||
* because the irq is shared.
|
||||
* a flow-handler because the irq is shared.
|
||||
*/
|
||||
ret = devm_request_irq(dev, irq, iproc_gpio_irq_handler,
|
||||
IRQF_SHARED, chip->gc.label, &chip->gc);
|
||||
|
@ -1800,7 +1800,7 @@ EXPORT_SYMBOL_GPL(gpiochip_irqchip_irq_valid);
|
||||
* gpiochip_set_cascaded_irqchip() - connects a cascaded irqchip to a gpiochip
|
||||
* @gc: the gpiochip to set the irqchip chain to
|
||||
* @parent_irq: the irq number corresponding to the parent IRQ for this
|
||||
* chained irqchip
|
||||
* cascaded irqchip
|
||||
* @parent_handler: the parent interrupt handler for the accumulated IRQ
|
||||
* coming out of the gpiochip. If the interrupt is nested rather than
|
||||
* cascaded, pass NULL in this handler argument
|
||||
@ -1842,29 +1842,6 @@ static void gpiochip_set_cascaded_irqchip(struct gpio_chip *gc,
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* gpiochip_set_chained_irqchip() - connects a chained irqchip to a gpiochip
|
||||
* @gpiochip: the gpiochip to set the irqchip chain to
|
||||
* @irqchip: the irqchip to chain to the gpiochip
|
||||
* @parent_irq: the irq number corresponding to the parent IRQ for this
|
||||
* chained irqchip
|
||||
* @parent_handler: the parent interrupt handler for the accumulated IRQ
|
||||
* coming out of the gpiochip.
|
||||
*/
|
||||
void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
|
||||
struct irq_chip *irqchip,
|
||||
unsigned int parent_irq,
|
||||
irq_flow_handler_t parent_handler)
|
||||
{
|
||||
if (gpiochip->irq.threaded) {
|
||||
chip_err(gpiochip, "tried to chain a threaded gpiochip\n");
|
||||
return;
|
||||
}
|
||||
|
||||
gpiochip_set_cascaded_irqchip(gpiochip, parent_irq, parent_handler);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(gpiochip_set_chained_irqchip);
|
||||
|
||||
/**
|
||||
* gpiochip_set_nested_irqchip() - connects a nested irqchip to a gpiochip
|
||||
* @gpiochip: the gpiochip to set the irqchip nested handler to
|
||||
|
@ -1583,7 +1583,6 @@ static const struct owl_pinmux_func s700_functions[] = {
|
||||
[S700_MUX_USB30] = FUNCTION(usb30),
|
||||
[S700_MUX_CLKO_25M] = FUNCTION(clko_25m),
|
||||
[S700_MUX_MIPI_CSI] = FUNCTION(mipi_csi),
|
||||
[S700_MUX_DSI] = FUNCTION(dsi),
|
||||
[S700_MUX_NAND] = FUNCTION(nand),
|
||||
[S700_MUX_SPDIF] = FUNCTION(spdif),
|
||||
[S700_MUX_SIRQ0] = FUNCTION(sirq0),
|
||||
|
@ -2439,88 +2439,88 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = {
|
||||
|
||||
static const struct aspeed_pin_config aspeed_g4_configs[] = {
|
||||
/* GPIO banks ranges [A, B], [D, J], [M, R] */
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { D6, D5 }, SCU8C, 16 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { D6, D5 }, SCU8C, 16 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { J21, E18 }, SCU8C, 17 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { J21, E18 }, SCU8C, 17 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { A18, E15 }, SCU8C, 19 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { A18, E15 }, SCU8C, 19 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { D15, B14 }, SCU8C, 20 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { D15, B14 }, SCU8C, 20 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { D18, C17 }, SCU8C, 21 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { D18, C17 }, SCU8C, 21 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { A14, U18 }, SCU8C, 22 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { A14, U18 }, SCU8C, 22 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { A8, E7 }, SCU8C, 23 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { A8, E7 }, SCU8C, 23 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { C22, E20 }, SCU8C, 24 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { C22, E20 }, SCU8C, 24 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { J5, T1 }, SCU8C, 25 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { J5, T1 }, SCU8C, 25 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { U1, U5 }, SCU8C, 26 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { U1, U5 }, SCU8C, 26 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { V3, V5 }, SCU8C, 27 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { V3, V5 }, SCU8C, 27 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { W4, AB2 }, SCU8C, 28 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { W4, AB2 }, SCU8C, 28 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { V6, V7 }, SCU8C, 29 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { V6, V7 }, SCU8C, 29 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { Y6, AB7 }, SCU8C, 30 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { Y6, AB7 }, SCU8C, 30 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { V20, A5 }, SCU8C, 31 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { V20, A5 }, SCU8C, 31 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D6, D5, SCU8C, 16),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D6, D5, SCU8C, 16),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J21, E18, SCU8C, 17),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J21, E18, SCU8C, 17),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A18, E15, SCU8C, 19),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A18, E15, SCU8C, 19),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D15, B14, SCU8C, 20),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D15, B14, SCU8C, 20),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D18, C17, SCU8C, 21),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D18, C17, SCU8C, 21),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A14, U18, SCU8C, 22),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A14, U18, SCU8C, 22),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A8, E7, SCU8C, 23),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A8, E7, SCU8C, 23),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C22, E20, SCU8C, 24),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C22, E20, SCU8C, 24),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J5, T1, SCU8C, 25),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J5, T1, SCU8C, 25),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, U1, U5, SCU8C, 26),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, U1, U5, SCU8C, 26),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V3, V5, SCU8C, 27),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V3, V5, SCU8C, 27),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, W4, AB2, SCU8C, 28),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, W4, AB2, SCU8C, 28),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V6, V7, SCU8C, 29),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V6, V7, SCU8C, 29),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y6, AB7, SCU8C, 30),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y6, AB7, SCU8C, 30),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V20, A5, SCU8C, 31),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V20, A5, SCU8C, 31),
|
||||
|
||||
/* GPIOs T[0-5] (RGMII1 Tx pins) */
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, { A12, A13 }, SCU90, 9 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { A12, A13 }, SCU90, 12 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { A12, A13 }, SCU90, 12 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, A12, A13, SCU90, 9),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A12, A13, SCU90, 12),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A12, A13, SCU90, 12),
|
||||
|
||||
/* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, { D9, D10 }, SCU90, 11 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { D9, D10 }, SCU90, 14 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { D9, D10 }, SCU90, 14 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, D9, D10, SCU90, 11),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D9, D10, SCU90, 14),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D9, D10, SCU90, 14),
|
||||
|
||||
/* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { E11, E10 }, SCU90, 13 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { E11, E10 }, SCU90, 13 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E11, E10, SCU90, 13),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E11, E10, SCU90, 13),
|
||||
|
||||
/* GPIOs V[2-7] (RGMII2 Rx pins) */
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { C9, C8 }, SCU90, 15 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { C9, C8 }, SCU90, 15 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C9, C8, SCU90, 15),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C9, C8, SCU90, 15),
|
||||
|
||||
/* ADC pull-downs (SCUA8[19:4]) */
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { L5, L5 }, SCUA8, 4 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { L5, L5 }, SCUA8, 4 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { L4, L4 }, SCUA8, 5 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { L4, L4 }, SCUA8, 5 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { L3, L3 }, SCUA8, 6 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { L3, L3 }, SCUA8, 6 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { L2, L2 }, SCUA8, 7 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { L2, L2 }, SCUA8, 7 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { L1, L1 }, SCUA8, 8 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { L1, L1 }, SCUA8, 8 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { M5, M5 }, SCUA8, 9 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { M5, M5 }, SCUA8, 9 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { M4, M4 }, SCUA8, 10 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { M4, M4 }, SCUA8, 10 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { M3, M3 }, SCUA8, 11 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { M3, M3 }, SCUA8, 11 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { M2, M2 }, SCUA8, 12 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { M2, M2 }, SCUA8, 12 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { M1, M1 }, SCUA8, 13 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { M1, M1 }, SCUA8, 13 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { N5, N5 }, SCUA8, 14 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { N5, N5 }, SCUA8, 14 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { N4, N4 }, SCUA8, 15 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { N4, N4 }, SCUA8, 15 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { N3, N3 }, SCUA8, 16 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { N3, N3 }, SCUA8, 16 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { N2, N2 }, SCUA8, 17 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { N2, N2 }, SCUA8, 17 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { N1, N1 }, SCUA8, 18 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { N1, N1 }, SCUA8, 18 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { P5, P5 }, SCUA8, 19 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { P5, P5 }, SCUA8, 19 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L5, L5, SCUA8, 4),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L5, L5, SCUA8, 4),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L4, L4, SCUA8, 5),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L4, L4, SCUA8, 5),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L3, L3, SCUA8, 6),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L3, L3, SCUA8, 6),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L2, L2, SCUA8, 7),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L2, L2, SCUA8, 7),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L1, L1, SCUA8, 8),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L1, L1, SCUA8, 8),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M5, M5, SCUA8, 9),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M5, M5, SCUA8, 9),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M4, M4, SCUA8, 10),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M4, M4, SCUA8, 10),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M3, M3, SCUA8, 11),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M3, M3, SCUA8, 11),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M2, M2, SCUA8, 12),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M2, M2, SCUA8, 12),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M1, M1, SCUA8, 13),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M1, M1, SCUA8, 13),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N5, N5, SCUA8, 14),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N5, N5, SCUA8, 14),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N4, N4, SCUA8, 15),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N4, N4, SCUA8, 15),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N3, N3, SCUA8, 16),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N3, N3, SCUA8, 16),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N2, N2, SCUA8, 17),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N2, N2, SCUA8, 17),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N1, N1, SCUA8, 18),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N1, N1, SCUA8, 18),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, P5, P5, SCUA8, 19),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, P5, P5, SCUA8, 19),
|
||||
|
||||
/*
|
||||
* Debounce settings for GPIOs D and E passthrough mode are in
|
||||
@ -2531,14 +2531,14 @@ static const struct aspeed_pin_config aspeed_g4_configs[] = {
|
||||
* controller. Due to this tangle between GPIO and pinctrl we don't yet
|
||||
* fully support pass-through debounce.
|
||||
*/
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { A18, D16 }, SCUA8, 20 },
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { B17, A17 }, SCUA8, 21 },
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { C16, B16 }, SCUA8, 22 },
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { A16, E15 }, SCUA8, 23 },
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { D15, C15 }, SCUA8, 24 },
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { B15, A15 }, SCUA8, 25 },
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { E14, D14 }, SCUA8, 26 },
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { C14, B14 }, SCUA8, 27 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A18, D16, SCUA8, 20),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B17, A17, SCUA8, 21),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, C16, B16, SCUA8, 22),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A16, E15, SCUA8, 23),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, D15, C15, SCUA8, 24),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B15, A15, SCUA8, 25),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, E14, D14, SCUA8, 26),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, C14, B14, SCUA8, 27),
|
||||
};
|
||||
|
||||
static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx,
|
||||
@ -2594,6 +2594,14 @@ static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct aspeed_pin_config_map aspeed_g4_pin_config_map[] = {
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)},
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
|
||||
{ PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, 8, 0, BIT_MASK(0)},
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, 16, 1, BIT_MASK(0)},
|
||||
};
|
||||
|
||||
static const struct aspeed_pinmux_ops aspeed_g4_ops = {
|
||||
.set = aspeed_g4_sig_expr_set,
|
||||
};
|
||||
@ -2610,6 +2618,8 @@ static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = {
|
||||
},
|
||||
.configs = aspeed_g4_configs,
|
||||
.nconfigs = ARRAY_SIZE(aspeed_g4_configs),
|
||||
.confmaps = aspeed_g4_pin_config_map,
|
||||
.nconfmaps = ARRAY_SIZE(aspeed_g4_pin_config_map),
|
||||
};
|
||||
|
||||
static const struct pinmux_ops aspeed_g4_pinmux_ops = {
|
||||
|
@ -2476,124 +2476,124 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = {
|
||||
|
||||
static struct aspeed_pin_config aspeed_g5_configs[] = {
|
||||
/* GPIOA, GPIOQ */
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { B14, B13 }, SCU8C, 16 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { B14, B13 }, SCU8C, 16 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { A11, N20 }, SCU8C, 16 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { A11, N20 }, SCU8C, 16 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B14, B13, SCU8C, 16),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B14, B13, SCU8C, 16),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A11, N20, SCU8C, 16),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A11, N20, SCU8C, 16),
|
||||
|
||||
/* GPIOB, GPIOR */
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { K19, H20 }, SCU8C, 17 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { K19, H20 }, SCU8C, 17 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { AA19, E10 }, SCU8C, 17 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { AA19, E10 }, SCU8C, 17 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, K19, H20, SCU8C, 17),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, K19, H20, SCU8C, 17),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, AA19, E10, SCU8C, 17),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, AA19, E10, SCU8C, 17),
|
||||
|
||||
/* GPIOC, GPIOS*/
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { C12, B11 }, SCU8C, 18 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { C12, B11 }, SCU8C, 18 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { V20, AA20 }, SCU8C, 18 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { V20, AA20 }, SCU8C, 18 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C12, B11, SCU8C, 18),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C12, B11, SCU8C, 18),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V20, AA20, SCU8C, 18),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V20, AA20, SCU8C, 18),
|
||||
|
||||
/* GPIOD, GPIOY */
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { F19, C21 }, SCU8C, 19 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { F19, C21 }, SCU8C, 19 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { R22, P20 }, SCU8C, 19 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { R22, P20 }, SCU8C, 19 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F19, C21, SCU8C, 19),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F19, C21, SCU8C, 19),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, R22, P20, SCU8C, 19),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, R22, P20, SCU8C, 19),
|
||||
|
||||
/* GPIOE, GPIOZ */
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { B20, B19 }, SCU8C, 20 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { B20, B19 }, SCU8C, 20 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { Y20, W21 }, SCU8C, 20 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { Y20, W21 }, SCU8C, 20 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B20, B19, SCU8C, 20),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B20, B19, SCU8C, 20),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y20, W21, SCU8C, 20),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y20, W21, SCU8C, 20),
|
||||
|
||||
/* GPIOF, GPIOAA */
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { J19, H18 }, SCU8C, 21 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { J19, H18 }, SCU8C, 21 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { Y21, P19 }, SCU8C, 21 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { Y21, P19 }, SCU8C, 21 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J19, H18, SCU8C, 21),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J19, H18, SCU8C, 21),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y21, P19, SCU8C, 21),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y21, P19, SCU8C, 21),
|
||||
|
||||
/* GPIOG, GPIOAB */
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { A19, E14 }, SCU8C, 22 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { A19, E14 }, SCU8C, 22 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { N19, R20 }, SCU8C, 22 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { N19, R20 }, SCU8C, 22 },
|
||||
/* GPIOG, GPIOAB */
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A19, E14, SCU8C, 22),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A19, E14, SCU8C, 22),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N19, R20, SCU8C, 22),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N19, R20, SCU8C, 22),
|
||||
|
||||
/* GPIOH, GPIOAC */
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { A18, D18 }, SCU8C, 23 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { A18, D18 }, SCU8C, 23 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { G21, G22 }, SCU8C, 23 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { G21, G22 }, SCU8C, 23 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A18, D18, SCU8C, 23),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A18, D18, SCU8C, 23),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G21, G22, SCU8C, 23),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G21, G22, SCU8C, 23),
|
||||
|
||||
/* GPIOs [I, P] */
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { C18, A15 }, SCU8C, 24 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { C18, A15 }, SCU8C, 24 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { R2, T3 }, SCU8C, 25 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { R2, T3 }, SCU8C, 25 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { L3, R1 }, SCU8C, 26 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { L3, R1 }, SCU8C, 26 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { T2, W1 }, SCU8C, 27 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { T2, W1 }, SCU8C, 27 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { Y1, T5 }, SCU8C, 28 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { Y1, T5 }, SCU8C, 28 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { V2, T4 }, SCU8C, 29 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { V2, T4 }, SCU8C, 29 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { U5, W4 }, SCU8C, 30 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { U5, W4 }, SCU8C, 30 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { V4, V6 }, SCU8C, 31 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { V4, V6 }, SCU8C, 31 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C18, A15, SCU8C, 24),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C18, A15, SCU8C, 24),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, R2, T3, SCU8C, 25),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, R2, T3, SCU8C, 25),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L3, R1, SCU8C, 26),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L3, R1, SCU8C, 26),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, T2, W1, SCU8C, 27),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, T2, W1, SCU8C, 27),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y1, T5, SCU8C, 28),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y1, T5, SCU8C, 28),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V2, T4, SCU8C, 29),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V2, T4, SCU8C, 29),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, U5, W4, SCU8C, 30),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, U5, W4, SCU8C, 30),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V4, V6, SCU8C, 31),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V4, V6, SCU8C, 31),
|
||||
|
||||
/* GPIOs T[0-5] (RGMII1 Tx pins) */
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, { B5, B5 }, SCU90, 8 },
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, { E9, A5 }, SCU90, 9 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { B5, D7 }, SCU90, 12 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { B5, D7 }, SCU90, 12 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B5, B5, SCU90, 8),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, E9, A5, SCU90, 9),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B5, D7, SCU90, 12),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B5, D7, SCU90, 12),
|
||||
|
||||
/* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, { B2, B2 }, SCU90, 10 },
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, { B1, B3 }, SCU90, 11 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { B2, D4 }, SCU90, 14 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { B2, D4 }, SCU90, 14 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B2, B2, SCU90, 10),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B1, B3, SCU90, 11),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B2, D4, SCU90, 14),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B2, D4, SCU90, 14),
|
||||
|
||||
/* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { B4, C4 }, SCU90, 13 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { B4, C4 }, SCU90, 13 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B4, C4, SCU90, 13),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B4, C4, SCU90, 13),
|
||||
|
||||
/* GPIOs V[2-7] (RGMII2 Rx pins) */
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { C2, E6 }, SCU90, 15 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { C2, E6 }, SCU90, 15 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C2, E6, SCU90, 15),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C2, E6, SCU90, 15),
|
||||
|
||||
/* ADC pull-downs (SCUA8[19:4]) */
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { F4, F4 }, SCUA8, 4 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { F4, F4 }, SCUA8, 4 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { F5, F5 }, SCUA8, 5 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { F5, F5 }, SCUA8, 5 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { E2, E2 }, SCUA8, 6 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { E2, E2 }, SCUA8, 6 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { E1, E1 }, SCUA8, 7 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { E1, E1 }, SCUA8, 7 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { F3, F3 }, SCUA8, 8 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { F3, F3 }, SCUA8, 8 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { E3, E3 }, SCUA8, 9 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { E3, E3 }, SCUA8, 9 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { G5, G5 }, SCUA8, 10 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { G5, G5 }, SCUA8, 10 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { G4, G4 }, SCUA8, 11 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { G4, G4 }, SCUA8, 11 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { F2, F2 }, SCUA8, 12 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { F2, F2 }, SCUA8, 12 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { G3, G3 }, SCUA8, 13 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { G3, G3 }, SCUA8, 13 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { G2, G2 }, SCUA8, 14 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { G2, G2 }, SCUA8, 14 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { F1, F1 }, SCUA8, 15 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { F1, F1 }, SCUA8, 15 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { H5, H5 }, SCUA8, 16 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { H5, H5 }, SCUA8, 16 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { G1, G1 }, SCUA8, 17 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { G1, G1 }, SCUA8, 17 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { H3, H3 }, SCUA8, 18 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { H3, H3 }, SCUA8, 18 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { H4, H4 }, SCUA8, 19 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { H4, H4 }, SCUA8, 19 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F4, F4, SCUA8, 4),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F4, F4, SCUA8, 4),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F5, F5, SCUA8, 5),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F5, F5, SCUA8, 5),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E2, E2, SCUA8, 6),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E2, E2, SCUA8, 6),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E1, E1, SCUA8, 7),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E1, E1, SCUA8, 7),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F3, F3, SCUA8, 8),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F3, F3, SCUA8, 8),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E3, E3, SCUA8, 9),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E3, E3, SCUA8, 9),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G5, G5, SCUA8, 10),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G5, G5, SCUA8, 10),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G4, G4, SCUA8, 11),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G4, G4, SCUA8, 11),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F2, F2, SCUA8, 12),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F2, F2, SCUA8, 12),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G3, G3, SCUA8, 13),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G3, G3, SCUA8, 13),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G2, G2, SCUA8, 14),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G2, G2, SCUA8, 14),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F1, F1, SCUA8, 15),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F1, F1, SCUA8, 15),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H5, H5, SCUA8, 16),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H5, H5, SCUA8, 16),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G1, G1, SCUA8, 17),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G1, G1, SCUA8, 17),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H3, H3, SCUA8, 18),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H3, H3, SCUA8, 18),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H4, H4, SCUA8, 19),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H4, H4, SCUA8, 19),
|
||||
|
||||
/*
|
||||
* Debounce settings for GPIOs D and E passthrough mode are in
|
||||
@ -2604,14 +2604,14 @@ static struct aspeed_pin_config aspeed_g5_configs[] = {
|
||||
* controller. Due to this tangle between GPIO and pinctrl we don't yet
|
||||
* fully support pass-through debounce.
|
||||
*/
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { F19, E21 }, SCUA8, 20 },
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { F20, D20 }, SCUA8, 21 },
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { D21, E20 }, SCUA8, 22 },
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { G18, C21 }, SCUA8, 23 },
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { B20, C20 }, SCUA8, 24 },
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { F18, F17 }, SCUA8, 25 },
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { E18, D19 }, SCUA8, 26 },
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { A20, B19 }, SCUA8, 27 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F19, E21, SCUA8, 20),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F20, D20, SCUA8, 21),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, D21, E20, SCUA8, 22),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, G18, C21, SCUA8, 23),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B20, C20, SCUA8, 24),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F18, F17, SCUA8, 25),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, E18, D19, SCUA8, 26),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A20, B19, SCUA8, 27),
|
||||
};
|
||||
|
||||
static struct regmap *aspeed_g5_acquire_regmap(struct aspeed_pinmux_data *ctx,
|
||||
@ -2780,6 +2780,14 @@ static int aspeed_g5_sig_expr_set(struct aspeed_pinmux_data *ctx,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct aspeed_pin_config_map aspeed_g5_pin_config_map[] = {
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)},
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
|
||||
{ PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, 8, 0, BIT_MASK(0)},
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, 16, 1, BIT_MASK(0)},
|
||||
};
|
||||
|
||||
static const struct aspeed_pinmux_ops aspeed_g5_ops = {
|
||||
.eval = aspeed_g5_sig_expr_eval,
|
||||
.set = aspeed_g5_sig_expr_set,
|
||||
@ -2797,6 +2805,8 @@ static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {
|
||||
},
|
||||
.configs = aspeed_g5_configs,
|
||||
.nconfigs = ARRAY_SIZE(aspeed_g5_configs),
|
||||
.confmaps = aspeed_g5_pin_config_map,
|
||||
.nconfmaps = ARRAY_SIZE(aspeed_g5_pin_config_map),
|
||||
};
|
||||
|
||||
static const struct pinmux_ops aspeed_g5_pinmux_ops = {
|
||||
|
@ -26,7 +26,10 @@
|
||||
#define SCU430 0x430 /* Multi-function Pin Control #8 */
|
||||
#define SCU434 0x434 /* Multi-function Pin Control #9 */
|
||||
#define SCU438 0x438 /* Multi-function Pin Control #10 */
|
||||
#define SCU440 0x440 /* USB Multi-function Pin Control #12 */
|
||||
#define SCU450 0x450 /* Multi-function Pin Control #14 */
|
||||
#define SCU454 0x454 /* Multi-function Pin Control #15 */
|
||||
#define SCU458 0x458 /* Multi-function Pin Control #16 */
|
||||
#define SCU4B0 0x4B0 /* Multi-function Pin Control #17 */
|
||||
#define SCU4B4 0x4B4 /* Multi-function Pin Control #18 */
|
||||
#define SCU4B8 0x4B8 /* Multi-function Pin Control #19 */
|
||||
@ -35,9 +38,17 @@
|
||||
#define SCU4D8 0x4D8 /* Multi-function Pin Control #23 */
|
||||
#define SCU500 0x500 /* Hardware Strap 1 */
|
||||
#define SCU510 0x510 /* Hardware Strap 2 */
|
||||
#define SCU610 0x610 /* Disable GPIO Internal Pull-Down #0 */
|
||||
#define SCU614 0x614 /* Disable GPIO Internal Pull-Down #1 */
|
||||
#define SCU618 0x618 /* Disable GPIO Internal Pull-Down #2 */
|
||||
#define SCU61C 0x61c /* Disable GPIO Internal Pull-Down #3 */
|
||||
#define SCU620 0x620 /* Disable GPIO Internal Pull-Down #4 */
|
||||
#define SCU634 0x634 /* Disable GPIO Internal Pull-Down #5 */
|
||||
#define SCU638 0x638 /* Disable GPIO Internal Pull-Down #6 */
|
||||
#define SCU694 0x694 /* Multi-function Pin Control #25 */
|
||||
#define SCUC20 0xC20 /* PCIE configuration Setting Control */
|
||||
|
||||
#define ASPEED_G6_NR_PINS 248
|
||||
#define ASPEED_G6_NR_PINS 256
|
||||
|
||||
#define M24 0
|
||||
SIG_EXPR_LIST_DECL_SESG(M24, MDC3, MDIO3, SIG_DESC_SET(SCU410, 0));
|
||||
@ -1534,6 +1545,78 @@ GROUP_DECL(I3C4, AE25, AF24);
|
||||
FUNC_DECL_2(I3C4, HVI3C4, I3C4);
|
||||
FUNC_GROUP_DECL(FSI2, AE25, AF24);
|
||||
|
||||
#define AF23 248
|
||||
SIG_EXPR_LIST_DECL_SESG(AF23, I3C1SCL, I3C1, SIG_DESC_SET(SCU438, 16));
|
||||
PIN_DECL_(AF23, SIG_EXPR_LIST_PTR(AF23, I3C1SCL));
|
||||
|
||||
#define AE24 249
|
||||
SIG_EXPR_LIST_DECL_SESG(AE24, I3C1SDA, I3C1, SIG_DESC_SET(SCU438, 17));
|
||||
PIN_DECL_(AE24, SIG_EXPR_LIST_PTR(AE24, I3C1SDA));
|
||||
|
||||
FUNC_GROUP_DECL(I3C1, AF23, AE24);
|
||||
|
||||
#define AF22 250
|
||||
SIG_EXPR_LIST_DECL_SESG(AF22, I3C2SCL, I3C2, SIG_DESC_SET(SCU438, 18));
|
||||
PIN_DECL_(AF22, SIG_EXPR_LIST_PTR(AF22, I3C2SCL));
|
||||
|
||||
#define AE22 251
|
||||
SIG_EXPR_LIST_DECL_SESG(AE22, I3C2SDA, I3C2, SIG_DESC_SET(SCU438, 19));
|
||||
PIN_DECL_(AE22, SIG_EXPR_LIST_PTR(AE22, I3C2SDA));
|
||||
|
||||
FUNC_GROUP_DECL(I3C2, AF22, AE22);
|
||||
|
||||
#define USB2ADP_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 0, 0 }
|
||||
#define USB2AD_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 1, 0 }
|
||||
#define USB2AH_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 2, 0 }
|
||||
#define USB2AHP_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 3, 0 }
|
||||
#define USB11BHID_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 0, 0 }
|
||||
#define USB2BD_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 1, 0 }
|
||||
#define USB2BH_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 2, 0 }
|
||||
|
||||
#define A4 252
|
||||
SIG_EXPR_LIST_DECL_SEMG(A4, USB2ADPDP, USBA, USB2ADP, USB2ADP_DESC,
|
||||
SIG_DESC_SET(SCUC20, 16));
|
||||
SIG_EXPR_LIST_DECL_SEMG(A4, USB2ADDP, USBA, USB2AD, USB2AD_DESC);
|
||||
SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHDP, USBA, USB2AH, USB2AH_DESC);
|
||||
SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHPDP, USBA, USB2AHP, USB2AHP_DESC);
|
||||
PIN_DECL_(A4, SIG_EXPR_LIST_PTR(A4, USB2ADPDP), SIG_EXPR_LIST_PTR(A4, USB2ADDP),
|
||||
SIG_EXPR_LIST_PTR(A4, USB2AHDP));
|
||||
|
||||
#define B4 253
|
||||
SIG_EXPR_LIST_DECL_SEMG(B4, USB2ADPDN, USBA, USB2ADP, USB2ADP_DESC);
|
||||
SIG_EXPR_LIST_DECL_SEMG(B4, USB2ADDN, USBA, USB2AD, USB2AD_DESC);
|
||||
SIG_EXPR_LIST_DECL_SEMG(B4, USB2AHDN, USBA, USB2AH, USB2AH_DESC);
|
||||
SIG_EXPR_LIST_DECL_SEMG(B4, USB2AHPDN, USBA, USB2AHP, USB2AHP_DESC);
|
||||
PIN_DECL_(B4, SIG_EXPR_LIST_PTR(B4, USB2ADPDN), SIG_EXPR_LIST_PTR(B4, USB2ADDN),
|
||||
SIG_EXPR_LIST_PTR(B4, USB2AHDN));
|
||||
|
||||
GROUP_DECL(USBA, A4, B4);
|
||||
|
||||
FUNC_DECL_1(USB2ADP, USBA);
|
||||
FUNC_DECL_1(USB2AD, USBA);
|
||||
FUNC_DECL_1(USB2AH, USBA);
|
||||
FUNC_DECL_1(USB2AHP, USBA);
|
||||
|
||||
#define A6 254
|
||||
SIG_EXPR_LIST_DECL_SEMG(A6, USB11BDP, USBB, USB11BHID, USB11BHID_DESC);
|
||||
SIG_EXPR_LIST_DECL_SEMG(A6, USB2BDDP, USBB, USB2BD, USB2BD_DESC);
|
||||
SIG_EXPR_LIST_DECL_SEMG(A6, USB2BHDP, USBB, USB2BH, USB2BH_DESC);
|
||||
PIN_DECL_(A6, SIG_EXPR_LIST_PTR(A6, USB11BDP), SIG_EXPR_LIST_PTR(A6, USB2BDDP),
|
||||
SIG_EXPR_LIST_PTR(A6, USB2BHDP));
|
||||
|
||||
#define B6 255
|
||||
SIG_EXPR_LIST_DECL_SEMG(B6, USB11BDN, USBB, USB11BHID, USB11BHID_DESC);
|
||||
SIG_EXPR_LIST_DECL_SEMG(B6, USB2BDDN, USBB, USB2BD, USB2BD_DESC);
|
||||
SIG_EXPR_LIST_DECL_SEMG(B6, USB2BHDN, USBB, USB2BH, USB2BH_DESC);
|
||||
PIN_DECL_(B6, SIG_EXPR_LIST_PTR(B6, USB11BDN), SIG_EXPR_LIST_PTR(B6, USB2BDDN),
|
||||
SIG_EXPR_LIST_PTR(B6, USB2BHDN));
|
||||
|
||||
GROUP_DECL(USBB, A6, B6);
|
||||
|
||||
FUNC_DECL_1(USB11BHID, USBB);
|
||||
FUNC_DECL_1(USB2BD, USBB);
|
||||
FUNC_DECL_1(USB2BH, USBB);
|
||||
|
||||
/* Pins, groups and functions are sort(1):ed alphabetically for sanity */
|
||||
|
||||
static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
|
||||
@ -1554,6 +1637,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
|
||||
ASPEED_PINCTRL_PIN(A24),
|
||||
ASPEED_PINCTRL_PIN(A25),
|
||||
ASPEED_PINCTRL_PIN(A3),
|
||||
ASPEED_PINCTRL_PIN(A4),
|
||||
ASPEED_PINCTRL_PIN(A6),
|
||||
ASPEED_PINCTRL_PIN(AA11),
|
||||
ASPEED_PINCTRL_PIN(AA12),
|
||||
ASPEED_PINCTRL_PIN(AA16),
|
||||
@ -1625,6 +1710,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
|
||||
ASPEED_PINCTRL_PIN(AE16),
|
||||
ASPEED_PINCTRL_PIN(AE18),
|
||||
ASPEED_PINCTRL_PIN(AE19),
|
||||
ASPEED_PINCTRL_PIN(AE22),
|
||||
ASPEED_PINCTRL_PIN(AE24),
|
||||
ASPEED_PINCTRL_PIN(AE25),
|
||||
ASPEED_PINCTRL_PIN(AE26),
|
||||
ASPEED_PINCTRL_PIN(AE7),
|
||||
@ -1634,6 +1721,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
|
||||
ASPEED_PINCTRL_PIN(AF12),
|
||||
ASPEED_PINCTRL_PIN(AF14),
|
||||
ASPEED_PINCTRL_PIN(AF15),
|
||||
ASPEED_PINCTRL_PIN(AF22),
|
||||
ASPEED_PINCTRL_PIN(AF23),
|
||||
ASPEED_PINCTRL_PIN(AF24),
|
||||
ASPEED_PINCTRL_PIN(AF25),
|
||||
ASPEED_PINCTRL_PIN(AF7),
|
||||
@ -1654,6 +1743,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
|
||||
ASPEED_PINCTRL_PIN(B25),
|
||||
ASPEED_PINCTRL_PIN(B26),
|
||||
ASPEED_PINCTRL_PIN(B3),
|
||||
ASPEED_PINCTRL_PIN(B4),
|
||||
ASPEED_PINCTRL_PIN(B6),
|
||||
ASPEED_PINCTRL_PIN(C1),
|
||||
ASPEED_PINCTRL_PIN(C11),
|
||||
ASPEED_PINCTRL_PIN(C12),
|
||||
@ -1847,6 +1938,8 @@ static const struct aspeed_pin_group aspeed_g6_groups[] = {
|
||||
ASPEED_PINCTRL_GROUP(I2C7),
|
||||
ASPEED_PINCTRL_GROUP(I2C8),
|
||||
ASPEED_PINCTRL_GROUP(I2C9),
|
||||
ASPEED_PINCTRL_GROUP(I3C1),
|
||||
ASPEED_PINCTRL_GROUP(I3C2),
|
||||
ASPEED_PINCTRL_GROUP(I3C3),
|
||||
ASPEED_PINCTRL_GROUP(I3C4),
|
||||
ASPEED_PINCTRL_GROUP(I3C5),
|
||||
@ -2012,6 +2105,8 @@ static const struct aspeed_pin_group aspeed_g6_groups[] = {
|
||||
ASPEED_PINCTRL_GROUP(UART7),
|
||||
ASPEED_PINCTRL_GROUP(UART8),
|
||||
ASPEED_PINCTRL_GROUP(UART9),
|
||||
ASPEED_PINCTRL_GROUP(USBA),
|
||||
ASPEED_PINCTRL_GROUP(USBB),
|
||||
ASPEED_PINCTRL_GROUP(VB),
|
||||
ASPEED_PINCTRL_GROUP(VGAHS),
|
||||
ASPEED_PINCTRL_GROUP(VGAVS),
|
||||
@ -2079,6 +2174,8 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = {
|
||||
ASPEED_PINCTRL_FUNC(I2C7),
|
||||
ASPEED_PINCTRL_FUNC(I2C8),
|
||||
ASPEED_PINCTRL_FUNC(I2C9),
|
||||
ASPEED_PINCTRL_FUNC(I3C1),
|
||||
ASPEED_PINCTRL_FUNC(I3C2),
|
||||
ASPEED_PINCTRL_FUNC(I3C3),
|
||||
ASPEED_PINCTRL_FUNC(I3C4),
|
||||
ASPEED_PINCTRL_FUNC(I3C5),
|
||||
@ -2221,6 +2318,13 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = {
|
||||
ASPEED_PINCTRL_FUNC(UART7),
|
||||
ASPEED_PINCTRL_FUNC(UART8),
|
||||
ASPEED_PINCTRL_FUNC(UART9),
|
||||
ASPEED_PINCTRL_FUNC(USB11BHID),
|
||||
ASPEED_PINCTRL_FUNC(USB2AD),
|
||||
ASPEED_PINCTRL_FUNC(USB2ADP),
|
||||
ASPEED_PINCTRL_FUNC(USB2AH),
|
||||
ASPEED_PINCTRL_FUNC(USB2AHP),
|
||||
ASPEED_PINCTRL_FUNC(USB2BD),
|
||||
ASPEED_PINCTRL_FUNC(USB2BH),
|
||||
ASPEED_PINCTRL_FUNC(VB),
|
||||
ASPEED_PINCTRL_FUNC(VGAHS),
|
||||
ASPEED_PINCTRL_FUNC(VGAVS),
|
||||
@ -2230,6 +2334,260 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = {
|
||||
ASPEED_PINCTRL_FUNC(WDTRST4),
|
||||
};
|
||||
|
||||
static struct aspeed_pin_config aspeed_g6_configs[] = {
|
||||
/* GPIOB7 */
|
||||
ASPEED_PULL_DOWN_PINCONF(J24, SCU610, 15),
|
||||
/* GPIOB6 */
|
||||
ASPEED_PULL_DOWN_PINCONF(H25, SCU610, 14),
|
||||
/* GPIOB5 */
|
||||
ASPEED_PULL_DOWN_PINCONF(G26, SCU610, 13),
|
||||
/* GPIOB4 */
|
||||
ASPEED_PULL_DOWN_PINCONF(J23, SCU610, 12),
|
||||
/* GPIOB3 */
|
||||
ASPEED_PULL_DOWN_PINCONF(J25, SCU610, 11),
|
||||
/* GPIOB2 */
|
||||
ASPEED_PULL_DOWN_PINCONF(H26, SCU610, 10),
|
||||
/* GPIOB1 */
|
||||
ASPEED_PULL_DOWN_PINCONF(K23, SCU610, 9),
|
||||
/* GPIOB0 */
|
||||
ASPEED_PULL_DOWN_PINCONF(J26, SCU610, 8),
|
||||
|
||||
/* GPIOH3 */
|
||||
ASPEED_PULL_DOWN_PINCONF(A17, SCU614, 27),
|
||||
/* GPIOH2 */
|
||||
ASPEED_PULL_DOWN_PINCONF(C18, SCU614, 26),
|
||||
/* GPIOH1 */
|
||||
ASPEED_PULL_DOWN_PINCONF(B18, SCU614, 25),
|
||||
/* GPIOH0 */
|
||||
ASPEED_PULL_DOWN_PINCONF(A18, SCU614, 24),
|
||||
|
||||
/* GPIOL7 */
|
||||
ASPEED_PULL_DOWN_PINCONF(C14, SCU618, 31),
|
||||
/* GPIOL6 */
|
||||
ASPEED_PULL_DOWN_PINCONF(B14, SCU618, 30),
|
||||
/* GPIOL5 */
|
||||
ASPEED_PULL_DOWN_PINCONF(F15, SCU618, 29),
|
||||
/* GPIOL4 */
|
||||
ASPEED_PULL_DOWN_PINCONF(C15, SCU618, 28),
|
||||
|
||||
/* GPIOJ7 */
|
||||
ASPEED_PULL_UP_PINCONF(D19, SCU618, 15),
|
||||
/* GPIOJ6 */
|
||||
ASPEED_PULL_UP_PINCONF(C20, SCU618, 14),
|
||||
/* GPIOJ5 */
|
||||
ASPEED_PULL_UP_PINCONF(A19, SCU618, 13),
|
||||
/* GPIOJ4 */
|
||||
ASPEED_PULL_UP_PINCONF(C19, SCU618, 12),
|
||||
/* GPIOJ3 */
|
||||
ASPEED_PULL_UP_PINCONF(D20, SCU618, 11),
|
||||
/* GPIOJ2 */
|
||||
ASPEED_PULL_UP_PINCONF(E19, SCU618, 10),
|
||||
/* GPIOJ1 */
|
||||
ASPEED_PULL_UP_PINCONF(A20, SCU618, 9),
|
||||
/* GPIOJ0 */
|
||||
ASPEED_PULL_UP_PINCONF(B20, SCU618, 8),
|
||||
|
||||
/* GPIOI7 */
|
||||
ASPEED_PULL_DOWN_PINCONF(A15, SCU618, 7),
|
||||
/* GPIOI6 */
|
||||
ASPEED_PULL_DOWN_PINCONF(B16, SCU618, 6),
|
||||
/* GPIOI5 */
|
||||
ASPEED_PULL_DOWN_PINCONF(E16, SCU618, 5),
|
||||
/* GPIOI4 */
|
||||
ASPEED_PULL_DOWN_PINCONF(C16, SCU618, 4),
|
||||
/* GPIOI3 */
|
||||
ASPEED_PULL_DOWN_PINCONF(D16, SCU618, 3),
|
||||
/* GPIOI2 */
|
||||
ASPEED_PULL_DOWN_PINCONF(E17, SCU618, 2),
|
||||
/* GPIOI1 */
|
||||
ASPEED_PULL_DOWN_PINCONF(A16, SCU618, 1),
|
||||
/* GPIOI0 */
|
||||
ASPEED_PULL_DOWN_PINCONF(D17, SCU618, 0),
|
||||
|
||||
/* GPIOP7 */
|
||||
ASPEED_PULL_DOWN_PINCONF(Y23, SCU61C, 31),
|
||||
/* GPIOP6 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AB24, SCU61C, 30),
|
||||
/* GPIOP5 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AB23, SCU61C, 29),
|
||||
/* GPIOP4 */
|
||||
ASPEED_PULL_DOWN_PINCONF(W23, SCU61C, 28),
|
||||
/* GPIOP3 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AA24, SCU61C, 27),
|
||||
/* GPIOP2 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AA23, SCU61C, 26),
|
||||
/* GPIOP1 */
|
||||
ASPEED_PULL_DOWN_PINCONF(W24, SCU61C, 25),
|
||||
/* GPIOP0 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AB22, SCU61C, 24),
|
||||
|
||||
/* GPIOO7 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AC23, SCU61C, 23),
|
||||
/* GPIOO6 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AC24, SCU61C, 22),
|
||||
/* GPIOO5 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AC22, SCU61C, 21),
|
||||
/* GPIOO4 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AD25, SCU61C, 20),
|
||||
/* GPIOO3 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AD24, SCU61C, 19),
|
||||
/* GPIOO2 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AD23, SCU61C, 18),
|
||||
/* GPIOO1 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AD22, SCU61C, 17),
|
||||
/* GPIOO0 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AD26, SCU61C, 16),
|
||||
|
||||
/* GPION7 */
|
||||
ASPEED_PULL_DOWN_PINCONF(M26, SCU61C, 15),
|
||||
/* GPION6 */
|
||||
ASPEED_PULL_DOWN_PINCONF(N26, SCU61C, 14),
|
||||
/* GPION5 */
|
||||
ASPEED_PULL_DOWN_PINCONF(M23, SCU61C, 13),
|
||||
/* GPION4 */
|
||||
ASPEED_PULL_DOWN_PINCONF(P26, SCU61C, 12),
|
||||
/* GPION3 */
|
||||
ASPEED_PULL_DOWN_PINCONF(N24, SCU61C, 11),
|
||||
/* GPION2 */
|
||||
ASPEED_PULL_DOWN_PINCONF(N25, SCU61C, 10),
|
||||
/* GPION1 */
|
||||
ASPEED_PULL_DOWN_PINCONF(N23, SCU61C, 9),
|
||||
/* GPION0 */
|
||||
ASPEED_PULL_DOWN_PINCONF(P25, SCU61C, 8),
|
||||
|
||||
/* GPIOM7 */
|
||||
ASPEED_PULL_DOWN_PINCONF(D13, SCU61C, 7),
|
||||
/* GPIOM6 */
|
||||
ASPEED_PULL_DOWN_PINCONF(C13, SCU61C, 6),
|
||||
/* GPIOM5 */
|
||||
ASPEED_PULL_DOWN_PINCONF(C12, SCU61C, 5),
|
||||
/* GPIOM4 */
|
||||
ASPEED_PULL_DOWN_PINCONF(B12, SCU61C, 4),
|
||||
/* GPIOM3 */
|
||||
ASPEED_PULL_DOWN_PINCONF(E14, SCU61C, 3),
|
||||
/* GPIOM2 */
|
||||
ASPEED_PULL_DOWN_PINCONF(A12, SCU61C, 2),
|
||||
/* GPIOM1 */
|
||||
ASPEED_PULL_DOWN_PINCONF(B13, SCU61C, 1),
|
||||
/* GPIOM0 */
|
||||
ASPEED_PULL_DOWN_PINCONF(D14, SCU61C, 0),
|
||||
|
||||
/* GPIOS7 */
|
||||
ASPEED_PULL_DOWN_PINCONF(T24, SCU620, 23),
|
||||
/* GPIOS6 */
|
||||
ASPEED_PULL_DOWN_PINCONF(P23, SCU620, 22),
|
||||
/* GPIOS5 */
|
||||
ASPEED_PULL_DOWN_PINCONF(P24, SCU620, 21),
|
||||
/* GPIOS4 */
|
||||
ASPEED_PULL_DOWN_PINCONF(R26, SCU620, 20),
|
||||
/* GPIOS3*/
|
||||
ASPEED_PULL_DOWN_PINCONF(R24, SCU620, 19),
|
||||
/* GPIOS2 */
|
||||
ASPEED_PULL_DOWN_PINCONF(T26, SCU620, 18),
|
||||
/* GPIOS1 */
|
||||
ASPEED_PULL_DOWN_PINCONF(T25, SCU620, 17),
|
||||
/* GPIOS0 */
|
||||
ASPEED_PULL_DOWN_PINCONF(R23, SCU620, 16),
|
||||
|
||||
/* GPIOR7 */
|
||||
ASPEED_PULL_DOWN_PINCONF(U26, SCU620, 15),
|
||||
/* GPIOR6 */
|
||||
ASPEED_PULL_DOWN_PINCONF(W26, SCU620, 14),
|
||||
/* GPIOR5 */
|
||||
ASPEED_PULL_DOWN_PINCONF(T23, SCU620, 13),
|
||||
/* GPIOR4 */
|
||||
ASPEED_PULL_DOWN_PINCONF(U25, SCU620, 12),
|
||||
/* GPIOR3*/
|
||||
ASPEED_PULL_DOWN_PINCONF(V26, SCU620, 11),
|
||||
/* GPIOR2 */
|
||||
ASPEED_PULL_DOWN_PINCONF(V24, SCU620, 10),
|
||||
/* GPIOR1 */
|
||||
ASPEED_PULL_DOWN_PINCONF(U24, SCU620, 9),
|
||||
/* GPIOR0 */
|
||||
ASPEED_PULL_DOWN_PINCONF(V25, SCU620, 8),
|
||||
|
||||
/* GPIOX7 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AB10, SCU634, 31),
|
||||
/* GPIOX6 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AF9, SCU634, 30),
|
||||
/* GPIOX5 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AD9, SCU634, 29),
|
||||
/* GPIOX4 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AB9, SCU634, 28),
|
||||
/* GPIOX3*/
|
||||
ASPEED_PULL_DOWN_PINCONF(AF8, SCU634, 27),
|
||||
/* GPIOX2 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AC9, SCU634, 26),
|
||||
/* GPIOX1 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AA9, SCU634, 25),
|
||||
/* GPIOX0 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AE8, SCU634, 24),
|
||||
|
||||
/* GPIOV7 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AF15, SCU634, 15),
|
||||
/* GPIOV6 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AD15, SCU634, 14),
|
||||
/* GPIOV5 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AE14, SCU634, 13),
|
||||
/* GPIOV4 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AE15, SCU634, 12),
|
||||
/* GPIOV3*/
|
||||
ASPEED_PULL_DOWN_PINCONF(AC15, SCU634, 11),
|
||||
/* GPIOV2 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AD14, SCU634, 10),
|
||||
/* GPIOV1 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AF14, SCU634, 9),
|
||||
/* GPIOV0 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AB15, SCU634, 8),
|
||||
|
||||
/* GPIOZ7 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AF10, SCU638, 15),
|
||||
/* GPIOZ6 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AD11, SCU638, 14),
|
||||
/* GPIOZ5 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AA11, SCU638, 13),
|
||||
/* GPIOZ4 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AC11, SCU638, 12),
|
||||
/* GPIOZ3*/
|
||||
ASPEED_PULL_DOWN_PINCONF(AB11, SCU638, 11),
|
||||
|
||||
/* GPIOZ1 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AD10, SCU638, 9),
|
||||
/* GPIOZ0 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AC10, SCU638, 8),
|
||||
|
||||
/* GPIOY6 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AC12, SCU638, 6),
|
||||
/* GPIOY5 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AF12, SCU638, 5),
|
||||
/* GPIOY4 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AE12, SCU638, 4),
|
||||
/* GPIOY3 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AA12, SCU638, 3),
|
||||
/* GPIOY2 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AE11, SCU638, 2),
|
||||
/* GPIOY1 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AD12, SCU638, 1),
|
||||
/* GPIOY0 */
|
||||
ASPEED_PULL_DOWN_PINCONF(AF11, SCU638, 0),
|
||||
|
||||
/* LAD3 */
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, { AC7, AC7 }, SCU454, GENMASK(31, 30)},
|
||||
/* LAD2 */
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, { AC8, AC8 }, SCU454, GENMASK(29, 28)},
|
||||
/* LAD1 */
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, { AB8, AB8 }, SCU454, GENMASK(27, 26)},
|
||||
/* LAD0 */
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, { AB7, AB7 }, SCU454, GENMASK(25, 24)},
|
||||
|
||||
/* MAC3 */
|
||||
{ PIN_CONFIG_POWER_SOURCE, { H24, E26 }, SCU458, BIT_MASK(4)},
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, { H24, E26 }, SCU458, GENMASK(1, 0)},
|
||||
/* MAC4 */
|
||||
{ PIN_CONFIG_POWER_SOURCE, { F24, B24 }, SCU458, BIT_MASK(5)},
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, { F24, B24 }, SCU458, GENMASK(3, 2)},
|
||||
};
|
||||
|
||||
/**
|
||||
* Configure a pin's signal by applying an expression's descriptor state for
|
||||
* all descriptors in the expression.
|
||||
@ -2297,6 +2655,20 @@ static int aspeed_g6_sig_expr_set(struct aspeed_pinmux_data *ctx,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct aspeed_pin_config_map aspeed_g6_pin_config_map[] = {
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)},
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
|
||||
{ PIN_CONFIG_BIAS_PULL_UP, 0, 1, BIT_MASK(0)},
|
||||
{ PIN_CONFIG_BIAS_PULL_UP, -1, 0, BIT_MASK(0)},
|
||||
{ PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, 4, 0, GENMASK(1, 0)},
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, 8, 1, GENMASK(1, 0)},
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, 12, 2, GENMASK(1, 0)},
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, 16, 3, GENMASK(1, 0)},
|
||||
{ PIN_CONFIG_POWER_SOURCE, 3300, 0, BIT_MASK(0)},
|
||||
{ PIN_CONFIG_POWER_SOURCE, 1800, 1, BIT_MASK(0)},
|
||||
};
|
||||
|
||||
static const struct aspeed_pinmux_ops aspeed_g5_ops = {
|
||||
.set = aspeed_g6_sig_expr_set,
|
||||
};
|
||||
@ -2311,6 +2683,10 @@ static struct aspeed_pinctrl_data aspeed_g6_pinctrl_data = {
|
||||
.functions = aspeed_g6_functions,
|
||||
.nfunctions = ARRAY_SIZE(aspeed_g6_functions),
|
||||
},
|
||||
.configs = aspeed_g6_configs,
|
||||
.nconfigs = ARRAY_SIZE(aspeed_g6_configs),
|
||||
.confmaps = aspeed_g6_pin_config_map,
|
||||
.nconfmaps = ARRAY_SIZE(aspeed_g6_pin_config_map),
|
||||
};
|
||||
|
||||
static const struct pinmux_ops aspeed_g6_pinmux_ops = {
|
||||
@ -2331,12 +2707,21 @@ static const struct pinctrl_ops aspeed_g6_pinctrl_ops = {
|
||||
.dt_free_map = pinctrl_utils_free_map,
|
||||
};
|
||||
|
||||
static const struct pinconf_ops aspeed_g6_conf_ops = {
|
||||
.is_generic = true,
|
||||
.pin_config_get = aspeed_pin_config_get,
|
||||
.pin_config_set = aspeed_pin_config_set,
|
||||
.pin_config_group_get = aspeed_pin_config_group_get,
|
||||
.pin_config_group_set = aspeed_pin_config_group_set,
|
||||
};
|
||||
|
||||
static struct pinctrl_desc aspeed_g6_pinctrl_desc = {
|
||||
.name = "aspeed-g6-pinctrl",
|
||||
.pins = aspeed_g6_pins,
|
||||
.npins = ARRAY_SIZE(aspeed_g6_pins),
|
||||
.pctlops = &aspeed_g6_pinctrl_ops,
|
||||
.pmxops = &aspeed_g6_pinmux_ops,
|
||||
.confops = &aspeed_g6_conf_ops,
|
||||
};
|
||||
|
||||
static int aspeed_g6_pinctrl_probe(struct platform_device *pdev)
|
||||
|
@ -411,49 +411,21 @@ static inline const struct aspeed_pin_config *find_pinconf_config(
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Aspeed pin configuration description.
|
||||
*
|
||||
* @param: pinconf configuration parameter
|
||||
* @arg: The supported argument for @param, or -1 if any value is supported
|
||||
* @val: The register value to write to configure @arg for @param
|
||||
*
|
||||
* The map is to be used in conjunction with the configuration array supplied
|
||||
* by the driver implementation.
|
||||
*/
|
||||
struct aspeed_pin_config_map {
|
||||
enum pin_config_param param;
|
||||
s32 arg;
|
||||
u32 val;
|
||||
};
|
||||
|
||||
enum aspeed_pin_config_map_type { MAP_TYPE_ARG, MAP_TYPE_VAL };
|
||||
|
||||
/* Aspeed consistently both:
|
||||
*
|
||||
* 1. Defines "disable bits" for internal pull-downs
|
||||
* 2. Uses 8mA or 16mA drive strengths
|
||||
*/
|
||||
static const struct aspeed_pin_config_map pin_config_map[] = {
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, 0, 1 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, -1, 0 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, -1, 1 },
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, 8, 0 },
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, 16, 1 },
|
||||
};
|
||||
|
||||
static const struct aspeed_pin_config_map *find_pinconf_map(
|
||||
const struct aspeed_pinctrl_data *pdata,
|
||||
enum pin_config_param param,
|
||||
enum aspeed_pin_config_map_type type,
|
||||
s64 value)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pin_config_map); i++) {
|
||||
for (i = 0; i < pdata->nconfmaps; i++) {
|
||||
const struct aspeed_pin_config_map *elem;
|
||||
bool match;
|
||||
|
||||
elem = &pin_config_map[i];
|
||||
elem = &pdata->confmaps[i];
|
||||
|
||||
switch (type) {
|
||||
case MAP_TYPE_ARG:
|
||||
@ -491,8 +463,8 @@ int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset,
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
pmap = find_pinconf_map(param, MAP_TYPE_VAL,
|
||||
(val & BIT(pconf->bit)) >> pconf->bit);
|
||||
pmap = find_pinconf_map(pdata, param, MAP_TYPE_VAL,
|
||||
(val & pconf->mask) >> __ffs(pconf->mask));
|
||||
|
||||
if (!pmap)
|
||||
return -EINVAL;
|
||||
@ -535,22 +507,22 @@ int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset,
|
||||
if (!pconf)
|
||||
return -ENOTSUPP;
|
||||
|
||||
pmap = find_pinconf_map(param, MAP_TYPE_ARG, arg);
|
||||
pmap = find_pinconf_map(pdata, param, MAP_TYPE_ARG, arg);
|
||||
|
||||
if (WARN_ON(!pmap))
|
||||
return -EINVAL;
|
||||
|
||||
val = pmap->val << pconf->bit;
|
||||
val = pmap->val << __ffs(pconf->mask);
|
||||
|
||||
rc = regmap_update_bits(pdata->scu, pconf->reg,
|
||||
BIT(pconf->bit), val);
|
||||
pmap->mask, val);
|
||||
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
pr_debug("%s: Set SCU%02X[%d]=%d for param %d(=%d) on pin %d\n",
|
||||
__func__, pconf->reg, pconf->bit, pmap->val,
|
||||
param, arg, offset);
|
||||
pr_debug("%s: Set SCU%02X[%lu]=%d for param %d(=%d) on pin %d\n",
|
||||
__func__, pconf->reg, __ffs(pconf->mask),
|
||||
pmap->val, param, arg, offset);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
@ -24,8 +24,7 @@ struct aspeed_pin_config {
|
||||
enum pin_config_param param;
|
||||
unsigned int pins[2];
|
||||
unsigned int reg;
|
||||
u8 bit;
|
||||
u8 value;
|
||||
u32 mask;
|
||||
};
|
||||
|
||||
#define ASPEED_PINCTRL_PIN(name_) \
|
||||
@ -35,6 +34,38 @@ struct aspeed_pin_config {
|
||||
.drv_data = (void *) &(PIN_SYM(name_)) \
|
||||
}
|
||||
|
||||
#define ASPEED_SB_PINCONF(param_, pin0_, pin1_, reg_, bit_) { \
|
||||
.param = param_, \
|
||||
.pins = {pin0_, pin1_}, \
|
||||
.reg = reg_, \
|
||||
.mask = BIT_MASK(bit_) \
|
||||
}
|
||||
|
||||
#define ASPEED_PULL_DOWN_PINCONF(pin_, reg_, bit_) \
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, pin_, pin_, reg_, bit_), \
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_)
|
||||
|
||||
#define ASPEED_PULL_UP_PINCONF(pin_, reg_, bit_) \
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_UP, pin_, pin_, reg_, bit_), \
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_)
|
||||
/*
|
||||
* Aspeed pin configuration description.
|
||||
*
|
||||
* @param: pinconf configuration parameter
|
||||
* @arg: The supported argument for @param, or -1 if any value is supported
|
||||
* @val: The register value to write to configure @arg for @param
|
||||
* @mask: The bitfield mask for @val
|
||||
*
|
||||
* The map is to be used in conjunction with the configuration array supplied
|
||||
* by the driver implementation.
|
||||
*/
|
||||
struct aspeed_pin_config_map {
|
||||
enum pin_config_param param;
|
||||
s32 arg;
|
||||
u32 val;
|
||||
u32 mask;
|
||||
};
|
||||
|
||||
struct aspeed_pinctrl_data {
|
||||
struct regmap *scu;
|
||||
|
||||
@ -45,6 +76,9 @@ struct aspeed_pinctrl_data {
|
||||
const unsigned int nconfigs;
|
||||
|
||||
struct aspeed_pinmux_data pinmux;
|
||||
|
||||
const struct aspeed_pin_config_map *confmaps;
|
||||
const unsigned int nconfmaps;
|
||||
};
|
||||
|
||||
/* Aspeed pinctrl helpers */
|
||||
|
@ -737,6 +737,7 @@ struct aspeed_pin_desc {
|
||||
#define FUNC_DECL_(func, ...) \
|
||||
static const char *FUNC_SYM(func)[] = { __VA_ARGS__ }
|
||||
|
||||
#define FUNC_DECL_1(func, group) FUNC_DECL_(func, #group)
|
||||
#define FUNC_DECL_2(func, one, two) FUNC_DECL_(func, #one, #two)
|
||||
#define FUNC_DECL_3(func, one, two, three) FUNC_DECL_(func, #one, #two, #three)
|
||||
|
||||
|
@ -286,6 +286,12 @@ static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type)
|
||||
iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge);
|
||||
iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio,
|
||||
rising_or_high);
|
||||
|
||||
if (type & IRQ_TYPE_EDGE_BOTH)
|
||||
irq_set_handler_locked(d, handle_edge_irq);
|
||||
else
|
||||
irq_set_handler_locked(d, handle_level_irq);
|
||||
|
||||
raw_spin_unlock_irqrestore(&chip->lock, flags);
|
||||
|
||||
dev_dbg(chip->dev,
|
||||
@ -843,7 +849,7 @@ static int iproc_gpio_probe(struct platform_device *pdev)
|
||||
"gpio-ranges");
|
||||
|
||||
/* optional GPIO interrupt support */
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
irq = platform_get_irq_optional(pdev, 0);
|
||||
if (irq > 0) {
|
||||
struct irq_chip *irqc;
|
||||
struct gpio_irq_chip *girq;
|
||||
@ -868,7 +874,7 @@ static int iproc_gpio_probe(struct platform_device *pdev)
|
||||
return -ENOMEM;
|
||||
girq->parents[0] = irq;
|
||||
girq->default_type = IRQ_TYPE_NONE;
|
||||
girq->handler = handle_simple_irq;
|
||||
girq->handler = handle_bad_irq;
|
||||
}
|
||||
|
||||
ret = gpiochip_add_data(gc, chip);
|
||||
|
@ -560,7 +560,6 @@ static void __maybe_unused madera_pin_dbg_show(struct pinctrl_dev *pctldev,
|
||||
seq_puts(s, " SCHMITT");
|
||||
}
|
||||
|
||||
|
||||
static const struct pinctrl_ops madera_pin_group_ops = {
|
||||
.get_groups_count = madera_get_groups_count,
|
||||
.get_group_name = madera_get_group_name,
|
||||
|
@ -1376,8 +1376,15 @@ void devm_pinctrl_put(struct pinctrl *p)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(devm_pinctrl_put);
|
||||
|
||||
int pinctrl_register_map(const struct pinctrl_map *maps, unsigned num_maps,
|
||||
bool dup)
|
||||
/**
|
||||
* pinctrl_register_mappings() - register a set of pin controller mappings
|
||||
* @maps: the pincontrol mappings table to register. Note the pinctrl-core
|
||||
* keeps a reference to the passed in maps, so they should _not_ be
|
||||
* marked with __initdata.
|
||||
* @num_maps: the number of maps in the mapping table
|
||||
*/
|
||||
int pinctrl_register_mappings(const struct pinctrl_map *maps,
|
||||
unsigned num_maps)
|
||||
{
|
||||
int i, ret;
|
||||
struct pinctrl_maps *maps_node;
|
||||
@ -1430,17 +1437,8 @@ int pinctrl_register_map(const struct pinctrl_map *maps, unsigned num_maps,
|
||||
if (!maps_node)
|
||||
return -ENOMEM;
|
||||
|
||||
maps_node->maps = maps;
|
||||
maps_node->num_maps = num_maps;
|
||||
if (dup) {
|
||||
maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps,
|
||||
GFP_KERNEL);
|
||||
if (!maps_node->maps) {
|
||||
kfree(maps_node);
|
||||
return -ENOMEM;
|
||||
}
|
||||
} else {
|
||||
maps_node->maps = maps;
|
||||
}
|
||||
|
||||
mutex_lock(&pinctrl_maps_mutex);
|
||||
list_add_tail(&maps_node->node, &pinctrl_maps);
|
||||
@ -1448,22 +1446,14 @@ int pinctrl_register_map(const struct pinctrl_map *maps, unsigned num_maps,
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* pinctrl_register_mappings() - register a set of pin controller mappings
|
||||
* @maps: the pincontrol mappings table to register. This should probably be
|
||||
* marked with __initdata so it can be discarded after boot. This
|
||||
* function will perform a shallow copy for the mapping entries.
|
||||
* @num_maps: the number of maps in the mapping table
|
||||
*/
|
||||
int pinctrl_register_mappings(const struct pinctrl_map *maps,
|
||||
unsigned num_maps)
|
||||
{
|
||||
return pinctrl_register_map(maps, num_maps, true);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pinctrl_register_mappings);
|
||||
|
||||
void pinctrl_unregister_map(const struct pinctrl_map *map)
|
||||
/**
|
||||
* pinctrl_unregister_mappings() - unregister a set of pin controller mappings
|
||||
* @maps: the pincontrol mappings table passed to pinctrl_register_mappings()
|
||||
* when registering the mappings.
|
||||
*/
|
||||
void pinctrl_unregister_mappings(const struct pinctrl_map *map)
|
||||
{
|
||||
struct pinctrl_maps *maps_node;
|
||||
|
||||
@ -1478,6 +1468,7 @@ void pinctrl_unregister_map(const struct pinctrl_map *map)
|
||||
}
|
||||
mutex_unlock(&pinctrl_maps_mutex);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pinctrl_unregister_mappings);
|
||||
|
||||
/**
|
||||
* pinctrl_force_sleep() - turn a given controller device into sleep state
|
||||
|
@ -236,10 +236,6 @@ extern struct pinctrl_gpio_range *
|
||||
pinctrl_find_gpio_range_from_pin_nolock(struct pinctrl_dev *pctldev,
|
||||
unsigned int pin);
|
||||
|
||||
int pinctrl_register_map(const struct pinctrl_map *maps, unsigned num_maps,
|
||||
bool dup);
|
||||
void pinctrl_unregister_map(const struct pinctrl_map *map);
|
||||
|
||||
extern int pinctrl_force_sleep(struct pinctrl_dev *pctldev);
|
||||
extern int pinctrl_force_default(struct pinctrl_dev *pctldev);
|
||||
|
||||
|
@ -51,7 +51,7 @@ void pinctrl_dt_free_maps(struct pinctrl *p)
|
||||
struct pinctrl_dt_map *dt_map, *n1;
|
||||
|
||||
list_for_each_entry_safe(dt_map, n1, &p->dt_maps, node) {
|
||||
pinctrl_unregister_map(dt_map->map);
|
||||
pinctrl_unregister_mappings(dt_map->map);
|
||||
list_del(&dt_map->node);
|
||||
dt_free_map(dt_map->pctldev, dt_map->map,
|
||||
dt_map->num_maps);
|
||||
@ -92,7 +92,7 @@ static int dt_remember_or_free_map(struct pinctrl *p, const char *statename,
|
||||
dt_map->num_maps = num_maps;
|
||||
list_add_tail(&dt_map->node, &p->dt_maps);
|
||||
|
||||
return pinctrl_register_map(map, num_maps, false);
|
||||
return pinctrl_register_mappings(map, num_maps);
|
||||
|
||||
err_free_map:
|
||||
dt_free_map(pctldev, map, num_maps);
|
||||
|
@ -137,6 +137,13 @@ config PINCTRL_IMX8MN
|
||||
help
|
||||
Say Y here to enable the imx8mn pinctrl driver
|
||||
|
||||
config PINCTRL_IMX8MP
|
||||
bool "IMX8MP pinctrl driver"
|
||||
depends on ARCH_MXC && ARM64
|
||||
select PINCTRL_IMX
|
||||
help
|
||||
Say Y here to enable the imx8mp pinctrl driver
|
||||
|
||||
config PINCTRL_IMX8MQ
|
||||
bool "IMX8MQ pinctrl driver"
|
||||
depends on ARCH_MXC && ARM64
|
||||
|
@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
|
||||
obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
|
||||
obj-$(CONFIG_PINCTRL_IMX8MM) += pinctrl-imx8mm.o
|
||||
obj-$(CONFIG_PINCTRL_IMX8MN) += pinctrl-imx8mn.o
|
||||
obj-$(CONFIG_PINCTRL_IMX8MP) += pinctrl-imx8mp.o
|
||||
obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o
|
||||
obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o
|
||||
obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
|
||||
|
345
drivers/pinctrl/freescale/pinctrl-imx8mp.c
Normal file
345
drivers/pinctrl/freescale/pinctrl-imx8mp.c
Normal file
@ -0,0 +1,345 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "pinctrl-imx.h"
|
||||
|
||||
enum imx8mp_pads {
|
||||
MX8MP_IOMUXC_RESERVE0 = 0,
|
||||
MX8MP_IOMUXC_RESERVE1 = 1,
|
||||
MX8MP_IOMUXC_RESERVE2 = 2,
|
||||
MX8MP_IOMUXC_RESERVE3 = 3,
|
||||
MX8MP_IOMUXC_RESERVE4 = 4,
|
||||
MX8MP_IOMUXC_GPIO1_IO00 = 5,
|
||||
MX8MP_IOMUXC_GPIO1_IO01 = 6,
|
||||
MX8MP_IOMUXC_GPIO1_IO02 = 7,
|
||||
MX8MP_IOMUXC_GPIO1_IO03 = 8,
|
||||
MX8MP_IOMUXC_GPIO1_IO04 = 9,
|
||||
MX8MP_IOMUXC_GPIO1_IO05 = 10,
|
||||
MX8MP_IOMUXC_GPIO1_IO06 = 11,
|
||||
MX8MP_IOMUXC_GPIO1_IO07 = 12,
|
||||
MX8MP_IOMUXC_GPIO1_IO08 = 13,
|
||||
MX8MP_IOMUXC_GPIO1_IO09 = 14,
|
||||
MX8MP_IOMUXC_GPIO1_IO10 = 15,
|
||||
MX8MP_IOMUXC_GPIO1_IO11 = 16,
|
||||
MX8MP_IOMUXC_GPIO1_IO12 = 17,
|
||||
MX8MP_IOMUXC_GPIO1_IO13 = 18,
|
||||
MX8MP_IOMUXC_GPIO1_IO14 = 19,
|
||||
MX8MP_IOMUXC_GPIO1_IO15 = 20,
|
||||
MX8MP_IOMUXC_ENET_MDC = 21,
|
||||
MX8MP_IOMUXC_ENET_MDIO = 22,
|
||||
MX8MP_IOMUXC_ENET_TD3 = 23,
|
||||
MX8MP_IOMUXC_ENET_TD2 = 24,
|
||||
MX8MP_IOMUXC_ENET_TD1 = 25,
|
||||
MX8MP_IOMUXC_ENET_TD0 = 26,
|
||||
MX8MP_IOMUXC_ENET_TX_CTL = 27,
|
||||
MX8MP_IOMUXC_ENET_TXC = 28,
|
||||
MX8MP_IOMUXC_ENET_RX_CTL = 29,
|
||||
MX8MP_IOMUXC_ENET_RXC = 30,
|
||||
MX8MP_IOMUXC_ENET_RD0 = 31,
|
||||
MX8MP_IOMUXC_ENET_RD1 = 32,
|
||||
MX8MP_IOMUXC_ENET_RD2 = 33,
|
||||
MX8MP_IOMUXC_ENET_RD3 = 34,
|
||||
MX8MP_IOMUXC_SD1_CLK = 35,
|
||||
MX8MP_IOMUXC_SD1_CMD = 36,
|
||||
MX8MP_IOMUXC_SD1_DATA0 = 37,
|
||||
MX8MP_IOMUXC_SD1_DATA1 = 38,
|
||||
MX8MP_IOMUXC_SD1_DATA2 = 39,
|
||||
MX8MP_IOMUXC_SD1_DATA3 = 40,
|
||||
MX8MP_IOMUXC_SD1_DATA4 = 41,
|
||||
MX8MP_IOMUXC_SD1_DATA5 = 42,
|
||||
MX8MP_IOMUXC_SD1_DATA6 = 43,
|
||||
MX8MP_IOMUXC_SD1_DATA7 = 44,
|
||||
MX8MP_IOMUXC_SD1_RESET_B = 45,
|
||||
MX8MP_IOMUXC_SD1_STROBE = 46,
|
||||
MX8MP_IOMUXC_SD2_CD_B = 47,
|
||||
MX8MP_IOMUXC_SD2_CLK = 48,
|
||||
MX8MP_IOMUXC_SD2_CMD = 49,
|
||||
MX8MP_IOMUXC_SD2_DATA0 = 50,
|
||||
MX8MP_IOMUXC_SD2_DATA1 = 51,
|
||||
MX8MP_IOMUXC_SD2_DATA2 = 52,
|
||||
MX8MP_IOMUXC_SD2_DATA3 = 53,
|
||||
MX8MP_IOMUXC_SD2_RESET_B = 54,
|
||||
MX8MP_IOMUXC_SD2_WP = 55,
|
||||
MX8MP_IOMUXC_NAND_ALE = 56,
|
||||
MX8MP_IOMUXC_NAND_CE0_B = 57,
|
||||
MX8MP_IOMUXC_NAND_CE1_B = 58,
|
||||
MX8MP_IOMUXC_NAND_CE2_B = 59,
|
||||
MX8MP_IOMUXC_NAND_CE3_B = 60,
|
||||
MX8MP_IOMUXC_NAND_CLE = 61,
|
||||
MX8MP_IOMUXC_NAND_DATA00 = 62,
|
||||
MX8MP_IOMUXC_NAND_DATA01 = 63,
|
||||
MX8MP_IOMUXC_NAND_DATA02 = 64,
|
||||
MX8MP_IOMUXC_NAND_DATA03 = 65,
|
||||
MX8MP_IOMUXC_NAND_DATA04 = 66,
|
||||
MX8MP_IOMUXC_NAND_DATA05 = 67,
|
||||
MX8MP_IOMUXC_NAND_DATA06 = 68,
|
||||
MX8MP_IOMUXC_NAND_DATA07 = 69,
|
||||
MX8MP_IOMUXC_NAND_DQS = 70,
|
||||
MX8MP_IOMUXC_NAND_RE_B = 71,
|
||||
MX8MP_IOMUXC_NAND_READY_B = 72,
|
||||
MX8MP_IOMUXC_NAND_WE_B = 73,
|
||||
MX8MP_IOMUXC_NAND_WP_B = 74,
|
||||
MX8MP_IOMUXC_SAI5_RXFS = 75,
|
||||
MX8MP_IOMUXC_SAI5_RXC = 76,
|
||||
MX8MP_IOMUXC_SAI5_RXD0 = 77,
|
||||
MX8MP_IOMUXC_SAI5_RXD1 = 78,
|
||||
MX8MP_IOMUXC_SAI5_RXD2 = 79,
|
||||
MX8MP_IOMUXC_SAI5_RXD3 = 80,
|
||||
MX8MP_IOMUXC_SAI5_MCLK = 81,
|
||||
MX8MP_IOMUXC_SAI1_RXFS = 82,
|
||||
MX8MP_IOMUXC_SAI1_RXC = 83,
|
||||
MX8MP_IOMUXC_SAI1_RXD0 = 84,
|
||||
MX8MP_IOMUXC_SAI1_RXD1 = 85,
|
||||
MX8MP_IOMUXC_SAI1_RXD2 = 86,
|
||||
MX8MP_IOMUXC_SAI1_RXD3 = 87,
|
||||
MX8MP_IOMUXC_SAI1_RXD4 = 88,
|
||||
MX8MP_IOMUXC_SAI1_RXD5 = 89,
|
||||
MX8MP_IOMUXC_SAI1_RXD6 = 90,
|
||||
MX8MP_IOMUXC_SAI1_RXD7 = 91,
|
||||
MX8MP_IOMUXC_SAI1_TXFS = 92,
|
||||
MX8MP_IOMUXC_SAI1_TXC = 93,
|
||||
MX8MP_IOMUXC_SAI1_TXD0 = 94,
|
||||
MX8MP_IOMUXC_SAI1_TXD1 = 95,
|
||||
MX8MP_IOMUXC_SAI1_TXD2 = 96,
|
||||
MX8MP_IOMUXC_SAI1_TXD3 = 97,
|
||||
MX8MP_IOMUXC_SAI1_TXD4 = 98,
|
||||
MX8MP_IOMUXC_SAI1_TXD5 = 99,
|
||||
MX8MP_IOMUXC_SAI1_TXD6 = 100,
|
||||
MX8MP_IOMUXC_SAI1_TXD7 = 101,
|
||||
MX8MP_IOMUXC_SAI1_MCLK = 102,
|
||||
MX8MP_IOMUXC_SAI2_RXFS = 103,
|
||||
MX8MP_IOMUXC_SAI2_RXC = 104,
|
||||
MX8MP_IOMUXC_SAI2_RXD0 = 105,
|
||||
MX8MP_IOMUXC_SAI2_TXFS = 106,
|
||||
MX8MP_IOMUXC_SAI2_TXC = 107,
|
||||
MX8MP_IOMUXC_SAI2_TXD0 = 108,
|
||||
MX8MP_IOMUXC_SAI2_MCLK = 109,
|
||||
MX8MP_IOMUXC_SAI3_RXFS = 110,
|
||||
MX8MP_IOMUXC_SAI3_RXC = 111,
|
||||
MX8MP_IOMUXC_SAI3_RXD = 112,
|
||||
MX8MP_IOMUXC_SAI3_TXFS = 113,
|
||||
MX8MP_IOMUXC_SAI3_TXC = 114,
|
||||
MX8MP_IOMUXC_SAI3_TXD = 115,
|
||||
MX8MP_IOMUXC_SAI3_MCLK = 116,
|
||||
MX8MP_IOMUXC_SPDIF_TX = 117,
|
||||
MX8MP_IOMUXC_SPDIF_RX = 118,
|
||||
MX8MP_IOMUXC_SPDIF_EXT_CLK = 119,
|
||||
MX8MP_IOMUXC_ECSPI1_SCLK = 120,
|
||||
MX8MP_IOMUXC_ECSPI1_MOSI = 121,
|
||||
MX8MP_IOMUXC_ECSPI1_MISO = 122,
|
||||
MX8MP_IOMUXC_ECSPI1_SS0 = 123,
|
||||
MX8MP_IOMUXC_ECSPI2_SCLK = 124,
|
||||
MX8MP_IOMUXC_ECSPI2_MOSI = 125,
|
||||
MX8MP_IOMUXC_ECSPI2_MISO = 126,
|
||||
MX8MP_IOMUXC_ECSPI2_SS0 = 127,
|
||||
MX8MP_IOMUXC_I2C1_SCL = 128,
|
||||
MX8MP_IOMUXC_I2C1_SDA = 129,
|
||||
MX8MP_IOMUXC_I2C2_SCL = 130,
|
||||
MX8MP_IOMUXC_I2C2_SDA = 131,
|
||||
MX8MP_IOMUXC_I2C3_SCL = 132,
|
||||
MX8MP_IOMUXC_I2C3_SDA = 133,
|
||||
MX8MP_IOMUXC_I2C4_SCL = 134,
|
||||
MX8MP_IOMUXC_I2C4_SDA = 135,
|
||||
MX8MP_IOMUXC_UART1_RXD = 136,
|
||||
MX8MP_IOMUXC_UART1_TXD = 137,
|
||||
MX8MP_IOMUXC_UART2_RXD = 138,
|
||||
MX8MP_IOMUXC_UART2_TXD = 139,
|
||||
MX8MP_IOMUXC_UART3_RXD = 140,
|
||||
MX8MP_IOMUXC_UART3_TXD = 141,
|
||||
MX8MP_IOMUXC_UART4_RXD = 142,
|
||||
MX8MP_IOMUXC_UART4_TXD = 143,
|
||||
MX8MP_IOMUXC_HDMI_DDC_SCL = 144,
|
||||
MX8MP_IOMUXC_HDMI_DDC_SDA = 145,
|
||||
MX8MP_IOMUXC_HDMI_CEC = 146,
|
||||
MX8MP_IOMUXC_HDMI_HPD = 147,
|
||||
};
|
||||
|
||||
/* Pad names for the pinmux subsystem */
|
||||
static const struct pinctrl_pin_desc imx8mp_pinctrl_pads[] = {
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE0),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE1),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE2),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE3),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE4),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO00),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO01),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO02),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO03),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO04),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO05),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO06),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO07),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO08),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO09),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO10),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO11),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO12),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO13),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO14),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO15),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_MDC),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_MDIO),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD3),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD2),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD1),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD0),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TX_CTL),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TXC),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RX_CTL),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RXC),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD0),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD1),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD2),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD3),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_CLK),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_CMD),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA0),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA1),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA2),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA3),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA4),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA5),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA6),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA7),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_RESET_B),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_STROBE),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_CD_B),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_CLK),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_CMD),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA0),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA1),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA2),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA3),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_RESET_B),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_WP),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_ALE),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE0_B),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE1_B),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE2_B),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE3_B),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CLE),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA00),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA01),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA02),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA03),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA04),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA05),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA06),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA07),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DQS),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_RE_B),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_READY_B),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_WE_B),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_WP_B),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXFS),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXC),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD0),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD1),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD2),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD3),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_MCLK),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXFS),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXC),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD0),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD1),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD2),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD3),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD4),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD5),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD6),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD7),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXFS),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXC),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD0),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD1),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD2),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD3),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD4),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD5),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD6),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD7),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_MCLK),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_RXFS),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_RXC),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_RXD0),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_TXFS),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_TXC),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_TXD0),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_MCLK),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_RXFS),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_RXC),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_RXD),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_TXFS),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_TXC),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_TXD),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_MCLK),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SPDIF_TX),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SPDIF_RX),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SPDIF_EXT_CLK),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_SCLK),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_MOSI),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_MISO),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_SS0),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_SCLK),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_MOSI),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_MISO),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_SS0),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C1_SCL),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C1_SDA),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C2_SCL),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C2_SDA),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C3_SCL),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C3_SDA),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C4_SCL),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C4_SDA),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART1_RXD),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART1_TXD),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART2_RXD),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART2_TXD),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART3_RXD),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART3_TXD),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART4_RXD),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART4_TXD),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_DDC_SCL),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_DDC_SDA),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_CEC),
|
||||
IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_HPD),
|
||||
};
|
||||
|
||||
static const struct imx_pinctrl_soc_info imx8mp_pinctrl_info = {
|
||||
.pins = imx8mp_pinctrl_pads,
|
||||
.npins = ARRAY_SIZE(imx8mp_pinctrl_pads),
|
||||
.gpr_compatible = "fsl,imx8mp-iomuxc-gpr",
|
||||
};
|
||||
|
||||
static const struct of_device_id imx8mp_pinctrl_of_match[] = {
|
||||
{ .compatible = "fsl,imx8mp-iomuxc", .data = &imx8mp_pinctrl_info, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int imx8mp_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return imx_pinctrl_probe(pdev, &imx8mp_pinctrl_info);
|
||||
}
|
||||
|
||||
static struct platform_driver imx8mp_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "imx8mp-pinctrl",
|
||||
.of_match_table = of_match_ptr(imx8mp_pinctrl_of_match),
|
||||
},
|
||||
.probe = imx8mp_pinctrl_probe,
|
||||
};
|
||||
|
||||
static int __init imx8mp_pinctrl_init(void)
|
||||
{
|
||||
return platform_driver_register(&imx8mp_pinctrl_driver);
|
||||
}
|
||||
arch_initcall(imx8mp_pinctrl_init);
|
@ -31,6 +31,19 @@ config PINCTRL_CHERRYVIEW
|
||||
Cherryview/Braswell pinctrl driver provides an interface that
|
||||
allows configuring of SoC pins and using them as GPIOs.
|
||||
|
||||
config PINCTRL_LYNXPOINT
|
||||
tristate "Intel Lynxpoint pinctrl and GPIO driver"
|
||||
depends on ACPI
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
select GENERIC_PINCONF
|
||||
select GPIOLIB
|
||||
select GPIOLIB_IRQCHIP
|
||||
help
|
||||
Lynxpoint is the PCH of Intel Haswell. This pinctrl driver
|
||||
provides an interface that allows configuring of PCH pins and
|
||||
using them as GPIOs.
|
||||
|
||||
config PINCTRL_MERRIFIELD
|
||||
tristate "Intel Merrifield pinctrl driver"
|
||||
depends on X86_INTEL_MID
|
||||
|
@ -3,6 +3,7 @@
|
||||
|
||||
obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
|
||||
obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o
|
||||
obj-$(CONFIG_PINCTRL_LYNXPOINT) += pinctrl-lynxpoint.o
|
||||
obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o
|
||||
obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o
|
||||
obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o
|
||||
|
@ -93,7 +93,7 @@
|
||||
#define BYT_DEFAULT_GPIO_MUX 0
|
||||
#define BYT_ALTER_GPIO_MUX 1
|
||||
|
||||
struct byt_gpio_pin_context {
|
||||
struct intel_pad_context {
|
||||
u32 conf0;
|
||||
u32 val;
|
||||
};
|
||||
@ -105,16 +105,6 @@ struct byt_gpio_pin_context {
|
||||
.pad_map = (map),\
|
||||
}
|
||||
|
||||
struct byt_gpio {
|
||||
struct gpio_chip chip;
|
||||
struct platform_device *pdev;
|
||||
struct pinctrl_dev *pctl_dev;
|
||||
struct pinctrl_desc pctl_desc;
|
||||
const struct intel_pinctrl_soc_data *soc_data;
|
||||
struct intel_community *communities_copy;
|
||||
struct byt_gpio_pin_context *saved_context;
|
||||
};
|
||||
|
||||
/* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */
|
||||
static const struct pinctrl_pin_desc byt_score_pins[] = {
|
||||
PINCTRL_PIN(0, "SATA_GP0"),
|
||||
@ -550,14 +540,14 @@ static const struct intel_pinctrl_soc_data *byt_soc_data[] = {
|
||||
|
||||
static DEFINE_RAW_SPINLOCK(byt_lock);
|
||||
|
||||
static struct intel_community *byt_get_community(struct byt_gpio *vg,
|
||||
static struct intel_community *byt_get_community(struct intel_pinctrl *vg,
|
||||
unsigned int pin)
|
||||
{
|
||||
struct intel_community *comm;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < vg->soc_data->ncommunities; i++) {
|
||||
comm = vg->communities_copy + i;
|
||||
for (i = 0; i < vg->ncommunities; i++) {
|
||||
comm = vg->communities + i;
|
||||
if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
|
||||
return comm;
|
||||
}
|
||||
@ -565,7 +555,7 @@ static struct intel_community *byt_get_community(struct byt_gpio *vg,
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset,
|
||||
static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset,
|
||||
int reg)
|
||||
{
|
||||
struct intel_community *comm = byt_get_community(vg, offset);
|
||||
@ -592,17 +582,17 @@ static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset,
|
||||
|
||||
static int byt_get_groups_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return vg->soc_data->ngroups;
|
||||
return vg->soc->ngroups;
|
||||
}
|
||||
|
||||
static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
|
||||
unsigned int selector)
|
||||
{
|
||||
struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return vg->soc_data->groups[selector].name;
|
||||
return vg->soc->groups[selector].name;
|
||||
}
|
||||
|
||||
static int byt_get_group_pins(struct pinctrl_dev *pctldev,
|
||||
@ -610,10 +600,10 @@ static int byt_get_group_pins(struct pinctrl_dev *pctldev,
|
||||
const unsigned int **pins,
|
||||
unsigned int *num_pins)
|
||||
{
|
||||
struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
*pins = vg->soc_data->groups[selector].pins;
|
||||
*num_pins = vg->soc_data->groups[selector].npins;
|
||||
*pins = vg->soc->groups[selector].pins;
|
||||
*num_pins = vg->soc->groups[selector].npins;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -626,17 +616,17 @@ static const struct pinctrl_ops byt_pinctrl_ops = {
|
||||
|
||||
static int byt_get_functions_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return vg->soc_data->nfunctions;
|
||||
return vg->soc->nfunctions;
|
||||
}
|
||||
|
||||
static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
|
||||
unsigned int selector)
|
||||
{
|
||||
struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return vg->soc_data->functions[selector].name;
|
||||
return vg->soc->functions[selector].name;
|
||||
}
|
||||
|
||||
static int byt_get_function_groups(struct pinctrl_dev *pctldev,
|
||||
@ -644,15 +634,15 @@ static int byt_get_function_groups(struct pinctrl_dev *pctldev,
|
||||
const char * const **groups,
|
||||
unsigned int *num_groups)
|
||||
{
|
||||
struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
*groups = vg->soc_data->functions[selector].groups;
|
||||
*num_groups = vg->soc_data->functions[selector].ngroups;
|
||||
*groups = vg->soc->functions[selector].groups;
|
||||
*num_groups = vg->soc->functions[selector].ngroups;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void byt_set_group_simple_mux(struct byt_gpio *vg,
|
||||
static void byt_set_group_simple_mux(struct intel_pinctrl *vg,
|
||||
const struct intel_pingroup group,
|
||||
unsigned int func)
|
||||
{
|
||||
@ -667,7 +657,7 @@ static void byt_set_group_simple_mux(struct byt_gpio *vg,
|
||||
|
||||
padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
|
||||
if (!padcfg0) {
|
||||
dev_warn(&vg->pdev->dev,
|
||||
dev_warn(vg->dev,
|
||||
"Group %s, pin %i not muxed (no padcfg0)\n",
|
||||
group.name, i);
|
||||
continue;
|
||||
@ -682,7 +672,7 @@ static void byt_set_group_simple_mux(struct byt_gpio *vg,
|
||||
raw_spin_unlock_irqrestore(&byt_lock, flags);
|
||||
}
|
||||
|
||||
static void byt_set_group_mixed_mux(struct byt_gpio *vg,
|
||||
static void byt_set_group_mixed_mux(struct intel_pinctrl *vg,
|
||||
const struct intel_pingroup group,
|
||||
const unsigned int *func)
|
||||
{
|
||||
@ -697,7 +687,7 @@ static void byt_set_group_mixed_mux(struct byt_gpio *vg,
|
||||
|
||||
padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
|
||||
if (!padcfg0) {
|
||||
dev_warn(&vg->pdev->dev,
|
||||
dev_warn(vg->dev,
|
||||
"Group %s, pin %i not muxed (no padcfg0)\n",
|
||||
group.name, i);
|
||||
continue;
|
||||
@ -715,9 +705,9 @@ static void byt_set_group_mixed_mux(struct byt_gpio *vg,
|
||||
static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
|
||||
unsigned int group_selector)
|
||||
{
|
||||
struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
|
||||
const struct intel_function func = vg->soc_data->functions[func_selector];
|
||||
const struct intel_pingroup group = vg->soc_data->groups[group_selector];
|
||||
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
|
||||
const struct intel_function func = vg->soc->functions[func_selector];
|
||||
const struct intel_pingroup group = vg->soc->groups[group_selector];
|
||||
|
||||
if (group.modes)
|
||||
byt_set_group_mixed_mux(vg, group, group.modes);
|
||||
@ -729,22 +719,22 @@ static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned int offset)
|
||||
static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset)
|
||||
{
|
||||
/* SCORE pin 92-93 */
|
||||
if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) &&
|
||||
if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) &&
|
||||
offset >= 92 && offset <= 93)
|
||||
return BYT_ALTER_GPIO_MUX;
|
||||
|
||||
/* SUS pin 11-21 */
|
||||
if (!strcmp(vg->soc_data->uid, BYT_SUS_ACPI_UID) &&
|
||||
if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) &&
|
||||
offset >= 11 && offset <= 21)
|
||||
return BYT_ALTER_GPIO_MUX;
|
||||
|
||||
return BYT_DEFAULT_GPIO_MUX;
|
||||
}
|
||||
|
||||
static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset)
|
||||
static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset)
|
||||
{
|
||||
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
|
||||
unsigned long flags;
|
||||
@ -752,7 +742,13 @@ static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset)
|
||||
|
||||
raw_spin_lock_irqsave(&byt_lock, flags);
|
||||
value = readl(reg);
|
||||
value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
|
||||
|
||||
/* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */
|
||||
if (value & BYT_DIRECT_IRQ_EN)
|
||||
/* nothing to do */ ;
|
||||
else
|
||||
value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
|
||||
|
||||
writel(value, reg);
|
||||
raw_spin_unlock_irqrestore(&byt_lock, flags);
|
||||
}
|
||||
@ -761,7 +757,7 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
|
||||
struct pinctrl_gpio_range *range,
|
||||
unsigned int offset)
|
||||
{
|
||||
struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
|
||||
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
|
||||
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
|
||||
u32 value, gpio_mux;
|
||||
unsigned long flags;
|
||||
@ -784,13 +780,12 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
|
||||
value |= gpio_mux;
|
||||
writel(value, reg);
|
||||
|
||||
dev_warn(&vg->pdev->dev, FW_BUG
|
||||
"pin %u forcibly re-configured as GPIO\n", offset);
|
||||
dev_warn(vg->dev, FW_BUG "pin %u forcibly re-configured as GPIO\n", offset);
|
||||
}
|
||||
|
||||
raw_spin_unlock_irqrestore(&byt_lock, flags);
|
||||
|
||||
pm_runtime_get(&vg->pdev->dev);
|
||||
pm_runtime_get(vg->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -799,10 +794,10 @@ static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
|
||||
struct pinctrl_gpio_range *range,
|
||||
unsigned int offset)
|
||||
{
|
||||
struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
|
||||
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
|
||||
|
||||
byt_gpio_clear_triggering(vg, offset);
|
||||
pm_runtime_put(&vg->pdev->dev);
|
||||
pm_runtime_put(vg->dev);
|
||||
}
|
||||
|
||||
static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
|
||||
@ -810,7 +805,7 @@ static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
|
||||
unsigned int offset,
|
||||
bool input)
|
||||
{
|
||||
struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
|
||||
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
|
||||
void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
|
||||
void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
|
||||
unsigned long flags;
|
||||
@ -822,15 +817,15 @@ static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
|
||||
value &= ~BYT_DIR_MASK;
|
||||
if (input)
|
||||
value |= BYT_OUTPUT_EN;
|
||||
else
|
||||
else if (readl(conf_reg) & BYT_DIRECT_IRQ_EN)
|
||||
/*
|
||||
* Before making any direction modifications, do a check if gpio
|
||||
* is set for direct IRQ. On baytrail, setting GPIO to output
|
||||
* does not make sense, so let's at least warn the caller before
|
||||
* does not make sense, so let's at least inform the caller before
|
||||
* they shoot themselves in the foot.
|
||||
*/
|
||||
WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
|
||||
"Potential Error: Setting GPIO with direct_irq_en to output");
|
||||
dev_info_once(vg->dev, "Potential Error: Setting GPIO with direct_irq_en to output");
|
||||
|
||||
writel(value, val_reg);
|
||||
|
||||
raw_spin_unlock_irqrestore(&byt_lock, flags);
|
||||
@ -893,7 +888,7 @@ static int byt_set_pull_strength(u32 *reg, u16 strength)
|
||||
static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
|
||||
unsigned long *config)
|
||||
{
|
||||
struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
|
||||
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
|
||||
enum pin_config_param param = pinconf_to_config_param(*config);
|
||||
void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
|
||||
void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
|
||||
@ -978,7 +973,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
|
||||
unsigned long *configs,
|
||||
unsigned int num_configs)
|
||||
{
|
||||
struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
|
||||
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
|
||||
unsigned int param, arg;
|
||||
void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
|
||||
void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
|
||||
@ -1012,7 +1007,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
|
||||
if (val & BYT_INPUT_EN) {
|
||||
val &= ~BYT_INPUT_EN;
|
||||
writel(val, val_reg);
|
||||
dev_warn(&vg->pdev->dev,
|
||||
dev_warn(vg->dev,
|
||||
"pin %u forcibly set to input mode\n",
|
||||
offset);
|
||||
}
|
||||
@ -1034,7 +1029,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
|
||||
if (val & BYT_INPUT_EN) {
|
||||
val &= ~BYT_INPUT_EN;
|
||||
writel(val, val_reg);
|
||||
dev_warn(&vg->pdev->dev,
|
||||
dev_warn(vg->dev,
|
||||
"pin %u forcibly set to input mode\n",
|
||||
offset);
|
||||
}
|
||||
@ -1115,7 +1110,7 @@ static const struct pinctrl_desc byt_pinctrl_desc = {
|
||||
|
||||
static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
|
||||
{
|
||||
struct byt_gpio *vg = gpiochip_get_data(chip);
|
||||
struct intel_pinctrl *vg = gpiochip_get_data(chip);
|
||||
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
@ -1129,7 +1124,7 @@ static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
|
||||
|
||||
static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
|
||||
{
|
||||
struct byt_gpio *vg = gpiochip_get_data(chip);
|
||||
struct intel_pinctrl *vg = gpiochip_get_data(chip);
|
||||
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
|
||||
unsigned long flags;
|
||||
u32 old_val;
|
||||
@ -1148,7 +1143,7 @@ static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
|
||||
|
||||
static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
|
||||
{
|
||||
struct byt_gpio *vg = gpiochip_get_data(chip);
|
||||
struct intel_pinctrl *vg = gpiochip_get_data(chip);
|
||||
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
|
||||
unsigned long flags;
|
||||
u32 value;
|
||||
@ -1161,9 +1156,9 @@ static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
|
||||
raw_spin_unlock_irqrestore(&byt_lock, flags);
|
||||
|
||||
if (!(value & BYT_OUTPUT_EN))
|
||||
return 0;
|
||||
return GPIO_LINE_DIRECTION_OUT;
|
||||
if (!(value & BYT_INPUT_EN))
|
||||
return 1;
|
||||
return GPIO_LINE_DIRECTION_IN;
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
@ -1188,11 +1183,11 @@ static int byt_gpio_direction_output(struct gpio_chip *chip,
|
||||
|
||||
static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
|
||||
{
|
||||
struct byt_gpio *vg = gpiochip_get_data(chip);
|
||||
struct intel_pinctrl *vg = gpiochip_get_data(chip);
|
||||
int i;
|
||||
u32 conf0, val;
|
||||
|
||||
for (i = 0; i < vg->soc_data->npins; i++) {
|
||||
for (i = 0; i < vg->soc->npins; i++) {
|
||||
const struct intel_community *comm;
|
||||
const char *pull_str = NULL;
|
||||
const char *pull = NULL;
|
||||
@ -1202,7 +1197,7 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
|
||||
unsigned int pin;
|
||||
|
||||
raw_spin_lock_irqsave(&byt_lock, flags);
|
||||
pin = vg->soc_data->pins[i].number;
|
||||
pin = vg->soc->pins[i].number;
|
||||
reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
|
||||
if (!reg) {
|
||||
seq_printf(s,
|
||||
@ -1297,7 +1292,7 @@ static const struct gpio_chip byt_gpio_chip = {
|
||||
static void byt_irq_ack(struct irq_data *d)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct byt_gpio *vg = gpiochip_get_data(gc);
|
||||
struct intel_pinctrl *vg = gpiochip_get_data(gc);
|
||||
unsigned int offset = irqd_to_hwirq(d);
|
||||
void __iomem *reg;
|
||||
|
||||
@ -1313,7 +1308,7 @@ static void byt_irq_ack(struct irq_data *d)
|
||||
static void byt_irq_mask(struct irq_data *d)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct byt_gpio *vg = gpiochip_get_data(gc);
|
||||
struct intel_pinctrl *vg = gpiochip_get_data(gc);
|
||||
|
||||
byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
|
||||
}
|
||||
@ -1321,7 +1316,7 @@ static void byt_irq_mask(struct irq_data *d)
|
||||
static void byt_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct byt_gpio *vg = gpiochip_get_data(gc);
|
||||
struct intel_pinctrl *vg = gpiochip_get_data(gc);
|
||||
unsigned int offset = irqd_to_hwirq(d);
|
||||
unsigned long flags;
|
||||
void __iomem *reg;
|
||||
@ -1359,7 +1354,7 @@ static void byt_irq_unmask(struct irq_data *d)
|
||||
|
||||
static int byt_irq_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
|
||||
struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
|
||||
u32 offset = irqd_to_hwirq(d);
|
||||
u32 value;
|
||||
unsigned long flags;
|
||||
@ -1395,20 +1390,10 @@ static int byt_irq_type(struct irq_data *d, unsigned int type)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_chip byt_irqchip = {
|
||||
.name = "BYT-GPIO",
|
||||
.irq_ack = byt_irq_ack,
|
||||
.irq_mask = byt_irq_mask,
|
||||
.irq_unmask = byt_irq_unmask,
|
||||
.irq_set_type = byt_irq_type,
|
||||
.flags = IRQCHIP_SKIP_SET_WAKE,
|
||||
};
|
||||
|
||||
static void byt_gpio_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
struct irq_data *data = irq_desc_get_irq_data(desc);
|
||||
struct byt_gpio *vg = gpiochip_get_data(
|
||||
irq_desc_get_handler_data(desc));
|
||||
struct intel_pinctrl *vg = gpiochip_get_data(irq_desc_get_handler_data(desc));
|
||||
struct irq_chip *chip = irq_data_get_irq_chip(data);
|
||||
u32 base, pin;
|
||||
void __iomem *reg;
|
||||
@ -1420,7 +1405,7 @@ static void byt_gpio_irq_handler(struct irq_desc *desc)
|
||||
reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
|
||||
|
||||
if (!reg) {
|
||||
dev_warn(&vg->pdev->dev,
|
||||
dev_warn(vg->dev,
|
||||
"Pin %i: could not retrieve interrupt status register\n",
|
||||
base);
|
||||
continue;
|
||||
@ -1441,22 +1426,9 @@ static void byt_init_irq_valid_mask(struct gpio_chip *chip,
|
||||
unsigned long *valid_mask,
|
||||
unsigned int ngpios)
|
||||
{
|
||||
/*
|
||||
* FIXME: currently the valid_mask is filled in as part of
|
||||
* initializing the irq_chip below in byt_gpio_irq_init_hw().
|
||||
* when converting this driver to the new way of passing the
|
||||
* gpio_irq_chip along when adding the gpio_chip, move the
|
||||
* mask initialization into this callback instead. Right now
|
||||
* this callback is here to make sure the mask gets allocated.
|
||||
*/
|
||||
}
|
||||
|
||||
static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
|
||||
{
|
||||
struct byt_gpio *vg = gpiochip_get_data(chip);
|
||||
struct device *dev = &vg->pdev->dev;
|
||||
struct intel_pinctrl *vg = gpiochip_get_data(chip);
|
||||
void __iomem *reg;
|
||||
u32 base, value;
|
||||
u32 value;
|
||||
int i;
|
||||
|
||||
/*
|
||||
@ -1464,12 +1436,12 @@ static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
|
||||
* do not use direct IRQ mode. This will prevent spurious
|
||||
* interrupts from misconfigured pins.
|
||||
*/
|
||||
for (i = 0; i < vg->soc_data->npins; i++) {
|
||||
unsigned int pin = vg->soc_data->pins[i].number;
|
||||
for (i = 0; i < vg->soc->npins; i++) {
|
||||
unsigned int pin = vg->soc->pins[i].number;
|
||||
|
||||
reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
|
||||
if (!reg) {
|
||||
dev_warn(&vg->pdev->dev,
|
||||
dev_warn(vg->dev,
|
||||
"Pin %i: could not retrieve conf0 register\n",
|
||||
i);
|
||||
continue;
|
||||
@ -1477,20 +1449,27 @@ static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
|
||||
|
||||
value = readl(reg);
|
||||
if (value & BYT_DIRECT_IRQ_EN) {
|
||||
clear_bit(i, chip->irq.valid_mask);
|
||||
dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i);
|
||||
clear_bit(i, valid_mask);
|
||||
dev_dbg(vg->dev, "excluding GPIO %d from IRQ domain\n", i);
|
||||
} else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
|
||||
byt_gpio_clear_triggering(vg, i);
|
||||
dev_dbg(dev, "disabling GPIO %d\n", i);
|
||||
dev_dbg(vg->dev, "disabling GPIO %d\n", i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
|
||||
{
|
||||
struct intel_pinctrl *vg = gpiochip_get_data(chip);
|
||||
void __iomem *reg;
|
||||
u32 base, value;
|
||||
|
||||
/* clear interrupt status trigger registers */
|
||||
for (base = 0; base < vg->soc_data->npins; base += 32) {
|
||||
for (base = 0; base < vg->soc->npins; base += 32) {
|
||||
reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
|
||||
|
||||
if (!reg) {
|
||||
dev_warn(&vg->pdev->dev,
|
||||
dev_warn(vg->dev,
|
||||
"Pin %i: could not retrieve irq status reg\n",
|
||||
base);
|
||||
continue;
|
||||
@ -1501,7 +1480,7 @@ static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
|
||||
might be misconfigured in bios */
|
||||
value = readl(reg);
|
||||
if (value)
|
||||
dev_err(&vg->pdev->dev,
|
||||
dev_err(vg->dev,
|
||||
"GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n",
|
||||
base / 32, value);
|
||||
}
|
||||
@ -1511,19 +1490,20 @@ static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
|
||||
|
||||
static int byt_gpio_add_pin_ranges(struct gpio_chip *chip)
|
||||
{
|
||||
struct byt_gpio *vg = gpiochip_get_data(chip);
|
||||
struct device *dev = &vg->pdev->dev;
|
||||
struct intel_pinctrl *vg = gpiochip_get_data(chip);
|
||||
struct device *dev = vg->dev;
|
||||
int ret;
|
||||
|
||||
ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc_data->npins);
|
||||
ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins);
|
||||
if (ret)
|
||||
dev_err(dev, "failed to add GPIO pin range\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int byt_gpio_probe(struct byt_gpio *vg)
|
||||
static int byt_gpio_probe(struct intel_pinctrl *vg)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(vg->dev);
|
||||
struct gpio_chip *gc;
|
||||
struct resource *irq_rc;
|
||||
int ret;
|
||||
@ -1531,32 +1511,39 @@ static int byt_gpio_probe(struct byt_gpio *vg)
|
||||
/* Set up gpio chip */
|
||||
vg->chip = byt_gpio_chip;
|
||||
gc = &vg->chip;
|
||||
gc->label = dev_name(&vg->pdev->dev);
|
||||
gc->label = dev_name(vg->dev);
|
||||
gc->base = -1;
|
||||
gc->can_sleep = false;
|
||||
gc->add_pin_ranges = byt_gpio_add_pin_ranges;
|
||||
gc->parent = &vg->pdev->dev;
|
||||
gc->ngpio = vg->soc_data->npins;
|
||||
gc->irq.init_valid_mask = byt_init_irq_valid_mask;
|
||||
gc->parent = vg->dev;
|
||||
gc->ngpio = vg->soc->npins;
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,
|
||||
sizeof(*vg->saved_context), GFP_KERNEL);
|
||||
if (!vg->saved_context)
|
||||
vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads),
|
||||
GFP_KERNEL);
|
||||
if (!vg->context.pads)
|
||||
return -ENOMEM;
|
||||
#endif
|
||||
|
||||
/* set up interrupts */
|
||||
irq_rc = platform_get_resource(vg->pdev, IORESOURCE_IRQ, 0);
|
||||
irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (irq_rc && irq_rc->start) {
|
||||
struct gpio_irq_chip *girq;
|
||||
|
||||
vg->irqchip.name = "BYT-GPIO",
|
||||
vg->irqchip.irq_ack = byt_irq_ack,
|
||||
vg->irqchip.irq_mask = byt_irq_mask,
|
||||
vg->irqchip.irq_unmask = byt_irq_unmask,
|
||||
vg->irqchip.irq_set_type = byt_irq_type,
|
||||
vg->irqchip.flags = IRQCHIP_SKIP_SET_WAKE,
|
||||
|
||||
girq = &gc->irq;
|
||||
girq->chip = &byt_irqchip;
|
||||
girq->chip = &vg->irqchip;
|
||||
girq->init_hw = byt_gpio_irq_init_hw;
|
||||
girq->init_valid_mask = byt_init_irq_valid_mask;
|
||||
girq->parent_handler = byt_gpio_irq_handler;
|
||||
girq->num_parents = 1;
|
||||
girq->parents = devm_kcalloc(&vg->pdev->dev, girq->num_parents,
|
||||
girq->parents = devm_kcalloc(vg->dev, girq->num_parents,
|
||||
sizeof(*girq->parents), GFP_KERNEL);
|
||||
if (!girq->parents)
|
||||
return -ENOMEM;
|
||||
@ -1565,34 +1552,35 @@ static int byt_gpio_probe(struct byt_gpio *vg)
|
||||
girq->handler = handle_bad_irq;
|
||||
}
|
||||
|
||||
ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg);
|
||||
ret = devm_gpiochip_add_data(vg->dev, gc, vg);
|
||||
if (ret) {
|
||||
dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n");
|
||||
dev_err(vg->dev, "failed adding byt-gpio chip\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int byt_set_soc_data(struct byt_gpio *vg,
|
||||
const struct intel_pinctrl_soc_data *soc_data)
|
||||
static int byt_set_soc_data(struct intel_pinctrl *vg,
|
||||
const struct intel_pinctrl_soc_data *soc)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(vg->dev);
|
||||
int i;
|
||||
|
||||
vg->soc_data = soc_data;
|
||||
vg->communities_copy = devm_kcalloc(&vg->pdev->dev,
|
||||
soc_data->ncommunities,
|
||||
sizeof(*vg->communities_copy),
|
||||
GFP_KERNEL);
|
||||
if (!vg->communities_copy)
|
||||
vg->soc = soc;
|
||||
|
||||
vg->ncommunities = vg->soc->ncommunities;
|
||||
vg->communities = devm_kcalloc(vg->dev, vg->ncommunities,
|
||||
sizeof(*vg->communities), GFP_KERNEL);
|
||||
if (!vg->communities)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < soc_data->ncommunities; i++) {
|
||||
struct intel_community *comm = vg->communities_copy + i;
|
||||
for (i = 0; i < vg->soc->ncommunities; i++) {
|
||||
struct intel_community *comm = vg->communities + i;
|
||||
|
||||
*comm = vg->soc_data->communities[i];
|
||||
*comm = vg->soc->communities[i];
|
||||
|
||||
comm->pad_regs = devm_platform_ioremap_resource(vg->pdev, 0);
|
||||
comm->pad_regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(comm->pad_regs))
|
||||
return PTR_ERR(comm->pad_regs);
|
||||
}
|
||||
@ -1610,15 +1598,16 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct intel_pinctrl_soc_data *soc_data = NULL;
|
||||
const struct intel_pinctrl_soc_data **soc_table;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct acpi_device *acpi_dev;
|
||||
struct byt_gpio *vg;
|
||||
struct intel_pinctrl *vg;
|
||||
int i, ret;
|
||||
|
||||
acpi_dev = ACPI_COMPANION(&pdev->dev);
|
||||
acpi_dev = ACPI_COMPANION(dev);
|
||||
if (!acpi_dev)
|
||||
return -ENODEV;
|
||||
|
||||
soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(&pdev->dev);
|
||||
soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(dev);
|
||||
|
||||
for (i = 0; soc_table[i]; i++) {
|
||||
if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {
|
||||
@ -1630,26 +1619,26 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
|
||||
if (!soc_data)
|
||||
return -ENODEV;
|
||||
|
||||
vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL);
|
||||
vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL);
|
||||
if (!vg)
|
||||
return -ENOMEM;
|
||||
|
||||
vg->pdev = pdev;
|
||||
vg->dev = dev;
|
||||
ret = byt_set_soc_data(vg, soc_data);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to set soc data\n");
|
||||
dev_err(dev, "failed to set soc data\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
vg->pctl_desc = byt_pinctrl_desc;
|
||||
vg->pctl_desc.name = dev_name(&pdev->dev);
|
||||
vg->pctl_desc.pins = vg->soc_data->pins;
|
||||
vg->pctl_desc.npins = vg->soc_data->npins;
|
||||
vg->pctldesc = byt_pinctrl_desc;
|
||||
vg->pctldesc.name = dev_name(dev);
|
||||
vg->pctldesc.pins = vg->soc->pins;
|
||||
vg->pctldesc.npins = vg->soc->npins;
|
||||
|
||||
vg->pctl_dev = devm_pinctrl_register(&pdev->dev, &vg->pctl_desc, vg);
|
||||
if (IS_ERR(vg->pctl_dev)) {
|
||||
dev_err(&pdev->dev, "failed to register pinctrl driver\n");
|
||||
return PTR_ERR(vg->pctl_dev);
|
||||
vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg);
|
||||
if (IS_ERR(vg->pctldev)) {
|
||||
dev_err(dev, "failed to register pinctrl driver\n");
|
||||
return PTR_ERR(vg->pctldev);
|
||||
}
|
||||
|
||||
ret = byt_gpio_probe(vg);
|
||||
@ -1657,7 +1646,7 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
|
||||
return ret;
|
||||
|
||||
platform_set_drvdata(pdev, vg);
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
pm_runtime_enable(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1665,30 +1654,30 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int byt_gpio_suspend(struct device *dev)
|
||||
{
|
||||
struct byt_gpio *vg = dev_get_drvdata(dev);
|
||||
struct intel_pinctrl *vg = dev_get_drvdata(dev);
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
raw_spin_lock_irqsave(&byt_lock, flags);
|
||||
|
||||
for (i = 0; i < vg->soc_data->npins; i++) {
|
||||
for (i = 0; i < vg->soc->npins; i++) {
|
||||
void __iomem *reg;
|
||||
u32 value;
|
||||
unsigned int pin = vg->soc_data->pins[i].number;
|
||||
unsigned int pin = vg->soc->pins[i].number;
|
||||
|
||||
reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
|
||||
if (!reg) {
|
||||
dev_warn(&vg->pdev->dev,
|
||||
dev_warn(vg->dev,
|
||||
"Pin %i: could not retrieve conf0 register\n",
|
||||
i);
|
||||
continue;
|
||||
}
|
||||
value = readl(reg) & BYT_CONF0_RESTORE_MASK;
|
||||
vg->saved_context[i].conf0 = value;
|
||||
vg->context.pads[i].conf0 = value;
|
||||
|
||||
reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
|
||||
value = readl(reg) & BYT_VAL_RESTORE_MASK;
|
||||
vg->saved_context[i].val = value;
|
||||
vg->context.pads[i].val = value;
|
||||
}
|
||||
|
||||
raw_spin_unlock_irqrestore(&byt_lock, flags);
|
||||
@ -1697,29 +1686,29 @@ static int byt_gpio_suspend(struct device *dev)
|
||||
|
||||
static int byt_gpio_resume(struct device *dev)
|
||||
{
|
||||
struct byt_gpio *vg = dev_get_drvdata(dev);
|
||||
struct intel_pinctrl *vg = dev_get_drvdata(dev);
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
raw_spin_lock_irqsave(&byt_lock, flags);
|
||||
|
||||
for (i = 0; i < vg->soc_data->npins; i++) {
|
||||
for (i = 0; i < vg->soc->npins; i++) {
|
||||
void __iomem *reg;
|
||||
u32 value;
|
||||
unsigned int pin = vg->soc_data->pins[i].number;
|
||||
unsigned int pin = vg->soc->pins[i].number;
|
||||
|
||||
reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
|
||||
if (!reg) {
|
||||
dev_warn(&vg->pdev->dev,
|
||||
dev_warn(vg->dev,
|
||||
"Pin %i: could not retrieve conf0 register\n",
|
||||
i);
|
||||
continue;
|
||||
}
|
||||
value = readl(reg);
|
||||
if ((value & BYT_CONF0_RESTORE_MASK) !=
|
||||
vg->saved_context[i].conf0) {
|
||||
vg->context.pads[i].conf0) {
|
||||
value &= ~BYT_CONF0_RESTORE_MASK;
|
||||
value |= vg->saved_context[i].conf0;
|
||||
value |= vg->context.pads[i].conf0;
|
||||
writel(value, reg);
|
||||
dev_info(dev, "restored pin %d conf0 %#08x", i, value);
|
||||
}
|
||||
@ -1727,11 +1716,11 @@ static int byt_gpio_resume(struct device *dev)
|
||||
reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
|
||||
value = readl(reg);
|
||||
if ((value & BYT_VAL_RESTORE_MASK) !=
|
||||
vg->saved_context[i].val) {
|
||||
vg->context.pads[i].val) {
|
||||
u32 v;
|
||||
|
||||
v = value & ~BYT_VAL_RESTORE_MASK;
|
||||
v |= vg->saved_context[i].val;
|
||||
v |= vg->context.pads[i].val;
|
||||
if (v != value) {
|
||||
writel(v, reg);
|
||||
dev_dbg(dev, "restored pin %d val %#08x\n",
|
||||
|
@ -1289,7 +1289,10 @@ static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
|
||||
direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
|
||||
direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
|
||||
|
||||
return direction != CHV_PADCTRL0_GPIOCFG_GPO;
|
||||
if (direction == CHV_PADCTRL0_GPIOCFG_GPO)
|
||||
return GPIO_LINE_DIRECTION_OUT;
|
||||
|
||||
return GPIO_LINE_DIRECTION_IN;
|
||||
}
|
||||
|
||||
static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
|
||||
|
@ -8,8 +8,8 @@
|
||||
*/
|
||||
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/gpio/driver.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/log2.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
@ -85,39 +85,6 @@ struct intel_community_context {
|
||||
u32 *hostown;
|
||||
};
|
||||
|
||||
struct intel_pinctrl_context {
|
||||
struct intel_pad_context *pads;
|
||||
struct intel_community_context *communities;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct intel_pinctrl - Intel pinctrl private structure
|
||||
* @dev: Pointer to the device structure
|
||||
* @lock: Lock to serialize register access
|
||||
* @pctldesc: Pin controller description
|
||||
* @pctldev: Pointer to the pin controller device
|
||||
* @chip: GPIO chip in this pin controller
|
||||
* @irqchip: IRQ chip in this pin controller
|
||||
* @soc: SoC/PCH specific pin configuration data
|
||||
* @communities: All communities in this pin controller
|
||||
* @ncommunities: Number of communities in this pin controller
|
||||
* @context: Configuration saved over system sleep
|
||||
* @irq: pinctrl/GPIO chip irq number
|
||||
*/
|
||||
struct intel_pinctrl {
|
||||
struct device *dev;
|
||||
raw_spinlock_t lock;
|
||||
struct pinctrl_desc pctldesc;
|
||||
struct pinctrl_dev *pctldev;
|
||||
struct gpio_chip chip;
|
||||
struct irq_chip irqchip;
|
||||
const struct intel_pinctrl_soc_data *soc;
|
||||
struct intel_community *communities;
|
||||
size_t ncommunities;
|
||||
struct intel_pinctrl_context context;
|
||||
int irq;
|
||||
};
|
||||
|
||||
#define pin_to_padno(c, p) ((p) - (c)->pin_base)
|
||||
#define padgroup_offset(g, p) ((p) - (g)->base)
|
||||
|
||||
@ -944,7 +911,10 @@ static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
|
||||
if (padcfg0 & PADCFG0_PMODE_MASK)
|
||||
return -EINVAL;
|
||||
|
||||
return !!(padcfg0 & PADCFG0_GPIOTXDIS);
|
||||
if (padcfg0 & PADCFG0_GPIOTXDIS)
|
||||
return GPIO_LINE_DIRECTION_IN;
|
||||
|
||||
return GPIO_LINE_DIRECTION_OUT;
|
||||
}
|
||||
|
||||
static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
|
||||
@ -1160,8 +1130,8 @@ static irqreturn_t intel_gpio_irq(int irq, void *data)
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
|
||||
const struct intel_community *community)
|
||||
static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl,
|
||||
const struct intel_community *community)
|
||||
{
|
||||
int ret = 0, i;
|
||||
|
||||
@ -1181,6 +1151,24 @@ static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
|
||||
{
|
||||
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
|
||||
int ret, i;
|
||||
|
||||
for (i = 0; i < pctrl->ncommunities; i++) {
|
||||
struct intel_community *community = &pctrl->communities[i];
|
||||
|
||||
ret = intel_gpio_add_community_ranges(pctrl, community);
|
||||
if (ret) {
|
||||
dev_err(pctrl->dev, "failed to add GPIO pin range\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
|
||||
{
|
||||
const struct intel_community *community;
|
||||
@ -1205,7 +1193,8 @@ static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
|
||||
|
||||
static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
|
||||
{
|
||||
int ret, i;
|
||||
int ret;
|
||||
struct gpio_irq_chip *girq;
|
||||
|
||||
pctrl->chip = intel_gpio_chip;
|
||||
|
||||
@ -1214,6 +1203,7 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
|
||||
pctrl->chip.label = dev_name(pctrl->dev);
|
||||
pctrl->chip.parent = pctrl->dev;
|
||||
pctrl->chip.base = -1;
|
||||
pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges;
|
||||
pctrl->irq = irq;
|
||||
|
||||
/* Setup IRQ chip */
|
||||
@ -1225,26 +1215,9 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
|
||||
pctrl->irqchip.irq_set_wake = intel_gpio_irq_wake;
|
||||
pctrl->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND;
|
||||
|
||||
ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
|
||||
if (ret) {
|
||||
dev_err(pctrl->dev, "failed to register gpiochip\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
for (i = 0; i < pctrl->ncommunities; i++) {
|
||||
struct intel_community *community = &pctrl->communities[i];
|
||||
|
||||
ret = intel_gpio_add_pin_ranges(pctrl, community);
|
||||
if (ret) {
|
||||
dev_err(pctrl->dev, "failed to add GPIO pin range\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* We need to request the interrupt here (instead of providing chip
|
||||
* to the irq directly) because on some platforms several GPIO
|
||||
* controllers share the same interrupt line.
|
||||
* On some platforms several GPIO controllers share the same interrupt
|
||||
* line.
|
||||
*/
|
||||
ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
|
||||
IRQF_SHARED | IRQF_NO_THREAD,
|
||||
@ -1254,14 +1227,20 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = gpiochip_irqchip_add(&pctrl->chip, &pctrl->irqchip, 0,
|
||||
handle_bad_irq, IRQ_TYPE_NONE);
|
||||
girq = &pctrl->chip.irq;
|
||||
girq->chip = &pctrl->irqchip;
|
||||
/* This will let us handle the IRQ in the driver */
|
||||
girq->parent_handler = NULL;
|
||||
girq->num_parents = 0;
|
||||
girq->default_type = IRQ_TYPE_NONE;
|
||||
girq->handler = handle_bad_irq;
|
||||
|
||||
ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
|
||||
if (ret) {
|
||||
dev_err(pctrl->dev, "failed to add irqchip\n");
|
||||
dev_err(pctrl->dev, "failed to register gpiochip\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
gpiochip_set_chained_irqchip(&pctrl->chip, &pctrl->irqchip, irq, NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -10,7 +10,10 @@
|
||||
#ifndef PINCTRL_INTEL_H
|
||||
#define PINCTRL_INTEL_H
|
||||
|
||||
#include <linux/gpio/driver.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/spinlock_types.h>
|
||||
|
||||
struct pinctrl_pin_desc;
|
||||
struct platform_device;
|
||||
@ -174,6 +177,47 @@ struct intel_pinctrl_soc_data {
|
||||
size_t ncommunities;
|
||||
};
|
||||
|
||||
struct intel_pad_context;
|
||||
struct intel_community_context;
|
||||
|
||||
/**
|
||||
* struct intel_pinctrl_context - context to be saved during suspend-resume
|
||||
* @pads: Opaque context per pad (driver dependent)
|
||||
* @communities: Opaque context per community (driver dependent)
|
||||
*/
|
||||
struct intel_pinctrl_context {
|
||||
struct intel_pad_context *pads;
|
||||
struct intel_community_context *communities;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct intel_pinctrl - Intel pinctrl private structure
|
||||
* @dev: Pointer to the device structure
|
||||
* @lock: Lock to serialize register access
|
||||
* @pctldesc: Pin controller description
|
||||
* @pctldev: Pointer to the pin controller device
|
||||
* @chip: GPIO chip in this pin controller
|
||||
* @irqchip: IRQ chip in this pin controller
|
||||
* @soc: SoC/PCH specific pin configuration data
|
||||
* @communities: All communities in this pin controller
|
||||
* @ncommunities: Number of communities in this pin controller
|
||||
* @context: Configuration saved over system sleep
|
||||
* @irq: pinctrl/GPIO chip irq number
|
||||
*/
|
||||
struct intel_pinctrl {
|
||||
struct device *dev;
|
||||
raw_spinlock_t lock;
|
||||
struct pinctrl_desc pctldesc;
|
||||
struct pinctrl_dev *pctldev;
|
||||
struct gpio_chip chip;
|
||||
struct irq_chip irqchip;
|
||||
const struct intel_pinctrl_soc_data *soc;
|
||||
struct intel_community *communities;
|
||||
size_t ncommunities;
|
||||
struct intel_pinctrl_context context;
|
||||
int irq;
|
||||
};
|
||||
|
||||
int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
|
||||
int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
|
||||
|
||||
|
975
drivers/pinctrl/intel/pinctrl-lynxpoint.c
Normal file
975
drivers/pinctrl/intel/pinctrl-lynxpoint.c
Normal file
@ -0,0 +1,975 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Intel Lynxpoint PCH pinctrl/GPIO driver
|
||||
*
|
||||
* Copyright (c) 2012, 2019, Intel Corporation
|
||||
* Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
|
||||
* Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
||||
*/
|
||||
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/gpio/driver.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/pinctrl/pinmux.h>
|
||||
#include <linux/pinctrl/pinconf.h>
|
||||
#include <linux/pinctrl/pinconf-generic.h>
|
||||
|
||||
#include "pinctrl-intel.h"
|
||||
|
||||
#define COMMUNITY(p, n) \
|
||||
{ \
|
||||
.pin_base = (p), \
|
||||
.npins = (n), \
|
||||
}
|
||||
|
||||
static const struct pinctrl_pin_desc lptlp_pins[] = {
|
||||
PINCTRL_PIN(0, "GP0_UART1_RXD"),
|
||||
PINCTRL_PIN(1, "GP1_UART1_TXD"),
|
||||
PINCTRL_PIN(2, "GP2_UART1_RTSB"),
|
||||
PINCTRL_PIN(3, "GP3_UART1_CTSB"),
|
||||
PINCTRL_PIN(4, "GP4_I2C0_SDA"),
|
||||
PINCTRL_PIN(5, "GP5_I2C0_SCL"),
|
||||
PINCTRL_PIN(6, "GP6_I2C1_SDA"),
|
||||
PINCTRL_PIN(7, "GP7_I2C1_SCL"),
|
||||
PINCTRL_PIN(8, "GP8"),
|
||||
PINCTRL_PIN(9, "GP9"),
|
||||
PINCTRL_PIN(10, "GP10"),
|
||||
PINCTRL_PIN(11, "GP11_SMBALERTB"),
|
||||
PINCTRL_PIN(12, "GP12_LANPHYPC"),
|
||||
PINCTRL_PIN(13, "GP13"),
|
||||
PINCTRL_PIN(14, "GP14"),
|
||||
PINCTRL_PIN(15, "GP15"),
|
||||
PINCTRL_PIN(16, "GP16_MGPIO9"),
|
||||
PINCTRL_PIN(17, "GP17_MGPIO10"),
|
||||
PINCTRL_PIN(18, "GP18_SRC0CLKRQB"),
|
||||
PINCTRL_PIN(19, "GP19_SRC1CLKRQB"),
|
||||
PINCTRL_PIN(20, "GP20_SRC2CLKRQB"),
|
||||
PINCTRL_PIN(21, "GP21_SRC3CLKRQB"),
|
||||
PINCTRL_PIN(22, "GP22_SRC4CLKRQB_TRST2"),
|
||||
PINCTRL_PIN(23, "GP23_SRC5CLKRQB_TDI2"),
|
||||
PINCTRL_PIN(24, "GP24_MGPIO0"),
|
||||
PINCTRL_PIN(25, "GP25_USBWAKEOUTB"),
|
||||
PINCTRL_PIN(26, "GP26_MGPIO5"),
|
||||
PINCTRL_PIN(27, "GP27_MGPIO6"),
|
||||
PINCTRL_PIN(28, "GP28_MGPIO7"),
|
||||
PINCTRL_PIN(29, "GP29_SLP_WLANB_MGPIO3"),
|
||||
PINCTRL_PIN(30, "GP30_SUSWARNB_SUSPWRDNACK_MGPIO1"),
|
||||
PINCTRL_PIN(31, "GP31_ACPRESENT_MGPIO2"),
|
||||
PINCTRL_PIN(32, "GP32_CLKRUNB"),
|
||||
PINCTRL_PIN(33, "GP33_DEVSLP0"),
|
||||
PINCTRL_PIN(34, "GP34_SATA0XPCIE6L3B_SATA0GP"),
|
||||
PINCTRL_PIN(35, "GP35_SATA1XPCIE6L2B_SATA1GP"),
|
||||
PINCTRL_PIN(36, "GP36_SATA2XPCIE6L1B_SATA2GP"),
|
||||
PINCTRL_PIN(37, "GP37_SATA3XPCIE6L0B_SATA3GP"),
|
||||
PINCTRL_PIN(38, "GP38_DEVSLP1"),
|
||||
PINCTRL_PIN(39, "GP39_DEVSLP2"),
|
||||
PINCTRL_PIN(40, "GP40_OC0B"),
|
||||
PINCTRL_PIN(41, "GP41_OC1B"),
|
||||
PINCTRL_PIN(42, "GP42_OC2B"),
|
||||
PINCTRL_PIN(43, "GP43_OC3B"),
|
||||
PINCTRL_PIN(44, "GP44"),
|
||||
PINCTRL_PIN(45, "GP45_TMS2"),
|
||||
PINCTRL_PIN(46, "GP46_TDO2"),
|
||||
PINCTRL_PIN(47, "GP47"),
|
||||
PINCTRL_PIN(48, "GP48"),
|
||||
PINCTRL_PIN(49, "GP49"),
|
||||
PINCTRL_PIN(50, "GP50"),
|
||||
PINCTRL_PIN(51, "GP51_GSXDOUT"),
|
||||
PINCTRL_PIN(52, "GP52_GSXSLOAD"),
|
||||
PINCTRL_PIN(53, "GP53_GSXDIN"),
|
||||
PINCTRL_PIN(54, "GP54_GSXSRESETB"),
|
||||
PINCTRL_PIN(55, "GP55_GSXCLK"),
|
||||
PINCTRL_PIN(56, "GP56"),
|
||||
PINCTRL_PIN(57, "GP57"),
|
||||
PINCTRL_PIN(58, "GP58"),
|
||||
PINCTRL_PIN(59, "GP59"),
|
||||
PINCTRL_PIN(60, "GP60_SML0ALERTB_MGPIO4"),
|
||||
PINCTRL_PIN(61, "GP61_SUS_STATB"),
|
||||
PINCTRL_PIN(62, "GP62_SUSCLK"),
|
||||
PINCTRL_PIN(63, "GP63_SLP_S5B"),
|
||||
PINCTRL_PIN(64, "GP64_SDIO_CLK"),
|
||||
PINCTRL_PIN(65, "GP65_SDIO_CMD"),
|
||||
PINCTRL_PIN(66, "GP66_SDIO_D0"),
|
||||
PINCTRL_PIN(67, "GP67_SDIO_D1"),
|
||||
PINCTRL_PIN(68, "GP68_SDIO_D2"),
|
||||
PINCTRL_PIN(69, "GP69_SDIO_D3"),
|
||||
PINCTRL_PIN(70, "GP70_SDIO_POWER_EN"),
|
||||
PINCTRL_PIN(71, "GP71_MPHYPC"),
|
||||
PINCTRL_PIN(72, "GP72_BATLOWB"),
|
||||
PINCTRL_PIN(73, "GP73_SML1ALERTB_PCHHOTB_MGPIO8"),
|
||||
PINCTRL_PIN(74, "GP74_SML1DATA_MGPIO12"),
|
||||
PINCTRL_PIN(75, "GP75_SML1CLK_MGPIO11"),
|
||||
PINCTRL_PIN(76, "GP76_BMBUSYB"),
|
||||
PINCTRL_PIN(77, "GP77_PIRQAB"),
|
||||
PINCTRL_PIN(78, "GP78_PIRQBB"),
|
||||
PINCTRL_PIN(79, "GP79_PIRQCB"),
|
||||
PINCTRL_PIN(80, "GP80_PIRQDB"),
|
||||
PINCTRL_PIN(81, "GP81_SPKR"),
|
||||
PINCTRL_PIN(82, "GP82_RCINB"),
|
||||
PINCTRL_PIN(83, "GP83_GSPI0_CSB"),
|
||||
PINCTRL_PIN(84, "GP84_GSPI0_CLK"),
|
||||
PINCTRL_PIN(85, "GP85_GSPI0_MISO"),
|
||||
PINCTRL_PIN(86, "GP86_GSPI0_MOSI"),
|
||||
PINCTRL_PIN(87, "GP87_GSPI1_CSB"),
|
||||
PINCTRL_PIN(88, "GP88_GSPI1_CLK"),
|
||||
PINCTRL_PIN(89, "GP89_GSPI1_MISO"),
|
||||
PINCTRL_PIN(90, "GP90_GSPI1_MOSI"),
|
||||
PINCTRL_PIN(91, "GP91_UART0_RXD"),
|
||||
PINCTRL_PIN(92, "GP92_UART0_TXD"),
|
||||
PINCTRL_PIN(93, "GP93_UART0_RTSB"),
|
||||
PINCTRL_PIN(94, "GP94_UART0_CTSB"),
|
||||
};
|
||||
|
||||
static const struct intel_community lptlp_communities[] = {
|
||||
COMMUNITY(0, 95),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data lptlp_soc_data = {
|
||||
.pins = lptlp_pins,
|
||||
.npins = ARRAY_SIZE(lptlp_pins),
|
||||
.communities = lptlp_communities,
|
||||
.ncommunities = ARRAY_SIZE(lptlp_communities),
|
||||
};
|
||||
|
||||
/* LynxPoint chipset has support for 95 GPIO pins */
|
||||
|
||||
#define LP_NUM_GPIO 95
|
||||
|
||||
/* Bitmapped register offsets */
|
||||
#define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */
|
||||
#define LP_IRQ2IOXAPIC 0x10 /* Bitmap, set by bios, 1: pin routed to IOxAPIC */
|
||||
#define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */
|
||||
#define LP_INT_STAT 0x80
|
||||
#define LP_INT_ENABLE 0x90
|
||||
|
||||
/* Each pin has two 32 bit config registers, starting at 0x100 */
|
||||
#define LP_CONFIG1 0x100
|
||||
#define LP_CONFIG2 0x104
|
||||
|
||||
/* LP_CONFIG1 reg bits */
|
||||
#define OUT_LVL_BIT BIT(31)
|
||||
#define IN_LVL_BIT BIT(30)
|
||||
#define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */
|
||||
#define INT_INV_BIT BIT(3) /* Invert interrupt triggering */
|
||||
#define DIR_BIT BIT(2) /* 0: Output, 1: Input */
|
||||
#define USE_SEL_MASK GENMASK(1, 0) /* 0: Native, 1: GPIO, ... */
|
||||
#define USE_SEL_NATIVE (0 << 0)
|
||||
#define USE_SEL_GPIO (1 << 0)
|
||||
|
||||
/* LP_CONFIG2 reg bits */
|
||||
#define GPINDIS_BIT BIT(2) /* disable input sensing */
|
||||
#define GPIWP_MASK GENMASK(1, 0) /* weak pull options */
|
||||
#define GPIWP_NONE 0 /* none */
|
||||
#define GPIWP_DOWN 1 /* weak pull down */
|
||||
#define GPIWP_UP 2 /* weak pull up */
|
||||
|
||||
/*
|
||||
* Lynxpoint gpios are controlled through both bitmapped registers and
|
||||
* per gpio specific registers. The bitmapped registers are in chunks of
|
||||
* 3 x 32bit registers to cover all 95 GPIOs
|
||||
*
|
||||
* per gpio specific registers consist of two 32bit registers per gpio
|
||||
* (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of
|
||||
* 190 config registers.
|
||||
*
|
||||
* A simplified view of the register layout look like this:
|
||||
*
|
||||
* LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers)
|
||||
* LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63
|
||||
* LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94
|
||||
* ...
|
||||
* LP_INT_ENABLE[31:0] ...
|
||||
* LP_INT_ENABLE[63:32] ...
|
||||
* LP_INT_ENABLE[94:64] ...
|
||||
* LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers)
|
||||
* LP0_CONFIG2 (gpio 0) config2 reg for gpio 0
|
||||
* LP1_CONFIG1 (gpio 1) config1 reg for gpio 1
|
||||
* LP1_CONFIG2 (gpio 1) config2 reg for gpio 1
|
||||
* LP2_CONFIG1 (gpio 2) ...
|
||||
* LP2_CONFIG2 (gpio 2) ...
|
||||
* ...
|
||||
* LP94_CONFIG1 (gpio 94) ...
|
||||
* LP94_CONFIG2 (gpio 94) ...
|
||||
*
|
||||
* IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55.
|
||||
*/
|
||||
|
||||
static struct intel_community *lp_get_community(struct intel_pinctrl *lg,
|
||||
unsigned int pin)
|
||||
{
|
||||
struct intel_community *comm;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < lg->ncommunities; i++) {
|
||||
comm = &lg->communities[i];
|
||||
if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
|
||||
return comm;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset,
|
||||
int reg)
|
||||
{
|
||||
struct intel_pinctrl *lg = gpiochip_get_data(chip);
|
||||
struct intel_community *comm;
|
||||
int reg_offset;
|
||||
|
||||
comm = lp_get_community(lg, offset);
|
||||
if (!comm)
|
||||
return NULL;
|
||||
|
||||
offset -= comm->pin_base;
|
||||
|
||||
if (reg == LP_CONFIG1 || reg == LP_CONFIG2)
|
||||
/* per gpio specific config registers */
|
||||
reg_offset = offset * 8;
|
||||
else
|
||||
/* bitmapped registers */
|
||||
reg_offset = (offset / 32) * 4;
|
||||
|
||||
return comm->regs + reg_offset + reg;
|
||||
}
|
||||
|
||||
static bool lp_gpio_acpi_use(struct intel_pinctrl *lg, unsigned int pin)
|
||||
{
|
||||
void __iomem *acpi_use;
|
||||
|
||||
acpi_use = lp_gpio_reg(&lg->chip, pin, LP_ACPI_OWNED);
|
||||
if (!acpi_use)
|
||||
return true;
|
||||
|
||||
return !(ioread32(acpi_use) & BIT(pin % 32));
|
||||
}
|
||||
|
||||
static bool lp_gpio_ioxapic_use(struct gpio_chip *chip, unsigned int offset)
|
||||
{
|
||||
void __iomem *ioxapic_use = lp_gpio_reg(chip, offset, LP_IRQ2IOXAPIC);
|
||||
u32 value;
|
||||
|
||||
value = ioread32(ioxapic_use);
|
||||
|
||||
if (offset >= 8 && offset <= 10)
|
||||
return !!(value & BIT(offset - 8 + 0));
|
||||
if (offset >= 13 && offset <= 14)
|
||||
return !!(value & BIT(offset - 13 + 3));
|
||||
if (offset >= 45 && offset <= 55)
|
||||
return !!(value & BIT(offset - 45 + 5));
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int lp_get_groups_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return lg->soc->ngroups;
|
||||
}
|
||||
|
||||
static const char *lp_get_group_name(struct pinctrl_dev *pctldev,
|
||||
unsigned int selector)
|
||||
{
|
||||
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return lg->soc->groups[selector].name;
|
||||
}
|
||||
|
||||
static int lp_get_group_pins(struct pinctrl_dev *pctldev,
|
||||
unsigned int selector,
|
||||
const unsigned int **pins,
|
||||
unsigned int *num_pins)
|
||||
{
|
||||
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
*pins = lg->soc->groups[selector].pins;
|
||||
*num_pins = lg->soc->groups[selector].npins;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void lp_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
|
||||
unsigned int pin)
|
||||
{
|
||||
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
|
||||
void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
|
||||
void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
|
||||
u32 value, mode;
|
||||
|
||||
value = ioread32(reg);
|
||||
|
||||
mode = value & USE_SEL_MASK;
|
||||
if (mode == USE_SEL_GPIO)
|
||||
seq_puts(s, "GPIO ");
|
||||
else
|
||||
seq_printf(s, "mode %d ", mode);
|
||||
|
||||
seq_printf(s, "0x%08x 0x%08x", value, ioread32(conf2));
|
||||
|
||||
if (lp_gpio_acpi_use(lg, pin))
|
||||
seq_puts(s, " [ACPI]");
|
||||
}
|
||||
|
||||
static const struct pinctrl_ops lptlp_pinctrl_ops = {
|
||||
.get_groups_count = lp_get_groups_count,
|
||||
.get_group_name = lp_get_group_name,
|
||||
.get_group_pins = lp_get_group_pins,
|
||||
.pin_dbg_show = lp_pin_dbg_show,
|
||||
};
|
||||
|
||||
static int lp_get_functions_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return lg->soc->nfunctions;
|
||||
}
|
||||
|
||||
static const char *lp_get_function_name(struct pinctrl_dev *pctldev,
|
||||
unsigned int selector)
|
||||
{
|
||||
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return lg->soc->functions[selector].name;
|
||||
}
|
||||
|
||||
static int lp_get_function_groups(struct pinctrl_dev *pctldev,
|
||||
unsigned int selector,
|
||||
const char * const **groups,
|
||||
unsigned int *num_groups)
|
||||
{
|
||||
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
*groups = lg->soc->functions[selector].groups;
|
||||
*num_groups = lg->soc->functions[selector].ngroups;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev,
|
||||
unsigned int function, unsigned int group)
|
||||
{
|
||||
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
|
||||
const struct intel_pingroup *grp = &lg->soc->groups[group];
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
raw_spin_lock_irqsave(&lg->lock, flags);
|
||||
|
||||
/* Now enable the mux setting for each pin in the group */
|
||||
for (i = 0; i < grp->npins; i++) {
|
||||
void __iomem *reg = lp_gpio_reg(&lg->chip, grp->pins[i], LP_CONFIG1);
|
||||
u32 value;
|
||||
|
||||
value = ioread32(reg);
|
||||
|
||||
value &= ~USE_SEL_MASK;
|
||||
if (grp->modes)
|
||||
value |= grp->modes[i];
|
||||
else
|
||||
value |= grp->mode;
|
||||
|
||||
iowrite32(value, reg);
|
||||
}
|
||||
|
||||
raw_spin_unlock_irqrestore(&lg->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lp_gpio_request_enable(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_gpio_range *range,
|
||||
unsigned int pin)
|
||||
{
|
||||
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
|
||||
void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
|
||||
void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
|
||||
unsigned long flags;
|
||||
u32 value;
|
||||
|
||||
pm_runtime_get(lg->dev);
|
||||
|
||||
raw_spin_lock_irqsave(&lg->lock, flags);
|
||||
|
||||
/*
|
||||
* Reconfigure pin to GPIO mode if needed and issue a warning,
|
||||
* since we expect firmware to configure it properly.
|
||||
*/
|
||||
value = ioread32(reg);
|
||||
if ((value & USE_SEL_MASK) != USE_SEL_GPIO) {
|
||||
iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg);
|
||||
dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", pin);
|
||||
}
|
||||
|
||||
/* Enable input sensing */
|
||||
iowrite32(ioread32(conf2) & ~GPINDIS_BIT, conf2);
|
||||
|
||||
raw_spin_unlock_irqrestore(&lg->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void lp_gpio_disable_free(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_gpio_range *range,
|
||||
unsigned int pin)
|
||||
{
|
||||
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
|
||||
void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
|
||||
unsigned long flags;
|
||||
|
||||
raw_spin_lock_irqsave(&lg->lock, flags);
|
||||
|
||||
/* Disable input sensing */
|
||||
iowrite32(ioread32(conf2) | GPINDIS_BIT, conf2);
|
||||
|
||||
raw_spin_unlock_irqrestore(&lg->lock, flags);
|
||||
|
||||
pm_runtime_put(lg->dev);
|
||||
}
|
||||
|
||||
static int lp_gpio_set_direction(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_gpio_range *range,
|
||||
unsigned int pin, bool input)
|
||||
{
|
||||
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
|
||||
void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
|
||||
unsigned long flags;
|
||||
u32 value;
|
||||
|
||||
raw_spin_lock_irqsave(&lg->lock, flags);
|
||||
|
||||
value = ioread32(reg);
|
||||
value &= ~DIR_BIT;
|
||||
if (input) {
|
||||
value |= DIR_BIT;
|
||||
} else {
|
||||
/*
|
||||
* Before making any direction modifications, do a check if GPIO
|
||||
* is set for direct IRQ. On Lynxpoint, setting GPIO to output
|
||||
* does not make sense, so let's at least warn the caller before
|
||||
* they shoot themselves in the foot.
|
||||
*/
|
||||
WARN(lp_gpio_ioxapic_use(&lg->chip, pin),
|
||||
"Potential Error: Setting GPIO to output with IOxAPIC redirection");
|
||||
}
|
||||
iowrite32(value, reg);
|
||||
|
||||
raw_spin_unlock_irqrestore(&lg->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct pinmux_ops lptlp_pinmux_ops = {
|
||||
.get_functions_count = lp_get_functions_count,
|
||||
.get_function_name = lp_get_function_name,
|
||||
.get_function_groups = lp_get_function_groups,
|
||||
.set_mux = lp_pinmux_set_mux,
|
||||
.gpio_request_enable = lp_gpio_request_enable,
|
||||
.gpio_disable_free = lp_gpio_disable_free,
|
||||
.gpio_set_direction = lp_gpio_set_direction,
|
||||
};
|
||||
|
||||
static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
unsigned long *config)
|
||||
{
|
||||
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
|
||||
void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
|
||||
enum pin_config_param param = pinconf_to_config_param(*config);
|
||||
unsigned long flags;
|
||||
u32 value, pull;
|
||||
u16 arg = 0;
|
||||
|
||||
raw_spin_lock_irqsave(&lg->lock, flags);
|
||||
value = ioread32(conf2);
|
||||
raw_spin_unlock_irqrestore(&lg->lock, flags);
|
||||
|
||||
pull = value & GPIWP_MASK;
|
||||
|
||||
switch (param) {
|
||||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
if (pull)
|
||||
return -EINVAL;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
if (pull != GPIWP_DOWN)
|
||||
return -EINVAL;
|
||||
|
||||
arg = 1;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
if (pull != GPIWP_UP)
|
||||
return -EINVAL;
|
||||
|
||||
arg = 1;
|
||||
break;
|
||||
default:
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
*config = pinconf_to_config_packed(param, arg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
unsigned long *configs, unsigned int num_configs)
|
||||
{
|
||||
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
|
||||
void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
|
||||
enum pin_config_param param;
|
||||
unsigned long flags;
|
||||
int i, ret = 0;
|
||||
u32 value;
|
||||
|
||||
raw_spin_lock_irqsave(&lg->lock, flags);
|
||||
|
||||
value = ioread32(conf2);
|
||||
|
||||
for (i = 0; i < num_configs; i++) {
|
||||
param = pinconf_to_config_param(configs[i]);
|
||||
|
||||
switch (param) {
|
||||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
value &= ~GPIWP_MASK;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
value &= ~GPIWP_MASK;
|
||||
value |= GPIWP_DOWN;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
value &= ~GPIWP_MASK;
|
||||
value |= GPIWP_UP;
|
||||
break;
|
||||
default:
|
||||
ret = -ENOTSUPP;
|
||||
}
|
||||
|
||||
if (ret)
|
||||
break;
|
||||
}
|
||||
|
||||
if (!ret)
|
||||
iowrite32(value, conf2);
|
||||
|
||||
raw_spin_unlock_irqrestore(&lg->lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct pinconf_ops lptlp_pinconf_ops = {
|
||||
.is_generic = true,
|
||||
.pin_config_get = lp_pin_config_get,
|
||||
.pin_config_set = lp_pin_config_set,
|
||||
};
|
||||
|
||||
static const struct pinctrl_desc lptlp_pinctrl_desc = {
|
||||
.pctlops = &lptlp_pinctrl_ops,
|
||||
.pmxops = &lptlp_pinmux_ops,
|
||||
.confops = &lptlp_pinconf_ops,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static int lp_gpio_get(struct gpio_chip *chip, unsigned int offset)
|
||||
{
|
||||
void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
|
||||
return !!(ioread32(reg) & IN_LVL_BIT);
|
||||
}
|
||||
|
||||
static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
|
||||
{
|
||||
struct intel_pinctrl *lg = gpiochip_get_data(chip);
|
||||
void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
|
||||
unsigned long flags;
|
||||
|
||||
raw_spin_lock_irqsave(&lg->lock, flags);
|
||||
|
||||
if (value)
|
||||
iowrite32(ioread32(reg) | OUT_LVL_BIT, reg);
|
||||
else
|
||||
iowrite32(ioread32(reg) & ~OUT_LVL_BIT, reg);
|
||||
|
||||
raw_spin_unlock_irqrestore(&lg->lock, flags);
|
||||
}
|
||||
|
||||
static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
|
||||
{
|
||||
return pinctrl_gpio_direction_input(chip->base + offset);
|
||||
}
|
||||
|
||||
static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
lp_gpio_set(chip, offset, value);
|
||||
|
||||
return pinctrl_gpio_direction_output(chip->base + offset);
|
||||
}
|
||||
|
||||
static int lp_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
|
||||
{
|
||||
void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
|
||||
|
||||
if (ioread32(reg) & DIR_BIT)
|
||||
return GPIO_LINE_DIRECTION_IN;
|
||||
|
||||
return GPIO_LINE_DIRECTION_OUT;
|
||||
}
|
||||
|
||||
static void lp_gpio_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
struct irq_data *data = irq_desc_get_irq_data(desc);
|
||||
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
|
||||
struct intel_pinctrl *lg = gpiochip_get_data(gc);
|
||||
struct irq_chip *chip = irq_data_get_irq_chip(data);
|
||||
void __iomem *reg, *ena;
|
||||
unsigned long pending;
|
||||
u32 base, pin;
|
||||
|
||||
/* check from GPIO controller which pin triggered the interrupt */
|
||||
for (base = 0; base < lg->chip.ngpio; base += 32) {
|
||||
reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
|
||||
ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
|
||||
|
||||
/* Only interrupts that are enabled */
|
||||
pending = ioread32(reg) & ioread32(ena);
|
||||
|
||||
for_each_set_bit(pin, &pending, 32) {
|
||||
unsigned int irq;
|
||||
|
||||
irq = irq_find_mapping(lg->chip.irq.domain, base + pin);
|
||||
generic_handle_irq(irq);
|
||||
}
|
||||
}
|
||||
chip->irq_eoi(data);
|
||||
}
|
||||
|
||||
static void lp_irq_ack(struct irq_data *d)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct intel_pinctrl *lg = gpiochip_get_data(gc);
|
||||
u32 hwirq = irqd_to_hwirq(d);
|
||||
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT);
|
||||
unsigned long flags;
|
||||
|
||||
raw_spin_lock_irqsave(&lg->lock, flags);
|
||||
iowrite32(BIT(hwirq % 32), reg);
|
||||
raw_spin_unlock_irqrestore(&lg->lock, flags);
|
||||
}
|
||||
|
||||
static void lp_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
}
|
||||
|
||||
static void lp_irq_mask(struct irq_data *d)
|
||||
{
|
||||
}
|
||||
|
||||
static void lp_irq_enable(struct irq_data *d)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct intel_pinctrl *lg = gpiochip_get_data(gc);
|
||||
u32 hwirq = irqd_to_hwirq(d);
|
||||
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
|
||||
unsigned long flags;
|
||||
|
||||
raw_spin_lock_irqsave(&lg->lock, flags);
|
||||
iowrite32(ioread32(reg) | BIT(hwirq % 32), reg);
|
||||
raw_spin_unlock_irqrestore(&lg->lock, flags);
|
||||
}
|
||||
|
||||
static void lp_irq_disable(struct irq_data *d)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct intel_pinctrl *lg = gpiochip_get_data(gc);
|
||||
u32 hwirq = irqd_to_hwirq(d);
|
||||
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
|
||||
unsigned long flags;
|
||||
|
||||
raw_spin_lock_irqsave(&lg->lock, flags);
|
||||
iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg);
|
||||
raw_spin_unlock_irqrestore(&lg->lock, flags);
|
||||
}
|
||||
|
||||
static int lp_irq_set_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct intel_pinctrl *lg = gpiochip_get_data(gc);
|
||||
u32 hwirq = irqd_to_hwirq(d);
|
||||
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1);
|
||||
unsigned long flags;
|
||||
u32 value;
|
||||
|
||||
if (hwirq >= lg->chip.ngpio)
|
||||
return -EINVAL;
|
||||
|
||||
/* Fail if BIOS reserved pin for ACPI use */
|
||||
if (lp_gpio_acpi_use(lg, hwirq)) {
|
||||
dev_err(lg->dev, "pin %u can't be used as IRQ\n", hwirq);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
raw_spin_lock_irqsave(&lg->lock, flags);
|
||||
value = ioread32(reg);
|
||||
|
||||
/* set both TRIG_SEL and INV bits to 0 for rising edge */
|
||||
if (type & IRQ_TYPE_EDGE_RISING)
|
||||
value &= ~(TRIG_SEL_BIT | INT_INV_BIT);
|
||||
|
||||
/* TRIG_SEL bit 0, INV bit 1 for falling edge */
|
||||
if (type & IRQ_TYPE_EDGE_FALLING)
|
||||
value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT;
|
||||
|
||||
/* TRIG_SEL bit 1, INV bit 0 for level low */
|
||||
if (type & IRQ_TYPE_LEVEL_LOW)
|
||||
value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT;
|
||||
|
||||
/* TRIG_SEL bit 1, INV bit 1 for level high */
|
||||
if (type & IRQ_TYPE_LEVEL_HIGH)
|
||||
value |= TRIG_SEL_BIT | INT_INV_BIT;
|
||||
|
||||
iowrite32(value, reg);
|
||||
|
||||
if (type & IRQ_TYPE_EDGE_BOTH)
|
||||
irq_set_handler_locked(d, handle_edge_irq);
|
||||
else if (type & IRQ_TYPE_LEVEL_MASK)
|
||||
irq_set_handler_locked(d, handle_level_irq);
|
||||
|
||||
raw_spin_unlock_irqrestore(&lg->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_chip lp_irqchip = {
|
||||
.name = "LP-GPIO",
|
||||
.irq_ack = lp_irq_ack,
|
||||
.irq_mask = lp_irq_mask,
|
||||
.irq_unmask = lp_irq_unmask,
|
||||
.irq_enable = lp_irq_enable,
|
||||
.irq_disable = lp_irq_disable,
|
||||
.irq_set_type = lp_irq_set_type,
|
||||
.flags = IRQCHIP_SKIP_SET_WAKE,
|
||||
};
|
||||
|
||||
static int lp_gpio_irq_init_hw(struct gpio_chip *chip)
|
||||
{
|
||||
struct intel_pinctrl *lg = gpiochip_get_data(chip);
|
||||
void __iomem *reg;
|
||||
unsigned int base;
|
||||
|
||||
for (base = 0; base < lg->chip.ngpio; base += 32) {
|
||||
/* disable gpio pin interrupts */
|
||||
reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
|
||||
iowrite32(0, reg);
|
||||
/* Clear interrupt status register */
|
||||
reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
|
||||
iowrite32(0xffffffff, reg);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lp_gpio_add_pin_ranges(struct gpio_chip *chip)
|
||||
{
|
||||
struct intel_pinctrl *lg = gpiochip_get_data(chip);
|
||||
struct device *dev = lg->dev;
|
||||
int ret;
|
||||
|
||||
ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins);
|
||||
if (ret)
|
||||
dev_err(dev, "failed to add GPIO pin range\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int lp_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct intel_pinctrl_soc_data *soc;
|
||||
struct intel_pinctrl *lg;
|
||||
struct gpio_chip *gc;
|
||||
struct resource *io_rc, *irq_rc;
|
||||
struct device *dev = &pdev->dev;
|
||||
void __iomem *regs;
|
||||
unsigned int i;
|
||||
int ret;
|
||||
|
||||
soc = (const struct intel_pinctrl_soc_data *)device_get_match_data(dev);
|
||||
if (!soc)
|
||||
return -ENODEV;
|
||||
|
||||
lg = devm_kzalloc(dev, sizeof(*lg), GFP_KERNEL);
|
||||
if (!lg)
|
||||
return -ENOMEM;
|
||||
|
||||
lg->dev = dev;
|
||||
lg->soc = soc;
|
||||
|
||||
lg->ncommunities = lg->soc->ncommunities;
|
||||
lg->communities = devm_kcalloc(dev, lg->ncommunities,
|
||||
sizeof(*lg->communities), GFP_KERNEL);
|
||||
if (!lg->communities)
|
||||
return -ENOMEM;
|
||||
|
||||
lg->pctldesc = lptlp_pinctrl_desc;
|
||||
lg->pctldesc.name = dev_name(dev);
|
||||
lg->pctldesc.pins = lg->soc->pins;
|
||||
lg->pctldesc.npins = lg->soc->npins;
|
||||
|
||||
lg->pctldev = devm_pinctrl_register(dev, &lg->pctldesc, lg);
|
||||
if (IS_ERR(lg->pctldev)) {
|
||||
dev_err(dev, "failed to register pinctrl driver\n");
|
||||
return PTR_ERR(lg->pctldev);
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, lg);
|
||||
|
||||
io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0);
|
||||
if (!io_rc) {
|
||||
dev_err(dev, "missing IO resources\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc));
|
||||
if (!regs) {
|
||||
dev_err(dev, "failed mapping IO region %pR\n", &io_rc);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
for (i = 0; i < lg->soc->ncommunities; i++) {
|
||||
struct intel_community *comm = &lg->communities[i];
|
||||
|
||||
*comm = lg->soc->communities[i];
|
||||
|
||||
comm->regs = regs;
|
||||
comm->pad_regs = regs + 0x100;
|
||||
}
|
||||
|
||||
raw_spin_lock_init(&lg->lock);
|
||||
|
||||
gc = &lg->chip;
|
||||
gc->label = dev_name(dev);
|
||||
gc->owner = THIS_MODULE;
|
||||
gc->request = gpiochip_generic_request;
|
||||
gc->free = gpiochip_generic_free;
|
||||
gc->direction_input = lp_gpio_direction_input;
|
||||
gc->direction_output = lp_gpio_direction_output;
|
||||
gc->get = lp_gpio_get;
|
||||
gc->set = lp_gpio_set;
|
||||
gc->get_direction = lp_gpio_get_direction;
|
||||
gc->base = -1;
|
||||
gc->ngpio = LP_NUM_GPIO;
|
||||
gc->can_sleep = false;
|
||||
gc->add_pin_ranges = lp_gpio_add_pin_ranges;
|
||||
gc->parent = dev;
|
||||
|
||||
/* set up interrupts */
|
||||
irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (irq_rc && irq_rc->start) {
|
||||
struct gpio_irq_chip *girq;
|
||||
|
||||
girq = &gc->irq;
|
||||
girq->chip = &lp_irqchip;
|
||||
girq->init_hw = lp_gpio_irq_init_hw;
|
||||
girq->parent_handler = lp_gpio_irq_handler;
|
||||
girq->num_parents = 1;
|
||||
girq->parents = devm_kcalloc(dev, girq->num_parents,
|
||||
sizeof(*girq->parents),
|
||||
GFP_KERNEL);
|
||||
if (!girq->parents)
|
||||
return -ENOMEM;
|
||||
girq->parents[0] = (unsigned int)irq_rc->start;
|
||||
girq->default_type = IRQ_TYPE_NONE;
|
||||
girq->handler = handle_bad_irq;
|
||||
}
|
||||
|
||||
ret = devm_gpiochip_add_data(dev, gc, lg);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed adding lp-gpio chip\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pm_runtime_enable(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lp_gpio_remove(struct platform_device *pdev)
|
||||
{
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lp_gpio_runtime_suspend(struct device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lp_gpio_runtime_resume(struct device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lp_gpio_resume(struct device *dev)
|
||||
{
|
||||
struct intel_pinctrl *lg = dev_get_drvdata(dev);
|
||||
void __iomem *reg;
|
||||
int i;
|
||||
|
||||
/* on some hardware suspend clears input sensing, re-enable it here */
|
||||
for (i = 0; i < lg->chip.ngpio; i++) {
|
||||
if (gpiochip_is_requested(&lg->chip, i) != NULL) {
|
||||
reg = lp_gpio_reg(&lg->chip, i, LP_CONFIG2);
|
||||
iowrite32(ioread32(reg) & ~GPINDIS_BIT, reg);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops lp_gpio_pm_ops = {
|
||||
.runtime_suspend = lp_gpio_runtime_suspend,
|
||||
.runtime_resume = lp_gpio_runtime_resume,
|
||||
.resume = lp_gpio_resume,
|
||||
};
|
||||
|
||||
static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = {
|
||||
{ "INT33C7", (kernel_ulong_t)&lptlp_soc_data },
|
||||
{ "INT3437", (kernel_ulong_t)&lptlp_soc_data },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match);
|
||||
|
||||
static struct platform_driver lp_gpio_driver = {
|
||||
.probe = lp_gpio_probe,
|
||||
.remove = lp_gpio_remove,
|
||||
.driver = {
|
||||
.name = "lp_gpio",
|
||||
.pm = &lp_gpio_pm_ops,
|
||||
.acpi_match_table = ACPI_PTR(lynxpoint_gpio_acpi_match),
|
||||
},
|
||||
};
|
||||
|
||||
static int __init lp_gpio_init(void)
|
||||
{
|
||||
return platform_driver_register(&lp_gpio_driver);
|
||||
}
|
||||
|
||||
static void __exit lp_gpio_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&lp_gpio_driver);
|
||||
}
|
||||
|
||||
subsys_initcall(lp_gpio_init);
|
||||
module_exit(lp_gpio_exit);
|
||||
|
||||
MODULE_AUTHOR("Mathias Nyman (Intel)");
|
||||
MODULE_AUTHOR("Andy Shevchenko (Intel)");
|
||||
MODULE_DESCRIPTION("Intel Lynxpoint pinctrl driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:lp_gpio");
|
@ -589,6 +589,7 @@ static const struct intel_pinctrl_soc_data spth_soc_data = {
|
||||
|
||||
static const struct acpi_device_id spt_pinctrl_acpi_match[] = {
|
||||
{ "INT344B", (kernel_ulong_t)&sptlp_soc_data },
|
||||
{ "INT3451", (kernel_ulong_t)&spth_soc_data },
|
||||
{ "INT345D", (kernel_ulong_t)&spth_soc_data },
|
||||
{ }
|
||||
};
|
||||
|
@ -2,7 +2,7 @@
|
||||
/*
|
||||
* Intel Tiger Lake PCH pinctrl/GPIO driver
|
||||
*
|
||||
* Copyright (C) 2019, Intel Corporation
|
||||
* Copyright (C) 2019 - 2020, Intel Corporation
|
||||
* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
||||
* Mika Westerberg <mika.westerberg@linux.intel.com>
|
||||
*/
|
||||
@ -21,15 +21,19 @@
|
||||
#define TGL_GPI_IS 0x100
|
||||
#define TGL_GPI_IE 0x120
|
||||
|
||||
#define TGL_GPP(r, s, e) \
|
||||
#define TGL_NO_GPIO -1
|
||||
|
||||
#define TGL_GPP(r, s, e, g) \
|
||||
{ \
|
||||
.reg_num = (r), \
|
||||
.base = (s), \
|
||||
.size = ((e) - (s) + 1), \
|
||||
.gpio_base = (g), \
|
||||
}
|
||||
|
||||
#define TGL_COMMUNITY(s, e, g) \
|
||||
#define TGL_COMMUNITY(b, s, e, g) \
|
||||
{ \
|
||||
.barno = (b), \
|
||||
.padown_offset = TGL_PAD_OWN, \
|
||||
.padcfglock_offset = TGL_PADCFGLOCK, \
|
||||
.hostown_offset = TGL_HOSTSW_OWN, \
|
||||
@ -42,7 +46,7 @@
|
||||
}
|
||||
|
||||
/* Tiger Lake-LP */
|
||||
static const struct pinctrl_pin_desc tgllp_community0_pins[] = {
|
||||
static const struct pinctrl_pin_desc tgllp_pins[] = {
|
||||
/* GPP_B */
|
||||
PINCTRL_PIN(0, "CORE_VID_0"),
|
||||
PINCTRL_PIN(1, "CORE_VID_1"),
|
||||
@ -113,324 +117,273 @@ static const struct pinctrl_pin_desc tgllp_community0_pins[] = {
|
||||
PINCTRL_PIN(64, "GPPC_A_22"),
|
||||
PINCTRL_PIN(65, "I2S1_SCLK"),
|
||||
PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),
|
||||
/* GPP_S */
|
||||
PINCTRL_PIN(67, "SNDW0_CLK"),
|
||||
PINCTRL_PIN(68, "SNDW0_DATA"),
|
||||
PINCTRL_PIN(69, "SNDW1_CLK"),
|
||||
PINCTRL_PIN(70, "SNDW1_DATA"),
|
||||
PINCTRL_PIN(71, "SNDW2_CLK"),
|
||||
PINCTRL_PIN(72, "SNDW2_DATA"),
|
||||
PINCTRL_PIN(73, "SNDW3_CLK"),
|
||||
PINCTRL_PIN(74, "SNDW3_DATA"),
|
||||
/* GPP_H */
|
||||
PINCTRL_PIN(75, "GPPC_H_0"),
|
||||
PINCTRL_PIN(76, "GPPC_H_1"),
|
||||
PINCTRL_PIN(77, "GPPC_H_2"),
|
||||
PINCTRL_PIN(78, "SX_EXIT_HOLDOFFB"),
|
||||
PINCTRL_PIN(79, "I2C2_SDA"),
|
||||
PINCTRL_PIN(80, "I2C2_SCL"),
|
||||
PINCTRL_PIN(81, "I2C3_SDA"),
|
||||
PINCTRL_PIN(82, "I2C3_SCL"),
|
||||
PINCTRL_PIN(83, "I2C4_SDA"),
|
||||
PINCTRL_PIN(84, "I2C4_SCL"),
|
||||
PINCTRL_PIN(85, "SRCCLKREQB_4"),
|
||||
PINCTRL_PIN(86, "SRCCLKREQB_5"),
|
||||
PINCTRL_PIN(87, "M2_SKT2_CFG_0"),
|
||||
PINCTRL_PIN(88, "M2_SKT2_CFG_1"),
|
||||
PINCTRL_PIN(89, "M2_SKT2_CFG_2"),
|
||||
PINCTRL_PIN(90, "M2_SKT2_CFG_3"),
|
||||
PINCTRL_PIN(91, "DDPB_CTRLCLK"),
|
||||
PINCTRL_PIN(92, "DDPB_CTRLDATA"),
|
||||
PINCTRL_PIN(93, "CPU_C10_GATEB"),
|
||||
PINCTRL_PIN(94, "TIME_SYNC_0"),
|
||||
PINCTRL_PIN(95, "IMGCLKOUT_1"),
|
||||
PINCTRL_PIN(96, "IMGCLKOUT_2"),
|
||||
PINCTRL_PIN(97, "IMGCLKOUT_3"),
|
||||
PINCTRL_PIN(98, "IMGCLKOUT_4"),
|
||||
/* GPP_D */
|
||||
PINCTRL_PIN(99, "ISH_GP_0"),
|
||||
PINCTRL_PIN(100, "ISH_GP_1"),
|
||||
PINCTRL_PIN(101, "ISH_GP_2"),
|
||||
PINCTRL_PIN(102, "ISH_GP_3"),
|
||||
PINCTRL_PIN(103, "IMGCLKOUT_0"),
|
||||
PINCTRL_PIN(104, "SRCCLKREQB_0"),
|
||||
PINCTRL_PIN(105, "SRCCLKREQB_1"),
|
||||
PINCTRL_PIN(106, "SRCCLKREQB_2"),
|
||||
PINCTRL_PIN(107, "SRCCLKREQB_3"),
|
||||
PINCTRL_PIN(108, "ISH_SPI_CSB"),
|
||||
PINCTRL_PIN(109, "ISH_SPI_CLK"),
|
||||
PINCTRL_PIN(110, "ISH_SPI_MISO"),
|
||||
PINCTRL_PIN(111, "ISH_SPI_MOSI"),
|
||||
PINCTRL_PIN(112, "ISH_UART0_RXD"),
|
||||
PINCTRL_PIN(113, "ISH_UART0_TXD"),
|
||||
PINCTRL_PIN(114, "ISH_UART0_RTSB"),
|
||||
PINCTRL_PIN(115, "ISH_UART0_CTSB"),
|
||||
PINCTRL_PIN(116, "ISH_GP_4"),
|
||||
PINCTRL_PIN(117, "ISH_GP_5"),
|
||||
PINCTRL_PIN(118, "I2S_MCLK1_OUT"),
|
||||
PINCTRL_PIN(119, "GSPI2_CLK_LOOPBK"),
|
||||
/* GPP_U */
|
||||
PINCTRL_PIN(120, "UART3_RXD"),
|
||||
PINCTRL_PIN(121, "UART3_TXD"),
|
||||
PINCTRL_PIN(122, "UART3_RTSB"),
|
||||
PINCTRL_PIN(123, "UART3_CTSB"),
|
||||
PINCTRL_PIN(124, "GSPI3_CS0B"),
|
||||
PINCTRL_PIN(125, "GSPI3_CLK"),
|
||||
PINCTRL_PIN(126, "GSPI3_MISO"),
|
||||
PINCTRL_PIN(127, "GSPI3_MOSI"),
|
||||
PINCTRL_PIN(128, "GSPI4_CS0B"),
|
||||
PINCTRL_PIN(129, "GSPI4_CLK"),
|
||||
PINCTRL_PIN(130, "GSPI4_MISO"),
|
||||
PINCTRL_PIN(131, "GSPI4_MOSI"),
|
||||
PINCTRL_PIN(132, "GSPI5_CS0B"),
|
||||
PINCTRL_PIN(133, "GSPI5_CLK"),
|
||||
PINCTRL_PIN(134, "GSPI5_MISO"),
|
||||
PINCTRL_PIN(135, "GSPI5_MOSI"),
|
||||
PINCTRL_PIN(136, "GSPI6_CS0B"),
|
||||
PINCTRL_PIN(137, "GSPI6_CLK"),
|
||||
PINCTRL_PIN(138, "GSPI6_MISO"),
|
||||
PINCTRL_PIN(139, "GSPI6_MOSI"),
|
||||
PINCTRL_PIN(140, "GSPI3_CLK_LOOPBK"),
|
||||
PINCTRL_PIN(141, "GSPI4_CLK_LOOPBK"),
|
||||
PINCTRL_PIN(142, "GSPI5_CLK_LOOPBK"),
|
||||
PINCTRL_PIN(143, "GSPI6_CLK_LOOPBK"),
|
||||
/* vGPIO */
|
||||
PINCTRL_PIN(144, "CNV_BTEN"),
|
||||
PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"),
|
||||
PINCTRL_PIN(146, "CNV_BT_IF_SELECT"),
|
||||
PINCTRL_PIN(147, "vCNV_BT_UART_TXD"),
|
||||
PINCTRL_PIN(148, "vCNV_BT_UART_RXD"),
|
||||
PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"),
|
||||
PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"),
|
||||
PINCTRL_PIN(151, "vCNV_MFUART1_TXD"),
|
||||
PINCTRL_PIN(152, "vCNV_MFUART1_RXD"),
|
||||
PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"),
|
||||
PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"),
|
||||
PINCTRL_PIN(155, "vUART0_TXD"),
|
||||
PINCTRL_PIN(156, "vUART0_RXD"),
|
||||
PINCTRL_PIN(157, "vUART0_CTS_B"),
|
||||
PINCTRL_PIN(158, "vUART0_RTS_B"),
|
||||
PINCTRL_PIN(159, "vISH_UART0_TXD"),
|
||||
PINCTRL_PIN(160, "vISH_UART0_RXD"),
|
||||
PINCTRL_PIN(161, "vISH_UART0_CTS_B"),
|
||||
PINCTRL_PIN(162, "vISH_UART0_RTS_B"),
|
||||
PINCTRL_PIN(163, "vCNV_BT_I2S_BCLK"),
|
||||
PINCTRL_PIN(164, "vCNV_BT_I2S_WS_SYNC"),
|
||||
PINCTRL_PIN(165, "vCNV_BT_I2S_SDO"),
|
||||
PINCTRL_PIN(166, "vCNV_BT_I2S_SDI"),
|
||||
PINCTRL_PIN(167, "vI2S2_SCLK"),
|
||||
PINCTRL_PIN(168, "vI2S2_SFRM"),
|
||||
PINCTRL_PIN(169, "vI2S2_TXD"),
|
||||
PINCTRL_PIN(170, "vI2S2_RXD"),
|
||||
/* GPP_C */
|
||||
PINCTRL_PIN(171, "SMBCLK"),
|
||||
PINCTRL_PIN(172, "SMBDATA"),
|
||||
PINCTRL_PIN(173, "SMBALERTB"),
|
||||
PINCTRL_PIN(174, "SML0CLK"),
|
||||
PINCTRL_PIN(175, "SML0DATA"),
|
||||
PINCTRL_PIN(176, "SML0ALERTB"),
|
||||
PINCTRL_PIN(177, "SML1CLK"),
|
||||
PINCTRL_PIN(178, "SML1DATA"),
|
||||
PINCTRL_PIN(179, "UART0_RXD"),
|
||||
PINCTRL_PIN(180, "UART0_TXD"),
|
||||
PINCTRL_PIN(181, "UART0_RTSB"),
|
||||
PINCTRL_PIN(182, "UART0_CTSB"),
|
||||
PINCTRL_PIN(183, "UART1_RXD"),
|
||||
PINCTRL_PIN(184, "UART1_TXD"),
|
||||
PINCTRL_PIN(185, "UART1_RTSB"),
|
||||
PINCTRL_PIN(186, "UART1_CTSB"),
|
||||
PINCTRL_PIN(187, "I2C0_SDA"),
|
||||
PINCTRL_PIN(188, "I2C0_SCL"),
|
||||
PINCTRL_PIN(189, "I2C1_SDA"),
|
||||
PINCTRL_PIN(190, "I2C1_SCL"),
|
||||
PINCTRL_PIN(191, "UART2_RXD"),
|
||||
PINCTRL_PIN(192, "UART2_TXD"),
|
||||
PINCTRL_PIN(193, "UART2_RTSB"),
|
||||
PINCTRL_PIN(194, "UART2_CTSB"),
|
||||
/* GPP_F */
|
||||
PINCTRL_PIN(195, "CNV_BRI_DT"),
|
||||
PINCTRL_PIN(196, "CNV_BRI_RSP"),
|
||||
PINCTRL_PIN(197, "CNV_RGI_DT"),
|
||||
PINCTRL_PIN(198, "CNV_RGI_RSP"),
|
||||
PINCTRL_PIN(199, "CNV_RF_RESET_B"),
|
||||
PINCTRL_PIN(200, "GPPC_F_5"),
|
||||
PINCTRL_PIN(201, "CNV_PA_BLANKING"),
|
||||
PINCTRL_PIN(202, "GPPC_F_7"),
|
||||
PINCTRL_PIN(203, "I2S_MCLK2_INOUT"),
|
||||
PINCTRL_PIN(204, "BOOTMPC"),
|
||||
PINCTRL_PIN(205, "GPPC_F_10"),
|
||||
PINCTRL_PIN(206, "GPPC_F_11"),
|
||||
PINCTRL_PIN(207, "GSXDOUT"),
|
||||
PINCTRL_PIN(208, "GSXSLOAD"),
|
||||
PINCTRL_PIN(209, "GSXDIN"),
|
||||
PINCTRL_PIN(210, "GSXSRESETB"),
|
||||
PINCTRL_PIN(211, "GSXCLK"),
|
||||
PINCTRL_PIN(212, "GMII_MDC"),
|
||||
PINCTRL_PIN(213, "GMII_MDIO"),
|
||||
PINCTRL_PIN(214, "SRCCLKREQB_6"),
|
||||
PINCTRL_PIN(215, "EXT_PWR_GATEB"),
|
||||
PINCTRL_PIN(216, "EXT_PWR_GATE2B"),
|
||||
PINCTRL_PIN(217, "VNN_CTRL"),
|
||||
PINCTRL_PIN(218, "V1P05_CTRL"),
|
||||
PINCTRL_PIN(219, "GPPF_CLK_LOOPBACK"),
|
||||
/* HVCMOS */
|
||||
PINCTRL_PIN(220, "L_BKLTEN"),
|
||||
PINCTRL_PIN(221, "L_BKLTCTL"),
|
||||
PINCTRL_PIN(222, "L_VDDEN"),
|
||||
PINCTRL_PIN(223, "SYS_PWROK"),
|
||||
PINCTRL_PIN(224, "SYS_RESETB"),
|
||||
PINCTRL_PIN(225, "MLK_RSTB"),
|
||||
/* GPP_E */
|
||||
PINCTRL_PIN(226, "SATAXPCIE_0"),
|
||||
PINCTRL_PIN(227, "SPI1_IO_2"),
|
||||
PINCTRL_PIN(228, "SPI1_IO_3"),
|
||||
PINCTRL_PIN(229, "CPU_GP_0"),
|
||||
PINCTRL_PIN(230, "SATA_DEVSLP_0"),
|
||||
PINCTRL_PIN(231, "SATA_DEVSLP_1"),
|
||||
PINCTRL_PIN(232, "GPPC_E_6"),
|
||||
PINCTRL_PIN(233, "CPU_GP_1"),
|
||||
PINCTRL_PIN(234, "SPI1_CS1B"),
|
||||
PINCTRL_PIN(235, "USB2_OCB_0"),
|
||||
PINCTRL_PIN(236, "SPI1_CSB"),
|
||||
PINCTRL_PIN(237, "SPI1_CLK"),
|
||||
PINCTRL_PIN(238, "SPI1_MISO_IO_1"),
|
||||
PINCTRL_PIN(239, "SPI1_MOSI_IO_0"),
|
||||
PINCTRL_PIN(240, "DDSP_HPD_A"),
|
||||
PINCTRL_PIN(241, "ISH_GP_6"),
|
||||
PINCTRL_PIN(242, "ISH_GP_7"),
|
||||
PINCTRL_PIN(243, "GPPC_E_17"),
|
||||
PINCTRL_PIN(244, "DDP1_CTRLCLK"),
|
||||
PINCTRL_PIN(245, "DDP1_CTRLDATA"),
|
||||
PINCTRL_PIN(246, "DDP2_CTRLCLK"),
|
||||
PINCTRL_PIN(247, "DDP2_CTRLDATA"),
|
||||
PINCTRL_PIN(248, "DDPA_CTRLCLK"),
|
||||
PINCTRL_PIN(249, "DDPA_CTRLDATA"),
|
||||
PINCTRL_PIN(250, "SPI1_CLK_LOOPBK"),
|
||||
/* JTAG */
|
||||
PINCTRL_PIN(251, "JTAG_TDO"),
|
||||
PINCTRL_PIN(252, "JTAGX"),
|
||||
PINCTRL_PIN(253, "PRDYB"),
|
||||
PINCTRL_PIN(254, "PREQB"),
|
||||
PINCTRL_PIN(255, "CPU_TRSTB"),
|
||||
PINCTRL_PIN(256, "JTAG_TDI"),
|
||||
PINCTRL_PIN(257, "JTAG_TMS"),
|
||||
PINCTRL_PIN(258, "JTAG_TCK"),
|
||||
PINCTRL_PIN(259, "DBG_PMODE"),
|
||||
/* GPP_R */
|
||||
PINCTRL_PIN(260, "HDA_BCLK"),
|
||||
PINCTRL_PIN(261, "HDA_SYNC"),
|
||||
PINCTRL_PIN(262, "HDA_SDO"),
|
||||
PINCTRL_PIN(263, "HDA_SDI_0"),
|
||||
PINCTRL_PIN(264, "HDA_RSTB"),
|
||||
PINCTRL_PIN(265, "HDA_SDI_1"),
|
||||
PINCTRL_PIN(266, "GPP_R_6"),
|
||||
PINCTRL_PIN(267, "GPP_R_7"),
|
||||
/* SPI */
|
||||
PINCTRL_PIN(268, "SPI0_IO_2"),
|
||||
PINCTRL_PIN(269, "SPI0_IO_3"),
|
||||
PINCTRL_PIN(270, "SPI0_MOSI_IO_0"),
|
||||
PINCTRL_PIN(271, "SPI0_MISO_IO_1"),
|
||||
PINCTRL_PIN(272, "SPI0_TPM_CSB"),
|
||||
PINCTRL_PIN(273, "SPI0_FLASH_0_CSB"),
|
||||
PINCTRL_PIN(274, "SPI0_FLASH_1_CSB"),
|
||||
PINCTRL_PIN(275, "SPI0_CLK"),
|
||||
PINCTRL_PIN(276, "SPI0_CLK_LOOPBK"),
|
||||
};
|
||||
|
||||
static const struct intel_padgroup tgllp_community0_gpps[] = {
|
||||
TGL_GPP(0, 0, 25), /* GPP_B */
|
||||
TGL_GPP(1, 26, 41), /* GPP_T */
|
||||
TGL_GPP(2, 42, 66), /* GPP_A */
|
||||
};
|
||||
|
||||
static const struct intel_community tgllp_community0[] = {
|
||||
TGL_COMMUNITY(0, 66, tgllp_community0_gpps),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data tgllp_community0_soc_data = {
|
||||
.uid = "0",
|
||||
.pins = tgllp_community0_pins,
|
||||
.npins = ARRAY_SIZE(tgllp_community0_pins),
|
||||
.communities = tgllp_community0,
|
||||
.ncommunities = ARRAY_SIZE(tgllp_community0),
|
||||
};
|
||||
|
||||
static const struct pinctrl_pin_desc tgllp_community1_pins[] = {
|
||||
/* GPP_S */
|
||||
PINCTRL_PIN(0, "SNDW0_CLK"),
|
||||
PINCTRL_PIN(1, "SNDW0_DATA"),
|
||||
PINCTRL_PIN(2, "SNDW1_CLK"),
|
||||
PINCTRL_PIN(3, "SNDW1_DATA"),
|
||||
PINCTRL_PIN(4, "SNDW2_CLK"),
|
||||
PINCTRL_PIN(5, "SNDW2_DATA"),
|
||||
PINCTRL_PIN(6, "SNDW3_CLK"),
|
||||
PINCTRL_PIN(7, "SNDW3_DATA"),
|
||||
/* GPP_H */
|
||||
PINCTRL_PIN(8, "GPPC_H_0"),
|
||||
PINCTRL_PIN(9, "GPPC_H_1"),
|
||||
PINCTRL_PIN(10, "GPPC_H_2"),
|
||||
PINCTRL_PIN(11, "SX_EXIT_HOLDOFFB"),
|
||||
PINCTRL_PIN(12, "I2C2_SDA"),
|
||||
PINCTRL_PIN(13, "I2C2_SCL"),
|
||||
PINCTRL_PIN(14, "I2C3_SDA"),
|
||||
PINCTRL_PIN(15, "I2C3_SCL"),
|
||||
PINCTRL_PIN(16, "I2C4_SDA"),
|
||||
PINCTRL_PIN(17, "I2C4_SCL"),
|
||||
PINCTRL_PIN(18, "SRCCLKREQB_4"),
|
||||
PINCTRL_PIN(19, "SRCCLKREQB_5"),
|
||||
PINCTRL_PIN(20, "M2_SKT2_CFG_0"),
|
||||
PINCTRL_PIN(21, "M2_SKT2_CFG_1"),
|
||||
PINCTRL_PIN(22, "M2_SKT2_CFG_2"),
|
||||
PINCTRL_PIN(23, "M2_SKT2_CFG_3"),
|
||||
PINCTRL_PIN(24, "DDPB_CTRLCLK"),
|
||||
PINCTRL_PIN(25, "DDPB_CTRLDATA"),
|
||||
PINCTRL_PIN(26, "CPU_C10_GATEB"),
|
||||
PINCTRL_PIN(27, "TIME_SYNC_0"),
|
||||
PINCTRL_PIN(28, "IMGCLKOUT_1"),
|
||||
PINCTRL_PIN(29, "IMGCLKOUT_2"),
|
||||
PINCTRL_PIN(30, "IMGCLKOUT_3"),
|
||||
PINCTRL_PIN(31, "IMGCLKOUT_4"),
|
||||
/* GPP_D */
|
||||
PINCTRL_PIN(32, "ISH_GP_0"),
|
||||
PINCTRL_PIN(33, "ISH_GP_1"),
|
||||
PINCTRL_PIN(34, "ISH_GP_2"),
|
||||
PINCTRL_PIN(35, "ISH_GP_3"),
|
||||
PINCTRL_PIN(36, "IMGCLKOUT_0"),
|
||||
PINCTRL_PIN(37, "SRCCLKREQB_0"),
|
||||
PINCTRL_PIN(38, "SRCCLKREQB_1"),
|
||||
PINCTRL_PIN(39, "SRCCLKREQB_2"),
|
||||
PINCTRL_PIN(40, "SRCCLKREQB_3"),
|
||||
PINCTRL_PIN(41, "ISH_SPI_CSB"),
|
||||
PINCTRL_PIN(42, "ISH_SPI_CLK"),
|
||||
PINCTRL_PIN(43, "ISH_SPI_MISO"),
|
||||
PINCTRL_PIN(44, "ISH_SPI_MOSI"),
|
||||
PINCTRL_PIN(45, "ISH_UART0_RXD"),
|
||||
PINCTRL_PIN(46, "ISH_UART0_TXD"),
|
||||
PINCTRL_PIN(47, "ISH_UART0_RTSB"),
|
||||
PINCTRL_PIN(48, "ISH_UART0_CTSB"),
|
||||
PINCTRL_PIN(49, "ISH_GP_4"),
|
||||
PINCTRL_PIN(50, "ISH_GP_5"),
|
||||
PINCTRL_PIN(51, "I2S_MCLK1_OUT"),
|
||||
PINCTRL_PIN(52, "GSPI2_CLK_LOOPBK"),
|
||||
/* GPP_U */
|
||||
PINCTRL_PIN(53, "UART3_RXD"),
|
||||
PINCTRL_PIN(54, "UART3_TXD"),
|
||||
PINCTRL_PIN(55, "UART3_RTSB"),
|
||||
PINCTRL_PIN(56, "UART3_CTSB"),
|
||||
PINCTRL_PIN(57, "GSPI3_CS0B"),
|
||||
PINCTRL_PIN(58, "GSPI3_CLK"),
|
||||
PINCTRL_PIN(59, "GSPI3_MISO"),
|
||||
PINCTRL_PIN(60, "GSPI3_MOSI"),
|
||||
PINCTRL_PIN(61, "GSPI4_CS0B"),
|
||||
PINCTRL_PIN(62, "GSPI4_CLK"),
|
||||
PINCTRL_PIN(63, "GSPI4_MISO"),
|
||||
PINCTRL_PIN(64, "GSPI4_MOSI"),
|
||||
PINCTRL_PIN(65, "GSPI5_CS0B"),
|
||||
PINCTRL_PIN(66, "GSPI5_CLK"),
|
||||
PINCTRL_PIN(67, "GSPI5_MISO"),
|
||||
PINCTRL_PIN(68, "GSPI5_MOSI"),
|
||||
PINCTRL_PIN(69, "GSPI6_CS0B"),
|
||||
PINCTRL_PIN(70, "GSPI6_CLK"),
|
||||
PINCTRL_PIN(71, "GSPI6_MISO"),
|
||||
PINCTRL_PIN(72, "GSPI6_MOSI"),
|
||||
PINCTRL_PIN(73, "GSPI3_CLK_LOOPBK"),
|
||||
PINCTRL_PIN(74, "GSPI4_CLK_LOOPBK"),
|
||||
PINCTRL_PIN(75, "GSPI5_CLK_LOOPBK"),
|
||||
PINCTRL_PIN(76, "GSPI6_CLK_LOOPBK"),
|
||||
/* vGPIO */
|
||||
PINCTRL_PIN(77, "CNV_BTEN"),
|
||||
PINCTRL_PIN(78, "CNV_BT_HOST_WAKEB"),
|
||||
PINCTRL_PIN(79, "CNV_BT_IF_SELECT"),
|
||||
PINCTRL_PIN(80, "vCNV_BT_UART_TXD"),
|
||||
PINCTRL_PIN(81, "vCNV_BT_UART_RXD"),
|
||||
PINCTRL_PIN(82, "vCNV_BT_UART_CTS_B"),
|
||||
PINCTRL_PIN(83, "vCNV_BT_UART_RTS_B"),
|
||||
PINCTRL_PIN(84, "vCNV_MFUART1_TXD"),
|
||||
PINCTRL_PIN(85, "vCNV_MFUART1_RXD"),
|
||||
PINCTRL_PIN(86, "vCNV_MFUART1_CTS_B"),
|
||||
PINCTRL_PIN(87, "vCNV_MFUART1_RTS_B"),
|
||||
PINCTRL_PIN(88, "vUART0_TXD"),
|
||||
PINCTRL_PIN(89, "vUART0_RXD"),
|
||||
PINCTRL_PIN(90, "vUART0_CTS_B"),
|
||||
PINCTRL_PIN(91, "vUART0_RTS_B"),
|
||||
PINCTRL_PIN(92, "vISH_UART0_TXD"),
|
||||
PINCTRL_PIN(93, "vISH_UART0_RXD"),
|
||||
PINCTRL_PIN(94, "vISH_UART0_CTS_B"),
|
||||
PINCTRL_PIN(95, "vISH_UART0_RTS_B"),
|
||||
PINCTRL_PIN(96, "vCNV_BT_I2S_BCLK"),
|
||||
PINCTRL_PIN(97, "vCNV_BT_I2S_WS_SYNC"),
|
||||
PINCTRL_PIN(98, "vCNV_BT_I2S_SDO"),
|
||||
PINCTRL_PIN(99, "vCNV_BT_I2S_SDI"),
|
||||
PINCTRL_PIN(100, "vI2S2_SCLK"),
|
||||
PINCTRL_PIN(101, "vI2S2_SFRM"),
|
||||
PINCTRL_PIN(102, "vI2S2_TXD"),
|
||||
PINCTRL_PIN(103, "vI2S2_RXD"),
|
||||
TGL_GPP(0, 0, 25, 0), /* GPP_B */
|
||||
TGL_GPP(1, 26, 41, 32), /* GPP_T */
|
||||
TGL_GPP(2, 42, 66, 64), /* GPP_A */
|
||||
};
|
||||
|
||||
static const struct intel_padgroup tgllp_community1_gpps[] = {
|
||||
TGL_GPP(0, 0, 7), /* GPP_S */
|
||||
TGL_GPP(1, 8, 31), /* GPP_H */
|
||||
TGL_GPP(2, 32, 52), /* GPP_D */
|
||||
TGL_GPP(3, 53, 76), /* GPP_U */
|
||||
TGL_GPP(4, 77, 103), /* vGPIO */
|
||||
};
|
||||
|
||||
static const struct intel_community tgllp_community1[] = {
|
||||
TGL_COMMUNITY(0, 103, tgllp_community1_gpps),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data tgllp_community1_soc_data = {
|
||||
.uid = "1",
|
||||
.pins = tgllp_community1_pins,
|
||||
.npins = ARRAY_SIZE(tgllp_community1_pins),
|
||||
.communities = tgllp_community1,
|
||||
.ncommunities = ARRAY_SIZE(tgllp_community1),
|
||||
};
|
||||
|
||||
static const struct pinctrl_pin_desc tgllp_community4_pins[] = {
|
||||
/* GPP_C */
|
||||
PINCTRL_PIN(0, "SMBCLK"),
|
||||
PINCTRL_PIN(1, "SMBDATA"),
|
||||
PINCTRL_PIN(2, "SMBALERTB"),
|
||||
PINCTRL_PIN(3, "SML0CLK"),
|
||||
PINCTRL_PIN(4, "SML0DATA"),
|
||||
PINCTRL_PIN(5, "SML0ALERTB"),
|
||||
PINCTRL_PIN(6, "SML1CLK"),
|
||||
PINCTRL_PIN(7, "SML1DATA"),
|
||||
PINCTRL_PIN(8, "UART0_RXD"),
|
||||
PINCTRL_PIN(9, "UART0_TXD"),
|
||||
PINCTRL_PIN(10, "UART0_RTSB"),
|
||||
PINCTRL_PIN(11, "UART0_CTSB"),
|
||||
PINCTRL_PIN(12, "UART1_RXD"),
|
||||
PINCTRL_PIN(13, "UART1_TXD"),
|
||||
PINCTRL_PIN(14, "UART1_RTSB"),
|
||||
PINCTRL_PIN(15, "UART1_CTSB"),
|
||||
PINCTRL_PIN(16, "I2C0_SDA"),
|
||||
PINCTRL_PIN(17, "I2C0_SCL"),
|
||||
PINCTRL_PIN(18, "I2C1_SDA"),
|
||||
PINCTRL_PIN(19, "I2C1_SCL"),
|
||||
PINCTRL_PIN(20, "UART2_RXD"),
|
||||
PINCTRL_PIN(21, "UART2_TXD"),
|
||||
PINCTRL_PIN(22, "UART2_RTSB"),
|
||||
PINCTRL_PIN(23, "UART2_CTSB"),
|
||||
/* GPP_F */
|
||||
PINCTRL_PIN(24, "CNV_BRI_DT"),
|
||||
PINCTRL_PIN(25, "CNV_BRI_RSP"),
|
||||
PINCTRL_PIN(26, "CNV_RGI_DT"),
|
||||
PINCTRL_PIN(27, "CNV_RGI_RSP"),
|
||||
PINCTRL_PIN(28, "CNV_RF_RESET_B"),
|
||||
PINCTRL_PIN(29, "GPPC_F_5"),
|
||||
PINCTRL_PIN(30, "CNV_PA_BLANKING"),
|
||||
PINCTRL_PIN(31, "GPPC_F_7"),
|
||||
PINCTRL_PIN(32, "I2S_MCLK2_INOUT"),
|
||||
PINCTRL_PIN(33, "BOOTMPC"),
|
||||
PINCTRL_PIN(34, "GPPC_F_10"),
|
||||
PINCTRL_PIN(35, "GPPC_F_11"),
|
||||
PINCTRL_PIN(36, "GSXDOUT"),
|
||||
PINCTRL_PIN(37, "GSXSLOAD"),
|
||||
PINCTRL_PIN(38, "GSXDIN"),
|
||||
PINCTRL_PIN(39, "GSXSRESETB"),
|
||||
PINCTRL_PIN(40, "GSXCLK"),
|
||||
PINCTRL_PIN(41, "GMII_MDC"),
|
||||
PINCTRL_PIN(42, "GMII_MDIO"),
|
||||
PINCTRL_PIN(43, "SRCCLKREQB_6"),
|
||||
PINCTRL_PIN(44, "EXT_PWR_GATEB"),
|
||||
PINCTRL_PIN(45, "EXT_PWR_GATE2B"),
|
||||
PINCTRL_PIN(46, "VNN_CTRL"),
|
||||
PINCTRL_PIN(47, "V1P05_CTRL"),
|
||||
PINCTRL_PIN(48, "GPPF_CLK_LOOPBACK"),
|
||||
/* HVCMOS */
|
||||
PINCTRL_PIN(49, "L_BKLTEN"),
|
||||
PINCTRL_PIN(50, "L_BKLTCTL"),
|
||||
PINCTRL_PIN(51, "L_VDDEN"),
|
||||
PINCTRL_PIN(52, "SYS_PWROK"),
|
||||
PINCTRL_PIN(53, "SYS_RESETB"),
|
||||
PINCTRL_PIN(54, "MLK_RSTB"),
|
||||
/* GPP_E */
|
||||
PINCTRL_PIN(55, "SATAXPCIE_0"),
|
||||
PINCTRL_PIN(56, "SPI1_IO_2"),
|
||||
PINCTRL_PIN(57, "SPI1_IO_3"),
|
||||
PINCTRL_PIN(58, "CPU_GP_0"),
|
||||
PINCTRL_PIN(59, "SATA_DEVSLP_0"),
|
||||
PINCTRL_PIN(60, "SATA_DEVSLP_1"),
|
||||
PINCTRL_PIN(61, "GPPC_E_6"),
|
||||
PINCTRL_PIN(62, "CPU_GP_1"),
|
||||
PINCTRL_PIN(63, "SPI1_CS1B"),
|
||||
PINCTRL_PIN(64, "USB2_OCB_0"),
|
||||
PINCTRL_PIN(65, "SPI1_CSB"),
|
||||
PINCTRL_PIN(66, "SPI1_CLK"),
|
||||
PINCTRL_PIN(67, "SPI1_MISO_IO_1"),
|
||||
PINCTRL_PIN(68, "SPI1_MOSI_IO_0"),
|
||||
PINCTRL_PIN(69, "DDSP_HPD_A"),
|
||||
PINCTRL_PIN(70, "ISH_GP_6"),
|
||||
PINCTRL_PIN(71, "ISH_GP_7"),
|
||||
PINCTRL_PIN(72, "GPPC_E_17"),
|
||||
PINCTRL_PIN(73, "DDP1_CTRLCLK"),
|
||||
PINCTRL_PIN(74, "DDP1_CTRLDATA"),
|
||||
PINCTRL_PIN(75, "DDP2_CTRLCLK"),
|
||||
PINCTRL_PIN(76, "DDP2_CTRLDATA"),
|
||||
PINCTRL_PIN(77, "DDPA_CTRLCLK"),
|
||||
PINCTRL_PIN(78, "DDPA_CTRLDATA"),
|
||||
PINCTRL_PIN(79, "SPI1_CLK_LOOPBK"),
|
||||
/* JTAG */
|
||||
PINCTRL_PIN(80, "JTAG_TDO"),
|
||||
PINCTRL_PIN(81, "JTAGX"),
|
||||
PINCTRL_PIN(82, "PRDYB"),
|
||||
PINCTRL_PIN(83, "PREQB"),
|
||||
PINCTRL_PIN(84, "CPU_TRSTB"),
|
||||
PINCTRL_PIN(85, "JTAG_TDI"),
|
||||
PINCTRL_PIN(86, "JTAG_TMS"),
|
||||
PINCTRL_PIN(87, "JTAG_TCK"),
|
||||
PINCTRL_PIN(88, "DBG_PMODE"),
|
||||
TGL_GPP(0, 67, 74, 96), /* GPP_S */
|
||||
TGL_GPP(1, 75, 98, 128), /* GPP_H */
|
||||
TGL_GPP(2, 99, 119, 160), /* GPP_D */
|
||||
TGL_GPP(3, 120, 143, 192), /* GPP_U */
|
||||
TGL_GPP(4, 144, 170, 224), /* vGPIO */
|
||||
};
|
||||
|
||||
static const struct intel_padgroup tgllp_community4_gpps[] = {
|
||||
TGL_GPP(0, 0, 23), /* GPP_C */
|
||||
TGL_GPP(1, 24, 48), /* GPP_F */
|
||||
TGL_GPP(2, 49, 54), /* HVCMOS */
|
||||
TGL_GPP(3, 55, 79), /* GPP_E */
|
||||
TGL_GPP(4, 80, 88), /* JTAG */
|
||||
};
|
||||
|
||||
static const struct intel_community tgllp_community4[] = {
|
||||
TGL_COMMUNITY(0, 88, tgllp_community4_gpps),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data tgllp_community4_soc_data = {
|
||||
.uid = "4",
|
||||
.pins = tgllp_community4_pins,
|
||||
.npins = ARRAY_SIZE(tgllp_community4_pins),
|
||||
.communities = tgllp_community4,
|
||||
.ncommunities = ARRAY_SIZE(tgllp_community4),
|
||||
};
|
||||
|
||||
static const struct pinctrl_pin_desc tgllp_community5_pins[] = {
|
||||
/* GPP_R */
|
||||
PINCTRL_PIN(0, "HDA_BCLK"),
|
||||
PINCTRL_PIN(1, "HDA_SYNC"),
|
||||
PINCTRL_PIN(2, "HDA_SDO"),
|
||||
PINCTRL_PIN(3, "HDA_SDI_0"),
|
||||
PINCTRL_PIN(4, "HDA_RSTB"),
|
||||
PINCTRL_PIN(5, "HDA_SDI_1"),
|
||||
PINCTRL_PIN(6, "GPP_R_6"),
|
||||
PINCTRL_PIN(7, "GPP_R_7"),
|
||||
/* SPI */
|
||||
PINCTRL_PIN(8, "SPI0_IO_2"),
|
||||
PINCTRL_PIN(9, "SPI0_IO_3"),
|
||||
PINCTRL_PIN(10, "SPI0_MOSI_IO_0"),
|
||||
PINCTRL_PIN(11, "SPI0_MISO_IO_1"),
|
||||
PINCTRL_PIN(12, "SPI0_TPM_CSB"),
|
||||
PINCTRL_PIN(13, "SPI0_FLASH_0_CSB"),
|
||||
PINCTRL_PIN(14, "SPI0_FLASH_1_CSB"),
|
||||
PINCTRL_PIN(15, "SPI0_CLK"),
|
||||
PINCTRL_PIN(16, "SPI0_CLK_LOOPBK"),
|
||||
TGL_GPP(0, 171, 194, 256), /* GPP_C */
|
||||
TGL_GPP(1, 195, 219, 288), /* GPP_F */
|
||||
TGL_GPP(2, 220, 225, TGL_NO_GPIO), /* HVCMOS */
|
||||
TGL_GPP(3, 226, 250, 320), /* GPP_E */
|
||||
TGL_GPP(4, 251, 259, TGL_NO_GPIO), /* JTAG */
|
||||
};
|
||||
|
||||
static const struct intel_padgroup tgllp_community5_gpps[] = {
|
||||
TGL_GPP(0, 0, 7), /* GPP_R */
|
||||
TGL_GPP(1, 8, 16), /* SPI */
|
||||
TGL_GPP(0, 260, 267, 352), /* GPP_R */
|
||||
TGL_GPP(1, 268, 276, TGL_NO_GPIO), /* SPI */
|
||||
};
|
||||
|
||||
static const struct intel_community tgllp_community5[] = {
|
||||
TGL_COMMUNITY(0, 16, tgllp_community5_gpps),
|
||||
static const struct intel_community tgllp_communities[] = {
|
||||
TGL_COMMUNITY(0, 0, 66, tgllp_community0_gpps),
|
||||
TGL_COMMUNITY(1, 67, 170, tgllp_community1_gpps),
|
||||
TGL_COMMUNITY(2, 171, 259, tgllp_community4_gpps),
|
||||
TGL_COMMUNITY(3, 260, 276, tgllp_community5_gpps),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data tgllp_community5_soc_data = {
|
||||
.uid = "5",
|
||||
.pins = tgllp_community5_pins,
|
||||
.npins = ARRAY_SIZE(tgllp_community5_pins),
|
||||
.communities = tgllp_community5,
|
||||
.ncommunities = ARRAY_SIZE(tgllp_community5),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data *tgllp_soc_data_array[] = {
|
||||
&tgllp_community0_soc_data,
|
||||
&tgllp_community1_soc_data,
|
||||
&tgllp_community4_soc_data,
|
||||
&tgllp_community5_soc_data,
|
||||
NULL
|
||||
static const struct intel_pinctrl_soc_data tgllp_soc_data = {
|
||||
.pins = tgllp_pins,
|
||||
.npins = ARRAY_SIZE(tgllp_pins),
|
||||
.communities = tgllp_communities,
|
||||
.ncommunities = ARRAY_SIZE(tgllp_communities),
|
||||
};
|
||||
|
||||
static const struct acpi_device_id tgl_pinctrl_acpi_match[] = {
|
||||
{ "INT34C5", (kernel_ulong_t)tgllp_soc_data_array },
|
||||
{ "INT34C5", (kernel_ulong_t)&tgllp_soc_data },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match);
|
||||
@ -438,7 +391,7 @@ MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match);
|
||||
static INTEL_PINCTRL_PM_OPS(tgl_pinctrl_pm_ops);
|
||||
|
||||
static struct platform_driver tgl_pinctrl_driver = {
|
||||
.probe = intel_pinctrl_probe_by_uid,
|
||||
.probe = intel_pinctrl_probe_by_hid,
|
||||
.driver = {
|
||||
.name = "tigerlake-pinctrl",
|
||||
.acpi_match_table = tgl_pinctrl_acpi_match,
|
||||
|
@ -1,4 +1,4 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2018 MediaTek Inc.
|
||||
* Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
|
||||
|
@ -1,3 +1,4 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
|
||||
/*
|
||||
* Copyright (c) 2017 Baylibre SAS.
|
||||
* Author: Jerome Brunet <jbrunet@baylibre.com>
|
||||
@ -5,7 +6,6 @@
|
||||
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
|
||||
* Author: Xingyu Chen <xingyu.chen@amlogic.com>
|
||||
*
|
||||
* SPDX-License-Identifier: (GPL-2.0+ or MIT)
|
||||
*/
|
||||
|
||||
struct meson_pmx_bank {
|
||||
|
@ -233,6 +233,8 @@ static const unsigned int hdmi_scl_pins[] = { GPIOH_2 };
|
||||
static const unsigned int hdmi_cec_0_pins[] = { GPIOH_3 };
|
||||
static const unsigned int eth_txd1_0_pins[] = { GPIOH_5 };
|
||||
static const unsigned int eth_txd0_0_pins[] = { GPIOH_6 };
|
||||
static const unsigned int eth_rxd3_h_pins[] = { GPIOH_5 };
|
||||
static const unsigned int eth_rxd2_h_pins[] = { GPIOH_6 };
|
||||
static const unsigned int clk_24m_out_pins[] = { GPIOH_9 };
|
||||
|
||||
static const unsigned int spi_ss1_pins[] = { GPIOH_0 };
|
||||
@ -535,6 +537,8 @@ static struct meson_pmx_group meson8b_cbus_groups[] = {
|
||||
GROUP(spi_miso_1, 9, 12),
|
||||
GROUP(spi_mosi_1, 9, 11),
|
||||
GROUP(spi_sclk_1, 9, 10),
|
||||
GROUP(eth_rxd3_h, 6, 15),
|
||||
GROUP(eth_rxd2_h, 6, 14),
|
||||
GROUP(eth_txd3, 6, 13),
|
||||
GROUP(eth_txd2, 6, 12),
|
||||
GROUP(eth_tx_clk, 6, 11),
|
||||
@ -746,7 +750,8 @@ static const char * const ethernet_groups[] = {
|
||||
"eth_tx_clk", "eth_tx_en", "eth_txd1_0", "eth_txd1_1",
|
||||
"eth_txd0_0", "eth_txd0_1", "eth_rx_clk", "eth_rx_dv",
|
||||
"eth_rxd1", "eth_rxd0", "eth_mdio_en", "eth_mdc", "eth_ref_clk",
|
||||
"eth_txd2", "eth_txd3", "eth_rxd3", "eth_rxd2"
|
||||
"eth_txd2", "eth_txd3", "eth_rxd3", "eth_rxd2",
|
||||
"eth_rxd3_h", "eth_rxd2_h"
|
||||
};
|
||||
|
||||
static const char * const i2c_a_groups[] = {
|
||||
|
@ -15,7 +15,6 @@
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/pinctrl/pinconf-generic.h>
|
||||
#include <linux/pinctrl/pinconf.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
@ -733,13 +732,20 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev,
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
};
|
||||
}
|
||||
if (ret) {
|
||||
dev_err(dev, "no gpio-controller child node\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
nr_irq_parent = of_irq_count(np);
|
||||
nr_irq_parent = platform_irq_count(pdev);
|
||||
if (nr_irq_parent < 0) {
|
||||
if (nr_irq_parent != -EPROBE_DEFER)
|
||||
dev_err(dev, "Couldn't determine irq count: %pe\n",
|
||||
ERR_PTR(nr_irq_parent));
|
||||
return nr_irq_parent;
|
||||
}
|
||||
|
||||
spin_lock_init(&info->irq_lock);
|
||||
|
||||
if (!nr_irq_parent) {
|
||||
@ -776,7 +782,7 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev,
|
||||
if (!girq->parents)
|
||||
return -ENOMEM;
|
||||
for (i = 0; i < nr_irq_parent; i++) {
|
||||
int irq = irq_of_parse_and_map(np, i);
|
||||
int irq = platform_get_irq(pdev, i);
|
||||
|
||||
if (irq < 0)
|
||||
continue;
|
||||
@ -800,7 +806,7 @@ static int armada_37xx_gpiochip_register(struct platform_device *pdev,
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
};
|
||||
}
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
@ -331,7 +331,7 @@ static unsigned int npcmgpio_irq_startup(struct irq_data *d)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_chip npcmgpio_irqchip = {
|
||||
static const struct irq_chip npcmgpio_irqchip = {
|
||||
.name = "NPCM7XX-GPIO-IRQ",
|
||||
.irq_ack = npcmgpio_irq_ack,
|
||||
.irq_unmask = npcmgpio_irq_unmask,
|
||||
|
@ -798,7 +798,7 @@ static int artpec6_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
enum pin_config_param param;
|
||||
unsigned int arg;
|
||||
unsigned int regval;
|
||||
unsigned int *reg;
|
||||
void __iomem *reg;
|
||||
int i;
|
||||
|
||||
/* Check for valid pin */
|
||||
|
File diff suppressed because it is too large
Load Diff
@ -1229,8 +1229,8 @@ static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl,
|
||||
|
||||
pinctrl_add_gpio_range(rza1_pctl->pctl, range);
|
||||
|
||||
dev_info(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n",
|
||||
chip->label, chip->ngpio);
|
||||
dev_dbg(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n",
|
||||
chip->label, chip->ngpio);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -960,7 +960,6 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
|
||||
unsigned long flags;
|
||||
|
||||
/*
|
||||
* While they may not wake up when the TLMM is powered off,
|
||||
@ -971,12 +970,8 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
|
||||
if (d->parent_data)
|
||||
irq_chip_set_wake_parent(d, on);
|
||||
|
||||
raw_spin_lock_irqsave(&pctrl->lock, flags);
|
||||
|
||||
irq_set_irq_wake(pctrl->irq, on);
|
||||
|
||||
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -589,7 +589,7 @@ static const char * const blsp_uart5_groups[] = {
|
||||
static const char * const qdss_traceclk_a_groups[] = {
|
||||
"gpio46",
|
||||
};
|
||||
const char * const m_voc_groups[] = {
|
||||
static const char * const m_voc_groups[] = {
|
||||
"gpio123", "gpio124",
|
||||
};
|
||||
static const char * const blsp_i2c5_groups[] = {
|
||||
|
@ -456,14 +456,18 @@ enum sc7180_functions {
|
||||
msm_mux_qspi_data,
|
||||
msm_mux_qup00,
|
||||
msm_mux_qup01,
|
||||
msm_mux_qup02,
|
||||
msm_mux_qup02_i2c,
|
||||
msm_mux_qup02_uart,
|
||||
msm_mux_qup03,
|
||||
msm_mux_qup04,
|
||||
msm_mux_qup04_i2c,
|
||||
msm_mux_qup04_uart,
|
||||
msm_mux_qup05,
|
||||
msm_mux_qup10,
|
||||
msm_mux_qup11,
|
||||
msm_mux_qup11_i2c,
|
||||
msm_mux_qup11_uart,
|
||||
msm_mux_qup12,
|
||||
msm_mux_qup13,
|
||||
msm_mux_qup13_i2c,
|
||||
msm_mux_qup13_uart,
|
||||
msm_mux_qup14,
|
||||
msm_mux_qup15,
|
||||
msm_mux_sdc1_tb,
|
||||
@ -543,7 +547,10 @@ static const char * const sdc1_tb_groups[] = {
|
||||
static const char * const sdc2_tb_groups[] = {
|
||||
"gpio5",
|
||||
};
|
||||
static const char * const qup11_groups[] = {
|
||||
static const char * const qup11_i2c_groups[] = {
|
||||
"gpio6", "gpio7",
|
||||
};
|
||||
static const char * const qup11_uart_groups[] = {
|
||||
"gpio6", "gpio7",
|
||||
};
|
||||
static const char * const ddr_bist_groups[] = {
|
||||
@ -593,7 +600,10 @@ static const char * const qdss_groups[] = {
|
||||
static const char * const pll_reset_groups[] = {
|
||||
"gpio14",
|
||||
};
|
||||
static const char * const qup02_groups[] = {
|
||||
static const char * const qup02_i2c_groups[] = {
|
||||
"gpio15", "gpio16",
|
||||
};
|
||||
static const char * const qup02_uart_groups[] = {
|
||||
"gpio15", "gpio16",
|
||||
};
|
||||
static const char * const cci_i2c_groups[] = {
|
||||
@ -698,7 +708,10 @@ static const char * const wlan1_adc1_groups[] = {
|
||||
static const char * const atest_usb13_groups[] = {
|
||||
"gpio44",
|
||||
};
|
||||
static const char * const qup13_groups[] = {
|
||||
static const char * const qup13_i2c_groups[] = {
|
||||
"gpio46", "gpio47",
|
||||
};
|
||||
static const char * const qup13_uart_groups[] = {
|
||||
"gpio46", "gpio47",
|
||||
};
|
||||
static const char * const gcc_gp1_groups[] = {
|
||||
@ -848,7 +861,10 @@ static const char * const usb_phy_groups[] = {
|
||||
static const char * const mss_lte_groups[] = {
|
||||
"gpio108", "gpio109",
|
||||
};
|
||||
static const char * const qup04_groups[] = {
|
||||
static const char * const qup04_i2c_groups[] = {
|
||||
"gpio115", "gpio116",
|
||||
};
|
||||
static const char * const qup04_uart_groups[] = {
|
||||
"gpio115", "gpio116",
|
||||
};
|
||||
|
||||
@ -929,14 +945,18 @@ static const struct msm_function sc7180_functions[] = {
|
||||
FUNCTION(qspi_data),
|
||||
FUNCTION(qup00),
|
||||
FUNCTION(qup01),
|
||||
FUNCTION(qup02),
|
||||
FUNCTION(qup02_i2c),
|
||||
FUNCTION(qup02_uart),
|
||||
FUNCTION(qup03),
|
||||
FUNCTION(qup04),
|
||||
FUNCTION(qup04_i2c),
|
||||
FUNCTION(qup04_uart),
|
||||
FUNCTION(qup05),
|
||||
FUNCTION(qup10),
|
||||
FUNCTION(qup11),
|
||||
FUNCTION(qup11_i2c),
|
||||
FUNCTION(qup11_uart),
|
||||
FUNCTION(qup12),
|
||||
FUNCTION(qup13),
|
||||
FUNCTION(qup13_i2c),
|
||||
FUNCTION(qup13_uart),
|
||||
FUNCTION(qup14),
|
||||
FUNCTION(qup15),
|
||||
FUNCTION(sdc1_tb),
|
||||
@ -976,8 +996,8 @@ static const struct msm_pingroup sc7180_groups[] = {
|
||||
[3] = PINGROUP(3, SOUTH, qup01, sp_cmu, dbg_out, qdss_cti, _, _, _, _, _),
|
||||
[4] = PINGROUP(4, NORTH, sdc1_tb, _, qdss_cti, _, _, _, _, _, _),
|
||||
[5] = PINGROUP(5, NORTH, sdc2_tb, _, _, _, _, _, _, _, _),
|
||||
[6] = PINGROUP(6, NORTH, qup11, qup11, _, _, _, _, _, _, _),
|
||||
[7] = PINGROUP(7, NORTH, qup11, qup11, ddr_bist, _, _, _, _, _, _),
|
||||
[6] = PINGROUP(6, NORTH, qup11_i2c, qup11_uart, _, _, _, _, _, _, _),
|
||||
[7] = PINGROUP(7, NORTH, qup11_i2c, qup11_uart, ddr_bist, _, _, _, _, _, _),
|
||||
[8] = PINGROUP(8, NORTH, gp_pdm1, ddr_bist, _, phase_flag, qdss_cti, _, _, _, _),
|
||||
[9] = PINGROUP(9, NORTH, ddr_bist, _, phase_flag, qdss_cti, _, _, _, _, _),
|
||||
[10] = PINGROUP(10, NORTH, mdp_vsync, ddr_bist, _, _, _, _, _, _, _),
|
||||
@ -985,8 +1005,8 @@ static const struct msm_pingroup sc7180_groups[] = {
|
||||
[12] = PINGROUP(12, SOUTH, mdp_vsync, m_voc, qup01, _, phase_flag, wlan2_adc0, atest_usb10, ddr_pxi3, _),
|
||||
[13] = PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, qdss, _, _, _, _, _, _),
|
||||
[14] = PINGROUP(14, SOUTH, cam_mclk, pll_reset, qdss, _, _, _, _, _, _),
|
||||
[15] = PINGROUP(15, SOUTH, cam_mclk, qup02, qup02, qdss, _, _, _, _, _),
|
||||
[16] = PINGROUP(16, SOUTH, cam_mclk, qup02, qup02, qdss, _, _, _, _, _),
|
||||
[15] = PINGROUP(15, SOUTH, cam_mclk, qup02_i2c, qup02_uart, qdss, _, _, _, _, _),
|
||||
[16] = PINGROUP(16, SOUTH, cam_mclk, qup02_i2c, qup02_uart, qdss, _, _, _, _, _),
|
||||
[17] = PINGROUP(17, SOUTH, cci_i2c, _, phase_flag, qdss, _, wlan1_adc0, atest_usb12, ddr_pxi1, atest_char),
|
||||
[18] = PINGROUP(18, SOUTH, cci_i2c, agera_pll, _, phase_flag, qdss, vsense_trigger, ddr_pxi0, atest_char3, _),
|
||||
[19] = PINGROUP(19, SOUTH, cci_i2c, _, phase_flag, qdss, atest_char2, _, _, _, _),
|
||||
@ -1016,8 +1036,8 @@ static const struct msm_pingroup sc7180_groups[] = {
|
||||
[43] = PINGROUP(43, NORTH, qup12, _, _, _, _, _, _, _, _),
|
||||
[44] = PINGROUP(44, NORTH, qup12, _, phase_flag, qdss_cti, wlan1_adc1, atest_usb13, ddr_pxi1, _, _),
|
||||
[45] = PINGROUP(45, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _),
|
||||
[46] = PINGROUP(46, NORTH, qup13, qup13, _, _, _, _, _, _, _),
|
||||
[47] = PINGROUP(47, NORTH, qup13, qup13, _, _, _, _, _, _, _),
|
||||
[46] = PINGROUP(46, NORTH, qup13_i2c, qup13_uart, _, _, _, _, _, _, _),
|
||||
[47] = PINGROUP(47, NORTH, qup13_i2c, qup13_uart, _, _, _, _, _, _, _),
|
||||
[48] = PINGROUP(48, NORTH, gcc_gp1, _, _, _, _, _, _, _, _),
|
||||
[49] = PINGROUP(49, WEST, mi2s_1, btfm_slimbus, _, _, _, _, _, _, _),
|
||||
[50] = PINGROUP(50, WEST, mi2s_1, btfm_slimbus, gp_pdm1, _, _, _, _, _, _),
|
||||
@ -1085,8 +1105,8 @@ static const struct msm_pingroup sc7180_groups[] = {
|
||||
[112] = PINGROUP(112, NORTH, _, _, _, _, _, _, _, _, _),
|
||||
[113] = PINGROUP(113, NORTH, _, _, _, _, _, _, _, _, _),
|
||||
[114] = PINGROUP(114, NORTH, _, _, _, _, _, _, _, _, _),
|
||||
[115] = PINGROUP(115, WEST, qup04, qup04, _, _, _, _, _, _, _),
|
||||
[116] = PINGROUP(116, WEST, qup04, qup04, _, _, _, _, _, _, _),
|
||||
[115] = PINGROUP(115, WEST, qup04_i2c, qup04_uart, _, _, _, _, _, _, _),
|
||||
[116] = PINGROUP(116, WEST, qup04_i2c, qup04_uart, _, _, _, _, _, _, _),
|
||||
[117] = PINGROUP(117, WEST, dp_hot, _, _, _, _, _, _, _, _),
|
||||
[118] = PINGROUP(118, WEST, _, _, _, _, _, _, _, _, _),
|
||||
[119] = UFS_RESET(ufs_reset, 0x7f000),
|
||||
@ -1099,6 +1119,22 @@ static const struct msm_pingroup sc7180_groups[] = {
|
||||
[126] = SDC_QDSD_PINGROUP(sdc2_data, 0x7b000, 9, 0),
|
||||
};
|
||||
|
||||
static const struct msm_gpio_wakeirq_map sc7180_pdc_map[] = {
|
||||
{0, 40}, {3, 50}, {4, 42}, {5, 70}, {6, 41}, {9, 35},
|
||||
{10, 80}, {11, 51}, {16, 20}, {21, 55}, {22, 90}, {23, 21},
|
||||
{24, 61}, {26, 52}, {28, 36}, {30, 100}, {31, 33}, {32, 81},
|
||||
{33, 62}, {34, 43}, {36, 91}, {37, 53}, {38, 63}, {39, 72},
|
||||
{41, 101}, {42, 7}, {43, 34}, {45, 73}, {47, 82}, {49, 17},
|
||||
{52, 109}, {53, 102}, {55, 92}, {56, 56}, {57, 57}, {58, 83},
|
||||
{59, 37}, {62, 110}, {63, 111}, {64, 74}, {65, 44}, {66, 93},
|
||||
{67, 58}, {68, 112}, {69, 32}, {70, 54}, {72, 59}, {73, 64},
|
||||
{74, 71}, {78, 31}, {82, 30}, {85, 103}, {86, 38}, {87, 39},
|
||||
{88, 45}, {89, 46}, {90, 47}, {91, 48}, {92, 60}, {93, 49},
|
||||
{94, 84}, {95, 94}, {98, 65}, {101, 66}, {104, 67}, {109, 104},
|
||||
{110, 68}, {113, 69}, {114, 113}, {115, 108}, {116, 121},
|
||||
{117, 114}, {118, 119},
|
||||
};
|
||||
|
||||
static const struct msm_pinctrl_soc_data sc7180_pinctrl = {
|
||||
.pins = sc7180_pins,
|
||||
.npins = ARRAY_SIZE(sc7180_pins),
|
||||
@ -1109,6 +1145,8 @@ static const struct msm_pinctrl_soc_data sc7180_pinctrl = {
|
||||
.ngpios = 120,
|
||||
.tiles = sc7180_tiles,
|
||||
.ntiles = ARRAY_SIZE(sc7180_tiles),
|
||||
.wakeirq_map = sc7180_pdc_map,
|
||||
.nwakeirq_map = ARRAY_SIZE(sc7180_pdc_map),
|
||||
};
|
||||
|
||||
static int sc7180_pinctrl_probe(struct platform_device *pdev)
|
||||
|
@ -439,7 +439,7 @@ static const struct pinconf_ops pm8xxx_pinconf_ops = {
|
||||
.pin_config_group_set = pm8xxx_pin_config_set,
|
||||
};
|
||||
|
||||
static struct pinctrl_desc pm8xxx_pinctrl_desc = {
|
||||
static const struct pinctrl_desc pm8xxx_pinctrl_desc = {
|
||||
.name = "pm8xxx_gpio",
|
||||
.pctlops = &pm8xxx_pinctrl_ops,
|
||||
.pmxops = &pm8xxx_pinmux_ops,
|
||||
|
@ -430,7 +430,7 @@ static const struct pinconf_ops pm8xxx_pinconf_ops = {
|
||||
.pin_config_group_set = pm8xxx_pin_config_set,
|
||||
};
|
||||
|
||||
static struct pinctrl_desc pm8xxx_pinctrl_desc = {
|
||||
static const struct pinctrl_desc pm8xxx_pinctrl_desc = {
|
||||
.name = "pm8xxx_mpp",
|
||||
.pctlops = &pm8xxx_pinctrl_ops,
|
||||
.pmxops = &pm8xxx_pinmux_ops,
|
||||
|
@ -4,30 +4,34 @@
|
||||
#
|
||||
config PINCTRL_SAMSUNG
|
||||
bool
|
||||
depends on OF_GPIO
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
|
||||
config PINCTRL_EXYNOS
|
||||
bool "Pinctrl driver data for Samsung EXYNOS SoCs"
|
||||
depends on OF && GPIOLIB && (ARCH_EXYNOS || ARCH_S5PV210)
|
||||
bool "Pinctrl common driver part for Samsung Exynos SoCs"
|
||||
depends on OF_GPIO
|
||||
depends on ARCH_EXYNOS || ARCH_S5PV210 || COMPILE_TEST
|
||||
select PINCTRL_SAMSUNG
|
||||
select PINCTRL_EXYNOS_ARM if ARM && (ARCH_EXYNOS || ARCH_S5PV210)
|
||||
select PINCTRL_EXYNOS_ARM64 if ARM64 && ARCH_EXYNOS
|
||||
|
||||
config PINCTRL_EXYNOS_ARM
|
||||
bool "ARMv7-specific pinctrl driver data for Exynos" if COMPILE_TEST
|
||||
bool "ARMv7-specific pinctrl driver for Samsung Exynos SoCs" if COMPILE_TEST
|
||||
depends on PINCTRL_EXYNOS
|
||||
|
||||
config PINCTRL_EXYNOS_ARM64
|
||||
bool "ARMv8-specific pinctrl driver data for Exynos" if COMPILE_TEST
|
||||
bool "ARMv8-specific pinctrl driver for Samsung Exynos SoCs" if COMPILE_TEST
|
||||
depends on PINCTRL_EXYNOS
|
||||
|
||||
config PINCTRL_S3C24XX
|
||||
bool "Samsung S3C24XX SoC pinctrl driver"
|
||||
depends on ARCH_S3C24XX && OF
|
||||
depends on OF_GPIO
|
||||
depends on ARCH_S3C24XX || COMPILE_TEST
|
||||
select PINCTRL_SAMSUNG
|
||||
|
||||
config PINCTRL_S3C64XX
|
||||
bool "Samsung S3C64XX SoC pinctrl driver"
|
||||
depends on ARCH_S3C64XX
|
||||
depends on OF_GPIO
|
||||
depends on ARCH_S3C64XX || COMPILE_TEST
|
||||
select PINCTRL_SAMSUNG
|
||||
|
@ -26,8 +26,9 @@ config PINCTRL_SH_PFC
|
||||
select PINCTRL_PFC_R8A7792 if ARCH_R8A7792
|
||||
select PINCTRL_PFC_R8A7793 if ARCH_R8A7793
|
||||
select PINCTRL_PFC_R8A7794 if ARCH_R8A7794
|
||||
select PINCTRL_PFC_R8A7795 if ARCH_R8A7795
|
||||
select PINCTRL_PFC_R8A77960 if ARCH_R8A77960 || ARCH_R8A7796
|
||||
select PINCTRL_PFC_R8A77950 if ARCH_R8A77950 || ARCH_R8A7795
|
||||
select PINCTRL_PFC_R8A77951 if ARCH_R8A77951 || ARCH_R8A7795
|
||||
select PINCTRL_PFC_R8A77960 if ARCH_R8A77960
|
||||
select PINCTRL_PFC_R8A77961 if ARCH_R8A77961
|
||||
select PINCTRL_PFC_R8A77965 if ARCH_R8A77965
|
||||
select PINCTRL_PFC_R8A77970 if ARCH_R8A77970
|
||||
@ -115,8 +116,11 @@ config PINCTRL_PFC_R8A7793
|
||||
config PINCTRL_PFC_R8A7794
|
||||
bool "R-Car E2 pin control support" if COMPILE_TEST
|
||||
|
||||
config PINCTRL_PFC_R8A7795
|
||||
bool "R-Car H3 pin control support" if COMPILE_TEST
|
||||
config PINCTRL_PFC_R8A77950
|
||||
bool "R-Car H3 ES1.x pin control support" if COMPILE_TEST
|
||||
|
||||
config PINCTRL_PFC_R8A77951
|
||||
bool "R-Car H3 ES2.0+ pin control support" if COMPILE_TEST
|
||||
|
||||
config PINCTRL_PFC_R8A77960
|
||||
bool "R-Car M3-W pin control support" if COMPILE_TEST
|
||||
|
@ -18,8 +18,8 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77950) += pfc-r8a77950.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77951) += pfc-r8a77951.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77960) += pfc-r8a7796.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77961) += pfc-r8a7796.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
|
||||
|
@ -23,6 +23,7 @@
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/psci.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/sys_soc.h>
|
||||
|
||||
#include "core.h"
|
||||
|
||||
@ -568,18 +569,18 @@ static const struct of_device_id sh_pfc_of_table[] = {
|
||||
.data = &r8a7794_pinmux_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7795
|
||||
/* Both r8a7795 entries must be present to make sanity checks work */
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77950
|
||||
{
|
||||
.compatible = "renesas,pfc-r8a7795",
|
||||
.data = &r8a7795_pinmux_info,
|
||||
.data = &r8a77950_pinmux_info,
|
||||
},
|
||||
#ifdef DEBUG
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77951
|
||||
{
|
||||
/* For sanity checks only (nothing matches against this) */
|
||||
.compatible = "renesas,pfc-r8a77950", /* R-Car H3 ES1.0 */
|
||||
.data = &r8a7795es1_pinmux_info,
|
||||
.compatible = "renesas,pfc-r8a7795",
|
||||
.data = &r8a77951_pinmux_info,
|
||||
},
|
||||
#endif /* DEBUG */
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77960
|
||||
{
|
||||
@ -886,19 +887,49 @@ static void __init sh_pfc_check_driver(const struct platform_driver *pdrv)
|
||||
static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}
|
||||
#endif /* !DEBUG */
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static const void *sh_pfc_quirk_match(void)
|
||||
{
|
||||
#if defined(CONFIG_PINCTRL_PFC_R8A77950) || \
|
||||
defined(CONFIG_PINCTRL_PFC_R8A77951)
|
||||
const struct soc_device_attribute *match;
|
||||
static const struct soc_device_attribute quirks[] = {
|
||||
{
|
||||
.soc_id = "r8a7795", .revision = "ES1.*",
|
||||
.data = &r8a77950_pinmux_info,
|
||||
},
|
||||
{
|
||||
.soc_id = "r8a7795",
|
||||
.data = &r8a77951_pinmux_info,
|
||||
},
|
||||
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
match = soc_device_match(quirks);
|
||||
if (match)
|
||||
return match->data ?: ERR_PTR(-ENODEV);
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77950 || CONFIG_PINCTRL_PFC_R8A77951 */
|
||||
|
||||
return NULL;
|
||||
}
|
||||
#endif /* CONFIG_OF */
|
||||
|
||||
static int sh_pfc_probe(struct platform_device *pdev)
|
||||
{
|
||||
#ifdef CONFIG_OF
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
#endif
|
||||
const struct sh_pfc_soc_info *info;
|
||||
struct sh_pfc *pfc;
|
||||
int ret;
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
if (np)
|
||||
info = of_device_get_match_data(&pdev->dev);
|
||||
else
|
||||
if (pdev->dev.of_node) {
|
||||
info = sh_pfc_quirk_match();
|
||||
if (IS_ERR(info))
|
||||
return PTR_ERR(info);
|
||||
|
||||
if (!info)
|
||||
info = of_device_get_match_data(&pdev->dev);
|
||||
} else
|
||||
#endif
|
||||
info = (const void *)platform_get_device_id(pdev)->driver_data;
|
||||
|
||||
|
@ -386,12 +386,11 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
|
||||
}
|
||||
|
||||
/* Register the function GPIOs chip. */
|
||||
if (pfc->info->nr_func_gpios == 0)
|
||||
return 0;
|
||||
|
||||
chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
|
||||
if (IS_ERR(chip))
|
||||
return PTR_ERR(chip);
|
||||
if (pfc->info->nr_func_gpios) {
|
||||
chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
|
||||
if (IS_ERR(chip))
|
||||
return PTR_ERR(chip);
|
||||
}
|
||||
#endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
|
||||
|
||||
return 0;
|
||||
|
@ -2305,7 +2305,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
FN_ATAG0_A, 0, FN_REMOCON_B, 0,
|
||||
/* IP0_11_8 [4] */
|
||||
FN_SD1_DAT2_A, FN_MMC_D2, 0, FN_BS,
|
||||
FN_ATADIR0_A, 0, FN_SDSELF_B, 0,
|
||||
FN_ATADIR0_A, 0, FN_SDSELF_A, 0,
|
||||
FN_PWM4_B, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
/* IP0_7_5 [3] */
|
||||
@ -2349,7 +2349,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
FN_TS_SDAT0_A, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
/* IP1_10_8 [3] */
|
||||
FN_SD1_CLK_B, FN_MMC_D6, 0, FN_A24,
|
||||
FN_SD1_CD_A, FN_MMC_D6, 0, FN_A24,
|
||||
FN_DREQ1_A, 0, FN_HRX0_B, FN_TS_SPSYNC0_A,
|
||||
/* IP1_7_5 [3] */
|
||||
FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A,
|
||||
|
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* R8A7795 ES1.x processor support - PFC hardware block.
|
||||
* R8A77950 processor support - PFC hardware block.
|
||||
*
|
||||
* Copyright (C) 2015-2017 Renesas Electronics Corporation
|
||||
*/
|
||||
@ -5562,8 +5562,8 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
|
||||
u32 *pocctrl)
|
||||
static int r8a77950_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
|
||||
u32 *pocctrl)
|
||||
{
|
||||
int bit = -EINVAL;
|
||||
|
||||
@ -5820,8 +5820,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc,
|
||||
unsigned int pin)
|
||||
static unsigned int r8a77950_pinmux_get_bias(struct sh_pfc *pfc,
|
||||
unsigned int pin)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
unsigned int bit;
|
||||
@ -5838,8 +5838,8 @@ static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc,
|
||||
return PIN_CONFIG_BIAS_PULL_DOWN;
|
||||
}
|
||||
|
||||
static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias)
|
||||
static void r8a77950_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
u32 enable, updown;
|
||||
@ -5861,15 +5861,15 @@ static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
sh_pfc_write(pfc, reg->puen, enable);
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a7795es1_pinmux_ops = {
|
||||
.pin_to_pocctrl = r8a7795es1_pin_to_pocctrl,
|
||||
.get_bias = r8a7795es1_pinmux_get_bias,
|
||||
.set_bias = r8a7795es1_pinmux_set_bias,
|
||||
static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = {
|
||||
.pin_to_pocctrl = r8a77950_pin_to_pocctrl,
|
||||
.get_bias = r8a77950_pinmux_get_bias,
|
||||
.set_bias = r8a77950_pinmux_set_bias,
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info r8a7795es1_pinmux_info = {
|
||||
const struct sh_pfc_soc_info r8a77950_pinmux_info = {
|
||||
.name = "r8a77950_pfc",
|
||||
.ops = &r8a7795es1_pinmux_ops,
|
||||
.ops = &r8a77950_pinmux_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* R8A7795 ES2.0+ processor support - PFC hardware block.
|
||||
* R8A77951 processor support - PFC hardware block.
|
||||
*
|
||||
* Copyright (C) 2015-2019 Renesas Electronics Corporation
|
||||
*/
|
||||
@ -5915,7 +5915,8 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
|
||||
static int r8a77951_pin_to_pocctrl(struct sh_pfc *pfc,
|
||||
unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = -EINVAL;
|
||||
|
||||
@ -6172,8 +6173,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
|
||||
unsigned int pin)
|
||||
static unsigned int r8a77951_pinmux_get_bias(struct sh_pfc *pfc,
|
||||
unsigned int pin)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
unsigned int bit;
|
||||
@ -6190,8 +6191,8 @@ static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
|
||||
return PIN_CONFIG_BIAS_PULL_DOWN;
|
||||
}
|
||||
|
||||
static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias)
|
||||
static void r8a77951_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
u32 enable, updown;
|
||||
@ -6213,29 +6214,15 @@ static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
sh_pfc_write(pfc, reg->puen, enable);
|
||||
}
|
||||
|
||||
static const struct soc_device_attribute r8a7795es1[] = {
|
||||
{ .soc_id = "r8a7795", .revision = "ES1.*" },
|
||||
{ /* sentinel */ }
|
||||
static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = {
|
||||
.pin_to_pocctrl = r8a77951_pin_to_pocctrl,
|
||||
.get_bias = r8a77951_pinmux_get_bias,
|
||||
.set_bias = r8a77951_pinmux_set_bias,
|
||||
};
|
||||
|
||||
static int r8a7795_pinmux_init(struct sh_pfc *pfc)
|
||||
{
|
||||
if (soc_device_match(r8a7795es1))
|
||||
pfc->info = &r8a7795es1_pinmux_info;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
|
||||
.init = r8a7795_pinmux_init,
|
||||
.pin_to_pocctrl = r8a7795_pin_to_pocctrl,
|
||||
.get_bias = r8a7795_pinmux_get_bias,
|
||||
.set_bias = r8a7795_pinmux_set_bias,
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info r8a7795_pinmux_info = {
|
||||
const struct sh_pfc_soc_info r8a77951_pinmux_info = {
|
||||
.name = "r8a77951_pfc",
|
||||
.ops = &r8a7795_pinmux_ops,
|
||||
.ops = &r8a77951_pinmux_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
@ -5998,7 +5998,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
||||
{ PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
|
||||
{ PIN_DU_DOTCLKIN3, 28, 2 }, /* DU_DOTCLKIN3 */
|
||||
{ PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
|
||||
{ PIN_FSCLKST, 20, 2 }, /* FSCLKST */
|
||||
{ PIN_TMS, 4, 2 }, /* TMS */
|
||||
} },
|
||||
@ -6254,8 +6254,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
[31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
|
||||
[ 0] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
|
||||
[ 1] = SH_PFC_PIN_NONE,
|
||||
[ 0] = SH_PFC_PIN_NONE,
|
||||
[ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
|
||||
[ 2] = PIN_FSCLKST, /* FSCLKST */
|
||||
[ 3] = PIN_EXTALR, /* EXTALR*/
|
||||
[ 4] = PIN_TRST_N, /* TRST# */
|
||||
|
@ -497,17 +497,15 @@ enum {
|
||||
SD_WP_MARK, SD_CLK_MARK, SD_CMD_MARK,
|
||||
CRX0_MARK, CRX1_MARK,
|
||||
CTX0_MARK, CTX1_MARK,
|
||||
CRX0_CRX1_MARK, CTX0_CTX1_MARK,
|
||||
|
||||
PWM1A_MARK, PWM1B_MARK, PWM1C_MARK, PWM1D_MARK,
|
||||
PWM1E_MARK, PWM1F_MARK, PWM1G_MARK, PWM1H_MARK,
|
||||
PWM2A_MARK, PWM2B_MARK, PWM2C_MARK, PWM2D_MARK,
|
||||
PWM2E_MARK, PWM2F_MARK, PWM2G_MARK, PWM2H_MARK,
|
||||
IERXD_MARK, IETXD_MARK,
|
||||
CRX0_CRX1_MARK,
|
||||
WDTOVF_MARK,
|
||||
|
||||
CRX0X1_MARK,
|
||||
|
||||
/* DMAC */
|
||||
TEND0_MARK, DACK0_MARK, DREQ0_MARK,
|
||||
TEND1_MARK, DACK1_MARK, DREQ1_MARK,
|
||||
@ -995,12 +993,12 @@ static const u16 pinmux_data[] = {
|
||||
|
||||
PINMUX_DATA(PJ3_DATA, PJ3MD_00),
|
||||
PINMUX_DATA(CRX1_MARK, PJ3MD_01),
|
||||
PINMUX_DATA(CRX0X1_MARK, PJ3MD_10),
|
||||
PINMUX_DATA(CRX0_CRX1_MARK, PJ3MD_10),
|
||||
PINMUX_DATA(IRQ1_PJ_MARK, PJ3MD_11),
|
||||
|
||||
PINMUX_DATA(PJ2_DATA, PJ2MD_000),
|
||||
PINMUX_DATA(CTX1_MARK, PJ2MD_001),
|
||||
PINMUX_DATA(CRX0_CRX1_MARK, PJ2MD_010),
|
||||
PINMUX_DATA(CTX0_CTX1_MARK, PJ2MD_010),
|
||||
PINMUX_DATA(CS2_MARK, PJ2MD_011),
|
||||
PINMUX_DATA(SCK0_MARK, PJ2MD_100),
|
||||
PINMUX_DATA(LCD_M_DISP_MARK, PJ2MD_101),
|
||||
@ -1245,6 +1243,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
|
||||
GPIO_FN(CTX1),
|
||||
GPIO_FN(CRX1),
|
||||
GPIO_FN(CTX0),
|
||||
GPIO_FN(CTX0_CTX1),
|
||||
GPIO_FN(CRX0),
|
||||
GPIO_FN(CRX0_CRX1),
|
||||
|
||||
@ -2020,18 +2019,18 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
|
||||
{ PINMUX_CFG_REG("PKIOR0", 0xfffe3932, 16, 1, GROUP(
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PJ11_IN, PJ11_OUT,
|
||||
PJ10_IN, PJ10_OUT,
|
||||
PJ9_IN, PJ9_OUT,
|
||||
PJ8_IN, PJ8_OUT,
|
||||
PJ7_IN, PJ7_OUT,
|
||||
PJ6_IN, PJ6_OUT,
|
||||
PJ5_IN, PJ5_OUT,
|
||||
PJ4_IN, PJ4_OUT,
|
||||
PJ3_IN, PJ3_OUT,
|
||||
PJ2_IN, PJ2_OUT,
|
||||
PJ1_IN, PJ1_OUT,
|
||||
PJ0_IN, PJ0_OUT ))
|
||||
PK11_IN, PK11_OUT,
|
||||
PK10_IN, PK10_OUT,
|
||||
PK9_IN, PK9_OUT,
|
||||
PK8_IN, PK8_OUT,
|
||||
PK7_IN, PK7_OUT,
|
||||
PK6_IN, PK6_OUT,
|
||||
PK5_IN, PK5_OUT,
|
||||
PK4_IN, PK4_OUT,
|
||||
PK3_IN, PK3_OUT,
|
||||
PK2_IN, PK2_OUT,
|
||||
PK1_IN, PK1_OUT,
|
||||
PK0_IN, PK0_OUT ))
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
@ -737,13 +737,12 @@ enum {
|
||||
CRX0_MARK, CTX0_MARK,
|
||||
CRX1_MARK, CTX1_MARK,
|
||||
CRX2_MARK, CTX2_MARK,
|
||||
CRX0_CRX1_MARK,
|
||||
CRX0_CRX1_CRX2_MARK,
|
||||
CTX0CTX1CTX2_MARK,
|
||||
CRX0_CRX1_MARK, CTX0_CTX1_MARK,
|
||||
CRX0_CRX1_CRX2_MARK, CTX0_CTX1_CTX2_MARK,
|
||||
CRX1_PJ22_MARK, CTX1_PJ23_MARK,
|
||||
CRX2_PJ20_MARK, CTX2_PJ21_MARK,
|
||||
CRX0CRX1_PJ22_MARK,
|
||||
CRX0CRX1CRX2_PJ20_MARK,
|
||||
CRX0_CRX1_PJ22_MARK, CTX0_CTX1_PJ23_MARK,
|
||||
CRX0_CRX1_CRX2_PJ20_MARK, CTX0_CTX1_CTX2_PJ21_MARK,
|
||||
|
||||
/* VDC */
|
||||
DV_CLK_MARK,
|
||||
@ -821,6 +820,7 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_DATA(CS3_MARK, PC8MD_001),
|
||||
PINMUX_DATA(TXD7_MARK, PC8MD_010),
|
||||
PINMUX_DATA(CTX1_MARK, PC8MD_011),
|
||||
PINMUX_DATA(CTX0_CTX1_MARK, PC8MD_100),
|
||||
|
||||
PINMUX_DATA(PC7_DATA, PC7MD_000),
|
||||
PINMUX_DATA(CKE_MARK, PC7MD_001),
|
||||
@ -833,11 +833,12 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_DATA(CAS_MARK, PC6MD_001),
|
||||
PINMUX_DATA(SCK7_MARK, PC6MD_010),
|
||||
PINMUX_DATA(CTX0_MARK, PC6MD_011),
|
||||
PINMUX_DATA(CTX0_CTX1_CTX2_MARK, PC6MD_100),
|
||||
|
||||
PINMUX_DATA(PC5_DATA, PC5MD_000),
|
||||
PINMUX_DATA(RAS_MARK, PC5MD_001),
|
||||
PINMUX_DATA(CRX0_MARK, PC5MD_011),
|
||||
PINMUX_DATA(CTX0CTX1CTX2_MARK, PC5MD_100),
|
||||
PINMUX_DATA(CTX0_CTX1_CTX2_MARK, PC5MD_100),
|
||||
PINMUX_DATA(IRQ0_PC_MARK, PC5MD_101),
|
||||
|
||||
PINMUX_DATA(PC4_DATA, PC4MD_00),
|
||||
@ -1289,30 +1290,32 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_DATA(LCD_DATA23_PJ23_MARK, PJ23MD_010),
|
||||
PINMUX_DATA(LCD_TCON6_MARK, PJ23MD_011),
|
||||
PINMUX_DATA(IRQ3_PJ_MARK, PJ23MD_100),
|
||||
PINMUX_DATA(CTX1_MARK, PJ23MD_101),
|
||||
PINMUX_DATA(CTX1_PJ23_MARK, PJ23MD_101),
|
||||
PINMUX_DATA(CTX0_CTX1_PJ23_MARK, PJ23MD_110),
|
||||
|
||||
PINMUX_DATA(PJ22_DATA, PJ22MD_000),
|
||||
PINMUX_DATA(DV_DATA22_MARK, PJ22MD_001),
|
||||
PINMUX_DATA(LCD_DATA22_PJ22_MARK, PJ22MD_010),
|
||||
PINMUX_DATA(LCD_TCON5_MARK, PJ22MD_011),
|
||||
PINMUX_DATA(IRQ2_PJ_MARK, PJ22MD_100),
|
||||
PINMUX_DATA(CRX1_MARK, PJ22MD_101),
|
||||
PINMUX_DATA(CRX0_CRX1_MARK, PJ22MD_110),
|
||||
PINMUX_DATA(CRX1_PJ22_MARK, PJ22MD_101),
|
||||
PINMUX_DATA(CRX0_CRX1_PJ22_MARK, PJ22MD_110),
|
||||
|
||||
PINMUX_DATA(PJ21_DATA, PJ21MD_000),
|
||||
PINMUX_DATA(DV_DATA21_MARK, PJ21MD_001),
|
||||
PINMUX_DATA(LCD_DATA21_PJ21_MARK, PJ21MD_010),
|
||||
PINMUX_DATA(LCD_TCON4_MARK, PJ21MD_011),
|
||||
PINMUX_DATA(IRQ1_PJ_MARK, PJ21MD_100),
|
||||
PINMUX_DATA(CTX2_MARK, PJ21MD_101),
|
||||
PINMUX_DATA(CTX2_PJ21_MARK, PJ21MD_101),
|
||||
PINMUX_DATA(CTX0_CTX1_CTX2_PJ21_MARK, PJ21MD_110),
|
||||
|
||||
PINMUX_DATA(PJ20_DATA, PJ20MD_000),
|
||||
PINMUX_DATA(DV_DATA20_MARK, PJ20MD_001),
|
||||
PINMUX_DATA(LCD_DATA20_PJ20_MARK, PJ20MD_010),
|
||||
PINMUX_DATA(LCD_TCON3_MARK, PJ20MD_011),
|
||||
PINMUX_DATA(IRQ0_PJ_MARK, PJ20MD_100),
|
||||
PINMUX_DATA(CRX2_MARK, PJ20MD_101),
|
||||
PINMUX_DATA(CRX0CRX1CRX2_PJ20_MARK, PJ20MD_110),
|
||||
PINMUX_DATA(CRX2_PJ20_MARK, PJ20MD_101),
|
||||
PINMUX_DATA(CRX0_CRX1_CRX2_PJ20_MARK, PJ20MD_110),
|
||||
|
||||
PINMUX_DATA(PJ19_DATA, PJ19MD_000),
|
||||
PINMUX_DATA(DV_DATA19_MARK, PJ19MD_001),
|
||||
@ -1663,12 +1666,24 @@ static const struct pinmux_func pinmux_func_gpios[] = {
|
||||
GPIO_FN(WDTOVF),
|
||||
|
||||
/* CAN */
|
||||
GPIO_FN(CTX2),
|
||||
GPIO_FN(CRX2),
|
||||
GPIO_FN(CTX1),
|
||||
GPIO_FN(CRX1),
|
||||
GPIO_FN(CTX0),
|
||||
GPIO_FN(CRX0),
|
||||
GPIO_FN(CTX0_CTX1),
|
||||
GPIO_FN(CRX0_CRX1),
|
||||
GPIO_FN(CTX0_CTX1_CTX2),
|
||||
GPIO_FN(CRX0_CRX1_CRX2),
|
||||
GPIO_FN(CTX2_PJ21),
|
||||
GPIO_FN(CRX2_PJ20),
|
||||
GPIO_FN(CTX1_PJ23),
|
||||
GPIO_FN(CRX1_PJ22),
|
||||
GPIO_FN(CTX0_CTX1_PJ23),
|
||||
GPIO_FN(CRX0_CRX1_PJ22),
|
||||
GPIO_FN(CTX0_CTX1_CTX2_PJ21),
|
||||
GPIO_FN(CRX0_CRX1_CRX2_PJ20),
|
||||
|
||||
/* DMAC */
|
||||
GPIO_FN(TEND0),
|
||||
|
@ -318,8 +318,8 @@ extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77950_pinmux_info __weak;
|
||||
extern const struct sh_pfc_soc_info r8a77951_pinmux_info __weak;
|
||||
extern const struct sh_pfc_soc_info r8a77960_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77961_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
|
||||
|
@ -1,4 +1,4 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) Maxime Coquelin 2015
|
||||
* Copyright (C) STMicroelectronics 2017
|
||||
|
@ -19,7 +19,6 @@
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
|
||||
#include "pinctrl-sunxi.h"
|
||||
@ -549,7 +548,17 @@ static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = {
|
||||
|
||||
static int sun50i_h5_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
switch (of_irq_count(pdev->dev.of_node)) {
|
||||
int ret;
|
||||
|
||||
ret = platform_irq_count(pdev);
|
||||
if (ret < 0) {
|
||||
if (ret != -EPROBE_DEFER)
|
||||
dev_err(&pdev->dev, "Couldn't determine irq count: %pe\n",
|
||||
ERR_PTR(ret));
|
||||
return ret;
|
||||
}
|
||||
|
||||
switch (ret) {
|
||||
case 2:
|
||||
dev_warn(&pdev->dev,
|
||||
"Your device tree's pinctrl node is broken, which has no IRQ of PG bank routed.\n");
|
||||
|
@ -648,7 +648,7 @@ static int tegra_pinctrl_suspend(struct device *dev)
|
||||
{
|
||||
struct tegra_pmx *pmx = dev_get_drvdata(dev);
|
||||
u32 *backup_regs = pmx->backup_regs;
|
||||
u32 *regs;
|
||||
u32 __iomem *regs;
|
||||
size_t bank_size;
|
||||
unsigned int i, k;
|
||||
|
||||
@ -666,7 +666,7 @@ static int tegra_pinctrl_resume(struct device *dev)
|
||||
{
|
||||
struct tegra_pmx *pmx = dev_get_drvdata(dev);
|
||||
u32 *backup_regs = pmx->backup_regs;
|
||||
u32 *regs;
|
||||
u32 __iomem *regs;
|
||||
size_t bank_size;
|
||||
unsigned int i, k;
|
||||
|
||||
|
@ -582,11 +582,6 @@ int gpiochip_irq_domain_activate(struct irq_domain *domain,
|
||||
void gpiochip_irq_domain_deactivate(struct irq_domain *domain,
|
||||
struct irq_data *data);
|
||||
|
||||
void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
|
||||
struct irq_chip *irqchip,
|
||||
unsigned int parent_irq,
|
||||
irq_flow_handler_t parent_handler);
|
||||
|
||||
void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip,
|
||||
struct irq_chip *irqchip,
|
||||
unsigned int parent_irq);
|
||||
|
@ -153,6 +153,7 @@ struct pinctrl_map {
|
||||
|
||||
extern int pinctrl_register_mappings(const struct pinctrl_map *map,
|
||||
unsigned num_maps);
|
||||
extern void pinctrl_unregister_mappings(const struct pinctrl_map *map);
|
||||
extern void pinctrl_provide_dummies(void);
|
||||
#else
|
||||
|
||||
@ -162,6 +163,10 @@ static inline int pinctrl_register_mappings(const struct pinctrl_map *map,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void pinctrl_unregister_mappings(const struct pinctrl_map *map)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void pinctrl_provide_dummies(void)
|
||||
{
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user