renegade-project/linux-next
2
0
Fork 0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-18 18:23:53 +08:00
Code

Several fixes for:

Browse Source 
- external irq on non-DT boards
 - cpuidle code in some circumstances
 - PMC code in relation with PLLB/PLL_UTMI/USB:
   mainly for SAMA5D3 and AT91SAM9N12
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQEcBAABAgAGBQJRyuyOAAoJEAf03oE53VmQDOgIALT6Ql8reZiaLcB9cuhpPVy1
 vJAx8jxmJy0V1eXiD/Gl00261vb2tw7YJK9gt3zfLP0upqsYWrV5sV7f8UhR73RQ
 rrJSfWfLkPFPBORYyKiHw9kWQUMBczybz9hhv3HbbxdVHmpD7LnaPRWXat71u1u/
 Uh8UpF5d2s3lAE1BBqTr9Ec6n3r7vKqI/0MO2pWnyf11nfNZMI705zG9ehrQZHZx
 v8hovwjWuQ/o06GD45xMJuunEp6IVHl01A2ZRcppuvQD4CtNBXo3AnlNLQ6TK7iz
 9qOVhAiD8/1Td3CXSOOMiInCDBIVOXI/bbkKrAFJcTgGdL1jkAKEN3A1xUxXYVQ=
 =28Xo
 -----END PGP SIGNATURE-----

Merge tag 'at91-fixes' of git://github.com/at91linux/linux-at91 into next/fixes-non-critical

From Nicolas Ferre:

Several fixes for:
- external irq on non-DT boards
- cpuidle code in some circumstances
- PMC code in relation with PLLB/PLL_UTMI/USB:
  mainly for SAMA5D3 and AT91SAM9N12

* tag 'at91-fixes' of git://github.com/at91linux/linux-at91:
  ARM: at91/PMC: use at91_usb_rate() for UTMI PLL
  ARM: at91/PMC: fix at91sam9n12 USB FS init
  ARM: at91/PMC: at91sam9n12 family has a PLLB
  ARM: at91/PMC: sama5d3 family doesn't have a PLLB
  ARM: at91: cpuidle: Fix target_residency
  ARM: at91: fix at91_extern_irq usage for non-dt boards

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2013-06-27 15:03:13 +02:00
commit 6b9a39de73
15 changed files with 53 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm/mach-at91/at91rm9200.c
View File

@ -332,10 +332,6 @@ static void __init at91rm9200_initialize(void)
{
arm_pm_idle = at91rm9200_idle;
arm_pm_restart = at91rm9200_restart;
at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
| (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
| (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
| (1 << AT91RM9200_ID_IRQ6);
/* Initialize GPIO subsystem */
at91_gpio_init(at91rm9200_gpio,
@ -388,6 +384,10 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
AT91_SOC_START(at91rm9200)
.map_io = at91rm9200_map_io,
.default_irq_priority = at91rm9200_default_irq_priority,
.extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
| (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
| (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
| (1 << AT91RM9200_ID_IRQ6),
.ioremap_registers = at91rm9200_ioremap_registers,
.register_clocks = at91rm9200_register_clocks,
.init = at91rm9200_initialize,

4
arch/arm/mach-at91/at91sam9260.c
View File

@ -348,8 +348,6 @@ static void __init at91sam9260_initialize(void)
{
arm_pm_idle = at91sam9_idle;
arm_pm_restart = at91sam9_alt_restart;
at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
| (1 << AT91SAM9260_ID_IRQ2);
/* Register GPIO subsystem */
at91_gpio_init(at91sam9260_gpio, 3);
@ -400,6 +398,8 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
AT91_SOC_START(at91sam9260)
.map_io = at91sam9260_map_io,
.default_irq_priority = at91sam9260_default_irq_priority,
.extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
| (1 << AT91SAM9260_ID_IRQ2),
.ioremap_registers = at91sam9260_ioremap_registers,
.register_clocks = at91sam9260_register_clocks,
.init = at91sam9260_initialize,

4
arch/arm/mach-at91/at91sam9261.c
View File

@ -290,8 +290,6 @@ static void __init at91sam9261_initialize(void)
{
arm_pm_idle = at91sam9_idle;
arm_pm_restart = at91sam9_alt_restart;
at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
| (1 << AT91SAM9261_ID_IRQ2);
/* Register GPIO subsystem */
at91_gpio_init(at91sam9261_gpio, 3);
@ -342,6 +340,8 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
AT91_SOC_START(at91sam9261)
.map_io = at91sam9261_map_io,
.default_irq_priority = at91sam9261_default_irq_priority,
.extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
| (1 << AT91SAM9261_ID_IRQ2),
.ioremap_registers = at91sam9261_ioremap_registers,
.register_clocks = at91sam9261_register_clocks,
.init = at91sam9261_initialize,

2
arch/arm/mach-at91/at91sam9263.c
View File

@ -327,7 +327,6 @@ static void __init at91sam9263_initialize(void)
{
arm_pm_idle = at91sam9_idle;
arm_pm_restart = at91sam9_alt_restart;
at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
/* Register GPIO subsystem */
at91_gpio_init(at91sam9263_gpio, 5);
@ -378,6 +377,7 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
AT91_SOC_START(at91sam9263)
.map_io = at91sam9263_map_io,
.default_irq_priority = at91sam9263_default_irq_priority,
.extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1),
.ioremap_registers = at91sam9263_ioremap_registers,
.register_clocks = at91sam9263_register_clocks,
.init = at91sam9263_initialize,

2
arch/arm/mach-at91/at91sam9g45.c
View File

@ -374,7 +374,6 @@ static void __init at91sam9g45_initialize(void)
{
arm_pm_idle = at91sam9_idle;
arm_pm_restart = at91sam9g45_restart;
at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
/* Register GPIO subsystem */
at91_gpio_init(at91sam9g45_gpio, 5);
@ -425,6 +424,7 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
AT91_SOC_START(at91sam9g45)
.map_io = at91sam9g45_map_io,
.default_irq_priority = at91sam9g45_default_irq_priority,
.extern_irq = (1 << AT91SAM9G45_ID_IRQ0),
.ioremap_registers = at91sam9g45_ioremap_registers,
.register_clocks = at91sam9g45_register_clocks,
.init = at91sam9g45_initialize,

2
arch/arm/mach-at91/at91sam9rl.c
View File

@ -293,7 +293,6 @@ static void __init at91sam9rl_initialize(void)
{
arm_pm_idle = at91sam9_idle;
arm_pm_restart = at91sam9_alt_restart;
at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
/* Register GPIO subsystem */
at91_gpio_init(at91sam9rl_gpio, 4);
@ -344,6 +343,7 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
AT91_SOC_START(at91sam9rl)
.map_io = at91sam9rl_map_io,
.default_irq_priority = at91sam9rl_default_irq_priority,
.extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
.ioremap_registers = at91sam9rl_ioremap_registers,
.register_clocks = at91sam9rl_register_clocks,
.init = at91sam9rl_initialize,

7
arch/arm/mach-at91/at91x40.c
View File

@ -55,8 +55,6 @@ static void at91x40_idle(void)
void __init at91x40_initialize(unsigned long main_clock)
{
arm_pm_idle = at91x40_idle;
at91_extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1)
| (1 << AT91X40_ID_IRQ2);
}
/*
@ -86,9 +84,10 @@ static unsigned int at91x40_default_irq_priority[NR_AIC_IRQS] __initdata = {
void __init at91x40_init_interrupts(unsigned int priority[NR_AIC_IRQS])
{
u32 extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1)
| (1 << AT91X40_ID_IRQ2);
if (!priority)
priority = at91x40_default_irq_priority;
at91_aic_init(priority, at91_extern_irq);
at91_aic_init(priority, extern_irq);
}

30
arch/arm/mach-at91/clock.c
View File

@ -75,7 +75,7 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
|| cpu_is_at91sam9g45() \
|| cpu_is_at91sam9x5() \
|| cpu_is_at91sam9n12()))
|| cpu_is_sama5d3()))
#define cpu_has_upll() (cpu_is_at91sam9g45() \
|| cpu_is_at91sam9x5() \
@ -489,7 +489,7 @@ static int at91_clk_show(struct seq_file *s, void *unused)
seq_printf(s, "UCKR = %8x\n", uckr);
}
seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
if (cpu_has_upll())
if (cpu_has_upll() || cpu_is_at91sam9n12())
seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB));
seq_printf(s, "SR = %8x\n", sr);
@ -614,6 +614,8 @@ static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
{
if (pll == &pllb && (reg & AT91_PMC_USB96M))
return freq / 2;
else if (pll == &utmi_clk || cpu_is_at91sam9n12())
return freq / (1 + ((reg & AT91_PMC_OHCIUSBDIV) >> 8));
else
return freq;
}
@ -683,6 +685,8 @@ static struct clk *const standard_pmc_clocks[] __initconst = {
/* PLLB generated USB full speed clock init */
static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
{
unsigned int reg;
/*
* USB clock init: choose 48 MHz PLLB value,
* disable 48MHz clock during usb peripheral suspend.
@ -691,22 +695,35 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
*/
uhpck.parent = &pllb;
at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
reg = at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2);
pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
if (cpu_is_at91rm9200()) {
reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
uhpck.pmc_mask = AT91RM9200_PMC_UHP;
udpck.pmc_mask = AT91RM9200_PMC_UDP;
at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
} else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
cpu_is_at91sam9g10()) {
reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
udpck.pmc_mask = AT91SAM926x_PMC_UDP;
} else if (cpu_is_at91sam9n12()) {
/* Divider for USB clock is in USB clock register for 9n12 */
reg = AT91_PMC_USBS_PLLB;
/* For PLLB output 96M, set usb divider 2 (USBDIV + 1) */
reg |= AT91_PMC_OHCIUSBDIV_2;
at91_pmc_write(AT91_PMC_USB, reg);
/* Still setup masks */
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
udpck.pmc_mask = AT91SAM926x_PMC_UDP;
}
at91_pmc_write(AT91_CKGR_PLLBR, 0);
udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
}
/* UPLL generated USB full speed clock init */
@ -725,8 +742,7 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
/* Now set uhpck values */
uhpck.parent = &utmi_clk;
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
uhpck.rate_hz = utmi_clk.rate_hz;
uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
uhpck.rate_hz = at91_usb_rate(&utmi_clk, utmi_clk.rate_hz, usbr);
}
static int __init at91_pmc_init(unsigned long main_clock)

2
arch/arm/mach-at91/cpuidle.c
View File

@ -51,7 +51,7 @@ static struct cpuidle_driver at91_idle_driver = {
.states[1] = {
.enter = at91_enter_idle,
.exit_latency = 10,
.target_residency = 100000,
.target_residency = 10000,
.flags = CPUIDLE_FLAG_TIME_VALID,
.name = "RAM_SR",
.desc = "WFI and DDR Self Refresh",

2
arch/arm/mach-at91/generic.h
View File

@ -85,4 +85,4 @@ extern void __init at91_gpio_irq_setup(void);
extern int __init at91_gpio_of_irq_setup(struct device_node *node,
struct device_node *parent);
extern int at91_extern_irq;
extern u32 at91_get_extern_irq(void);

3
arch/arm/mach-at91/include/mach/at91_pmc.h
View File

@ -130,7 +130,10 @@ extern void __iomem *at91_pmc_base;
#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
#define AT91_PMC_USBS_PLLA (0 << 0)
#define AT91_PMC_USBS_UPLL (1 << 0)
#define AT91_PMC_USBS_PLLB (1 << 0) /* [AT91SAMN12 only] */
#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
#define AT91_PMC_OHCIUSBDIV_1 (0x0 << 8)
#define AT91_PMC_OHCIUSBDIV_2 (0x1 << 8)
#define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */
#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */

9
arch/arm/mach-at91/irq.c
View File

@ -232,7 +232,14 @@ static void __maybe_unused at91_aic5_eoi(struct irq_data *d)
at91_aic_write(AT91_AIC5_EOICR, 0);
}
unsigned long *at91_extern_irq;
static unsigned long *at91_extern_irq;
u32 at91_get_extern_irq(void)
{
if (!at91_extern_irq)
return 0;
return *at91_extern_irq;
}
#define is_extern_irq(hwirq) test_bit(hwirq, at91_extern_irq)

2
arch/arm/mach-at91/pm.c
View File

@ -212,7 +212,7 @@ static int at91_pm_enter(suspend_state_t state)
(at91_pmc_read(AT91_PMC_PCSR)
| (1 << AT91_ID_FIQ)
| (1 << AT91_ID_SYS)
| (at91_extern_irq))
| (at91_get_extern_irq()))
& at91_aic_read(AT91_AIC_IMR),
state);

2
arch/arm/mach-at91/setup.c
View File

@ -48,7 +48,7 @@ void __init at91_init_irq_default(void)
void __init at91_init_interrupts(unsigned int *priority)
{
/* Initialize the AIC interrupt controller */
at91_aic_init(priority, at91_extern_irq);
at91_aic_init(priority, at91_boot_soc.extern_irq);
/* Enable GPIO interrupts */
at91_gpio_irq_setup();

1
arch/arm/mach-at91/soc.h
View File

@ -6,6 +6,7 @@
struct at91_init_soc {
int builtin;
u32 extern_irq;
unsigned int *default_irq_priority;
void (*map_io)(void);
void (*ioremap_registers)(void);