mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-25 13:43:55 +08:00
pinctrl: renesas: Updates for v5.11 (take two)
- Add QSPI pin groups on R-Car E3, H3, M3-W/W+, and M3-N, - A small fix for a Clang warning. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCX8D/lAAKCRCKwlD9ZEnx cLu+APwPXWg+/eDeGMft7GROw5SbCxhYcB8Gaouno7oYY7Z6mAD/cC9TJXrdZKV2 dRsTFT3bSyQD8iSVd+J/4AcqmoTHHQM= =TRxU -----END PGP SIGNATURE----- Merge tag 'renesas-pinctrl-for-v5.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.11 (take two) - Add QSPI pin groups on R-Car E3, H3, M3-W/W+, and M3-N, - A small fix for a Clang warning.
This commit is contained in:
commit
6b99afc01a
@ -3252,6 +3252,57 @@ static const unsigned int pwm6_b_mux[] = {
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PWM6_B_MARK,
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};
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/* - QSPI0 ------------------------------------------------------------------ */
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static const unsigned int qspi0_ctrl_pins[] = {
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/* QSPI0_SPCLK, QSPI0_SSL */
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PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
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};
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static const unsigned int qspi0_ctrl_mux[] = {
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QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
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};
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static const unsigned int qspi0_data2_pins[] = {
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/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
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PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
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};
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static const unsigned int qspi0_data2_mux[] = {
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QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
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};
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static const unsigned int qspi0_data4_pins[] = {
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/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
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PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
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/* QSPI0_IO2, QSPI0_IO3 */
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PIN_QSPI0_IO2, PIN_QSPI0_IO3,
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};
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static const unsigned int qspi0_data4_mux[] = {
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QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
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QSPI0_IO2_MARK, QSPI0_IO3_MARK,
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};
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/* - QSPI1 ------------------------------------------------------------------ */
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static const unsigned int qspi1_ctrl_pins[] = {
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/* QSPI1_SPCLK, QSPI1_SSL */
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PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
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};
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static const unsigned int qspi1_ctrl_mux[] = {
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QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
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};
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static const unsigned int qspi1_data2_pins[] = {
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/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
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PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
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};
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static const unsigned int qspi1_data2_mux[] = {
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QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
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};
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static const unsigned int qspi1_data4_pins[] = {
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/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
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PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
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/* QSPI1_IO2, QSPI1_IO3 */
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PIN_QSPI1_IO2, PIN_QSPI1_IO3,
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};
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static const unsigned int qspi1_data4_mux[] = {
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QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
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QSPI1_IO2_MARK, QSPI1_IO3_MARK,
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};
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/* - SATA --------------------------------------------------------------------*/
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static const unsigned int sata0_devslp_a_pins[] = {
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/* DEVSLP */
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@ -4160,7 +4211,7 @@ static const unsigned int vin5_clk_mux[] = {
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};
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static const struct {
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struct sh_pfc_pin_group common[320];
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struct sh_pfc_pin_group common[326];
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#ifdef CONFIG_PINCTRL_PFC_R8A77951
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struct sh_pfc_pin_group automotive[30];
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#endif
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@ -4365,6 +4416,12 @@ static const struct {
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SH_PFC_PIN_GROUP(pwm5_b),
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SH_PFC_PIN_GROUP(pwm6_a),
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SH_PFC_PIN_GROUP(pwm6_b),
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SH_PFC_PIN_GROUP(qspi0_ctrl),
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SH_PFC_PIN_GROUP(qspi0_data2),
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SH_PFC_PIN_GROUP(qspi0_data4),
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SH_PFC_PIN_GROUP(qspi1_ctrl),
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SH_PFC_PIN_GROUP(qspi1_data2),
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SH_PFC_PIN_GROUP(qspi1_data4),
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SH_PFC_PIN_GROUP(sata0_devslp_a),
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SH_PFC_PIN_GROUP(sata0_devslp_b),
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SH_PFC_PIN_GROUP(scif0_data),
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@ -4859,6 +4916,18 @@ static const char * const pwm6_groups[] = {
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"pwm6_b",
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};
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static const char * const qspi0_groups[] = {
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"qspi0_ctrl",
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"qspi0_data2",
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"qspi0_data4",
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};
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static const char * const qspi1_groups[] = {
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"qspi1_ctrl",
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"qspi1_data2",
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"qspi1_data4",
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};
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static const char * const sata0_groups[] = {
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"sata0_devslp_a",
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"sata0_devslp_b",
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@ -5047,7 +5116,7 @@ static const char * const vin5_groups[] = {
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};
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static const struct {
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struct sh_pfc_function common[53];
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struct sh_pfc_function common[55];
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#ifdef CONFIG_PINCTRL_PFC_R8A77951
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struct sh_pfc_function automotive[4];
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#endif
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@ -5084,6 +5153,8 @@ static const struct {
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SH_PFC_FUNCTION(pwm4),
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SH_PFC_FUNCTION(pwm5),
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SH_PFC_FUNCTION(pwm6),
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SH_PFC_FUNCTION(qspi0),
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SH_PFC_FUNCTION(qspi1),
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SH_PFC_FUNCTION(sata0),
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SH_PFC_FUNCTION(scif0),
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SH_PFC_FUNCTION(scif1),
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@ -3257,6 +3257,57 @@ static const unsigned int pwm6_b_mux[] = {
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PWM6_B_MARK,
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};
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/* - QSPI0 ------------------------------------------------------------------ */
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static const unsigned int qspi0_ctrl_pins[] = {
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/* QSPI0_SPCLK, QSPI0_SSL */
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PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
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};
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static const unsigned int qspi0_ctrl_mux[] = {
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QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
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};
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static const unsigned int qspi0_data2_pins[] = {
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/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
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PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
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};
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static const unsigned int qspi0_data2_mux[] = {
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QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
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};
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static const unsigned int qspi0_data4_pins[] = {
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/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
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PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
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/* QSPI0_IO2, QSPI0_IO3 */
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PIN_QSPI0_IO2, PIN_QSPI0_IO3,
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};
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static const unsigned int qspi0_data4_mux[] = {
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QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
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QSPI0_IO2_MARK, QSPI0_IO3_MARK,
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};
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/* - QSPI1 ------------------------------------------------------------------ */
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static const unsigned int qspi1_ctrl_pins[] = {
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/* QSPI1_SPCLK, QSPI1_SSL */
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PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
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};
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static const unsigned int qspi1_ctrl_mux[] = {
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QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
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};
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static const unsigned int qspi1_data2_pins[] = {
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/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
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PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
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};
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static const unsigned int qspi1_data2_mux[] = {
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QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
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};
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static const unsigned int qspi1_data4_pins[] = {
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/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
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PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
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/* QSPI1_IO2, QSPI1_IO3 */
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PIN_QSPI1_IO2, PIN_QSPI1_IO3,
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};
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static const unsigned int qspi1_data4_mux[] = {
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QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
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QSPI1_IO2_MARK, QSPI1_IO3_MARK,
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};
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/* - SCIF0 ------------------------------------------------------------------ */
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static const unsigned int scif0_data_pins[] = {
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/* RX, TX */
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@ -4134,7 +4185,7 @@ static const unsigned int vin5_clk_mux[] = {
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};
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static const struct {
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struct sh_pfc_pin_group common[316];
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struct sh_pfc_pin_group common[322];
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#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
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struct sh_pfc_pin_group automotive[30];
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#endif
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@ -4339,6 +4390,12 @@ static const struct {
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SH_PFC_PIN_GROUP(pwm5_b),
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SH_PFC_PIN_GROUP(pwm6_a),
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SH_PFC_PIN_GROUP(pwm6_b),
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SH_PFC_PIN_GROUP(qspi0_ctrl),
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SH_PFC_PIN_GROUP(qspi0_data2),
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SH_PFC_PIN_GROUP(qspi0_data4),
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SH_PFC_PIN_GROUP(qspi1_ctrl),
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SH_PFC_PIN_GROUP(qspi1_data2),
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SH_PFC_PIN_GROUP(qspi1_data4),
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SH_PFC_PIN_GROUP(scif0_data),
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SH_PFC_PIN_GROUP(scif0_clk),
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SH_PFC_PIN_GROUP(scif0_ctrl),
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@ -4829,6 +4886,18 @@ static const char * const pwm6_groups[] = {
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"pwm6_b",
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};
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static const char * const qspi0_groups[] = {
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"qspi0_ctrl",
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"qspi0_data2",
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"qspi0_data4",
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};
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static const char * const qspi1_groups[] = {
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"qspi1_ctrl",
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"qspi1_data2",
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"qspi1_data4",
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};
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static const char * const scif0_groups[] = {
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"scif0_data",
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"scif0_clk",
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@ -5004,7 +5073,7 @@ static const char * const vin5_groups[] = {
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};
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static const struct {
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struct sh_pfc_function common[50];
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struct sh_pfc_function common[52];
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#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
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struct sh_pfc_function automotive[4];
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#endif
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@ -5041,6 +5110,8 @@ static const struct {
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SH_PFC_FUNCTION(pwm4),
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SH_PFC_FUNCTION(pwm5),
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SH_PFC_FUNCTION(pwm6),
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SH_PFC_FUNCTION(qspi0),
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SH_PFC_FUNCTION(qspi1),
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SH_PFC_FUNCTION(scif0),
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SH_PFC_FUNCTION(scif1),
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SH_PFC_FUNCTION(scif2),
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@ -3408,6 +3408,57 @@ static const unsigned int pwm6_b_mux[] = {
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PWM6_B_MARK,
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};
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/* - QSPI0 ------------------------------------------------------------------ */
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static const unsigned int qspi0_ctrl_pins[] = {
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/* QSPI0_SPCLK, QSPI0_SSL */
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PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
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};
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static const unsigned int qspi0_ctrl_mux[] = {
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QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
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};
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static const unsigned int qspi0_data2_pins[] = {
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/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
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PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
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};
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static const unsigned int qspi0_data2_mux[] = {
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QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
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};
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static const unsigned int qspi0_data4_pins[] = {
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/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
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PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
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/* QSPI0_IO2, QSPI0_IO3 */
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PIN_QSPI0_IO2, PIN_QSPI0_IO3,
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};
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static const unsigned int qspi0_data4_mux[] = {
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QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
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QSPI0_IO2_MARK, QSPI0_IO3_MARK,
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};
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/* - QSPI1 ------------------------------------------------------------------ */
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static const unsigned int qspi1_ctrl_pins[] = {
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/* QSPI1_SPCLK, QSPI1_SSL */
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PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
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};
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static const unsigned int qspi1_ctrl_mux[] = {
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QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
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};
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static const unsigned int qspi1_data2_pins[] = {
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/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
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PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
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};
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static const unsigned int qspi1_data2_mux[] = {
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QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
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};
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static const unsigned int qspi1_data4_pins[] = {
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/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
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PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
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/* QSPI1_IO2, QSPI1_IO3 */
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PIN_QSPI1_IO2, PIN_QSPI1_IO3,
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};
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static const unsigned int qspi1_data4_mux[] = {
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QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
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QSPI1_IO2_MARK, QSPI1_IO3_MARK,
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};
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/* - SATA --------------------------------------------------------------------*/
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static const unsigned int sata0_devslp_a_pins[] = {
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/* DEVSLP */
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@ -4381,7 +4432,7 @@ static const unsigned int vin5_clk_mux[] = {
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};
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static const struct {
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struct sh_pfc_pin_group common[318];
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struct sh_pfc_pin_group common[324];
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#ifdef CONFIG_PINCTRL_PFC_R8A77965
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struct sh_pfc_pin_group automotive[30];
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#endif
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@ -4586,6 +4637,12 @@ static const struct {
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SH_PFC_PIN_GROUP(pwm5_b),
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SH_PFC_PIN_GROUP(pwm6_a),
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SH_PFC_PIN_GROUP(pwm6_b),
|
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SH_PFC_PIN_GROUP(qspi0_ctrl),
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SH_PFC_PIN_GROUP(qspi0_data2),
|
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SH_PFC_PIN_GROUP(qspi0_data4),
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SH_PFC_PIN_GROUP(qspi1_ctrl),
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SH_PFC_PIN_GROUP(qspi1_data2),
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SH_PFC_PIN_GROUP(qspi1_data4),
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SH_PFC_PIN_GROUP(sata0_devslp_a),
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SH_PFC_PIN_GROUP(sata0_devslp_b),
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SH_PFC_PIN_GROUP(scif0_data),
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@ -5078,6 +5135,18 @@ static const char * const pwm6_groups[] = {
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"pwm6_b",
|
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};
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static const char * const qspi0_groups[] = {
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"qspi0_ctrl",
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"qspi0_data2",
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"qspi0_data4",
|
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};
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static const char * const qspi1_groups[] = {
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"qspi1_ctrl",
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"qspi1_data2",
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"qspi1_data4",
|
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};
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|
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static const char * const sata0_groups[] = {
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"sata0_devslp_a",
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"sata0_devslp_b",
|
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@ -5257,7 +5326,7 @@ static const char * const vin5_groups[] = {
|
||||
};
|
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|
||||
static const struct {
|
||||
struct sh_pfc_function common[51];
|
||||
struct sh_pfc_function common[53];
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77965
|
||||
struct sh_pfc_function automotive[4];
|
||||
#endif
|
||||
@ -5294,6 +5363,8 @@ static const struct {
|
||||
SH_PFC_FUNCTION(pwm4),
|
||||
SH_PFC_FUNCTION(pwm5),
|
||||
SH_PFC_FUNCTION(pwm6),
|
||||
SH_PFC_FUNCTION(qspi0),
|
||||
SH_PFC_FUNCTION(qspi1),
|
||||
SH_PFC_FUNCTION(sata0),
|
||||
SH_PFC_FUNCTION(scif0),
|
||||
SH_PFC_FUNCTION(scif1),
|
||||
|
@ -2810,6 +2810,57 @@ static const unsigned int pwm6_b_mux[] = {
|
||||
PWM6_B_MARK,
|
||||
};
|
||||
|
||||
/* - QSPI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int qspi0_ctrl_pins[] = {
|
||||
/* QSPI0_SPCLK, QSPI0_SSL */
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 5),
|
||||
};
|
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static const unsigned int qspi0_ctrl_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data2_pins[] = {
|
||||
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
|
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RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
|
||||
};
|
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static const unsigned int qspi0_data2_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
};
|
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static const unsigned int qspi0_data4_pins[] = {
|
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/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
|
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RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
|
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/* QSPI0_IO2, QSPI0_IO3 */
|
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RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
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};
|
||||
static const unsigned int qspi0_data4_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
|
||||
};
|
||||
/* - QSPI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int qspi1_ctrl_pins[] = {
|
||||
/* QSPI1_SPCLK, QSPI1_SSL */
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 11),
|
||||
};
|
||||
static const unsigned int qspi1_ctrl_mux[] = {
|
||||
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data2_pins[] = {
|
||||
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
|
||||
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
|
||||
};
|
||||
static const unsigned int qspi1_data2_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data4_pins[] = {
|
||||
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
|
||||
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
|
||||
/* QSPI1_IO2, QSPI1_IO3 */
|
||||
RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
|
||||
};
|
||||
static const unsigned int qspi1_data4_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
|
||||
};
|
||||
|
||||
/* - SCIF0 ------------------------------------------------------------------ */
|
||||
static const unsigned int scif0_data_a_pins[] = {
|
||||
/* RX, TX */
|
||||
@ -3762,7 +3813,7 @@ static const unsigned int vin5_clk_b_mux[] = {
|
||||
};
|
||||
|
||||
static const struct {
|
||||
struct sh_pfc_pin_group common[247];
|
||||
struct sh_pfc_pin_group common[253];
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77990
|
||||
struct sh_pfc_pin_group automotive[21];
|
||||
#endif
|
||||
@ -3910,6 +3961,12 @@ static const struct {
|
||||
SH_PFC_PIN_GROUP(pwm5_b),
|
||||
SH_PFC_PIN_GROUP(pwm6_a),
|
||||
SH_PFC_PIN_GROUP(pwm6_b),
|
||||
SH_PFC_PIN_GROUP(qspi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi0_data2),
|
||||
SH_PFC_PIN_GROUP(qspi0_data4),
|
||||
SH_PFC_PIN_GROUP(qspi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi1_data2),
|
||||
SH_PFC_PIN_GROUP(qspi1_data4),
|
||||
SH_PFC_PIN_GROUP(scif0_data_a),
|
||||
SH_PFC_PIN_GROUP(scif0_clk_a),
|
||||
SH_PFC_PIN_GROUP(scif0_ctrl_a),
|
||||
@ -4313,6 +4370,18 @@ static const char * const pwm6_groups[] = {
|
||||
"pwm6_b",
|
||||
};
|
||||
|
||||
static const char * const qspi0_groups[] = {
|
||||
"qspi0_ctrl",
|
||||
"qspi0_data2",
|
||||
"qspi0_data4",
|
||||
};
|
||||
|
||||
static const char * const qspi1_groups[] = {
|
||||
"qspi1_ctrl",
|
||||
"qspi1_data2",
|
||||
"qspi1_data4",
|
||||
};
|
||||
|
||||
static const char * const scif0_groups[] = {
|
||||
"scif0_data_a",
|
||||
"scif0_clk_a",
|
||||
@ -4467,7 +4536,7 @@ static const char * const vin5_groups[] = {
|
||||
};
|
||||
|
||||
static const struct {
|
||||
struct sh_pfc_function common[47];
|
||||
struct sh_pfc_function common[49];
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77990
|
||||
struct sh_pfc_function automotive[4];
|
||||
#endif
|
||||
@ -4504,6 +4573,8 @@ static const struct {
|
||||
SH_PFC_FUNCTION(pwm4),
|
||||
SH_PFC_FUNCTION(pwm5),
|
||||
SH_PFC_FUNCTION(pwm6),
|
||||
SH_PFC_FUNCTION(qspi0),
|
||||
SH_PFC_FUNCTION(qspi1),
|
||||
SH_PFC_FUNCTION(scif0),
|
||||
SH_PFC_FUNCTION(scif1),
|
||||
SH_PFC_FUNCTION(scif2),
|
||||
|
@ -931,6 +931,7 @@ static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl,
|
||||
case PIN_CONFIG_OUTPUT: /* for DT backwards compatibility */
|
||||
case PIN_CONFIG_OUTPUT_ENABLE:
|
||||
pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user