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AT91RM9200 Ethernet: Support additional PHYs
Add support for a number of new PHY's in the AT91RM9200 Ethernet driver. - Teridian 78Q21x3 - SMSC LAN83C185 (Patch from Luca Gamma) - National Semiconductor DP83848 (Patches from Ivan Kuten & Thomas Foldesi) Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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parent
0b45d18643
commit
6b4aea7352
drivers/net/arm
@ -225,6 +225,16 @@ static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id)
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if (!(phy & ((1 << 2) | 1)))
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goto done;
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}
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else if (lp->phy_type == MII_T78Q21x3_ID) { /* ack interrupt in Teridian PHY */
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read_phy(lp->phy_address, MII_T78Q21INT_REG, &phy);
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if (!(phy & ((1 << 2) | 1)))
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goto done;
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}
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else if (lp->phy_type == MII_DP83848_ID) {
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read_phy(lp->phy_address, MII_DPPHYSTS_REG, &phy); /* ack interrupt in DP83848 PHY */
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if (!(phy & (1 << 7)))
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goto done;
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}
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update_linkspeed(dev, 0);
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@ -280,6 +290,19 @@ static void enable_phyirq(struct net_device *dev)
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dsintr = (1 << 10) | ( 1 << 8);
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write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
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}
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else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
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read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr);
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dsintr = dsintr | 0x500; /* set bits 8, 10 */
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write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr);
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}
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else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
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read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr);
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dsintr = dsintr | 0x3c; /* set bits 2..5 */
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write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
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read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr);
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dsintr = dsintr | 0x3; /* set bits 0,1 */
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write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
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}
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disable_mdi();
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spin_unlock_irq(&lp->lock);
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@ -323,6 +346,19 @@ static void disable_phyirq(struct net_device *dev)
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dsintr = ~((1 << 10) | (1 << 8));
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write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
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}
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else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
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read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr);
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dsintr = dsintr & ~0x500; /* clear bits 8, 10 */
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write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr);
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}
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else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
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read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr);
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dsintr = dsintr & ~0x3; /* clear bits 0, 1 */
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write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
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read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr);
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dsintr = dsintr & ~0x3c; /* clear bits 2..5 */
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write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
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}
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disable_mdi();
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spin_unlock_irq(&lp->lock);
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@ -1062,10 +1098,16 @@ static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_add
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printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name);
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else if (phy_type == MII_DP83847_ID)
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printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name);
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else if (phy_type == MII_DP83848_ID)
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printk(KERN_INFO "%s: National Semiconductor DP83848 PHY\n", dev->name);
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else if (phy_type == MII_AC101L_ID)
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printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name);
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else if (phy_type == MII_KS8721_ID)
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printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name);
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else if (phy_type == MII_T78Q21x3_ID)
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printk(KERN_INFO "%s: Teridian 78Q21x3 PHY\n", dev->name);
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else if (phy_type == MII_LAN83C185_ID)
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printk(KERN_INFO "%s: SMSC LAN83C185 PHY\n", dev->name);
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return 0;
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}
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@ -1103,8 +1145,11 @@ static int __init at91ether_probe(struct platform_device *pdev)
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case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */
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case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */
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case MII_DP83847_ID: /* National Semiconductor DP83847: */
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case MII_DP83848_ID: /* National Semiconductor DP83848: */
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case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
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case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
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case MII_T78Q21x3_ID: /* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */
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case MII_LAN83C185_ID: /* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */
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detected = at91ether_setup(phy_id, phy_address, pdev, ether_clk);
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break;
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}
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@ -17,39 +17,46 @@
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/* Davicom 9161 PHY */
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#define MII_DM9161_ID 0x0181b880
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#define MII_DM9161A_ID 0x0181b8a0
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/* Davicom specific registers */
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#define MII_DSCR_REG 16
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#define MII_DSCSR_REG 17
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#define MII_DSINTR_REG 21
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#define MII_DM9161_ID 0x0181b880
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#define MII_DM9161A_ID 0x0181b8a0
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#define MII_DSCR_REG 16
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#define MII_DSCSR_REG 17
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#define MII_DSINTR_REG 21
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/* Intel LXT971A PHY */
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#define MII_LXT971A_ID 0x001378E0
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/* Intel specific registers */
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#define MII_ISINTE_REG 18
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#define MII_ISINTS_REG 19
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#define MII_LEDCTRL_REG 20
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#define MII_LXT971A_ID 0x001378E0
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#define MII_ISINTE_REG 18
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#define MII_ISINTS_REG 19
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#define MII_LEDCTRL_REG 20
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/* Realtek RTL8201 PHY */
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#define MII_RTL8201_ID 0x00008200
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#define MII_RTL8201_ID 0x00008200
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/* Broadcom BCM5221 PHY */
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#define MII_BCM5221_ID 0x004061e0
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/* Broadcom specific registers */
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#define MII_BCMINTR_REG 26
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#define MII_BCM5221_ID 0x004061e0
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#define MII_BCMINTR_REG 26
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/* National Semiconductor DP83847 */
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#define MII_DP83847_ID 0x20005c30
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#define MII_DP83847_ID 0x20005c30
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/* National Semiconductor DP83848 */
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#define MII_DP83848_ID 0x20005c90
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#define MII_DPPHYSTS_REG 16
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#define MII_DPMICR_REG 17
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#define MII_DPMISR_REG 18
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/* Altima AC101L PHY */
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#define MII_AC101L_ID 0x00225520
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#define MII_AC101L_ID 0x00225520
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/* Micrel KS8721 PHY */
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#define MII_KS8721_ID 0x00221610
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#define MII_KS8721_ID 0x00221610
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/* Teridian 78Q2123/78Q2133 */
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#define MII_T78Q21x3_ID 0x000e7230
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#define MII_T78Q21INT_REG 17
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/* SMSC LAN83C185 */
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#define MII_LAN83C185_ID 0x0007C0A0
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/* ........................................................................ */
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