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thermal: exynos: remove needless threshold_temp abstraction
reg->threshold_temp is used only in exynos_tmu_initialize() and is accessed only on Exynos4210 (other SoC types don't even have threshold_temp entry assigned in their struct exynos_tmu_registers instances) so the register abstraction is not needed and can be removed. There should be no functional changes caused by this patch. Cc: Amit Daniel Kachhap <amit.daniel@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Eduardo Valentin <edubezval@gmail.com> Cc: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
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@ -219,7 +219,7 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
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/* Write temperature code for threshold */
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/* Write temperature code for threshold */
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threshold_code = temp_to_code(data, pdata->threshold);
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threshold_code = temp_to_code(data, pdata->threshold);
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writeb(threshold_code,
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writeb(threshold_code,
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data->base + reg->threshold_temp);
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data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
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for (i = 0; i < pdata->non_hw_trigger_levels; i++)
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for (i = 0; i < pdata->non_hw_trigger_levels; i++)
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writeb(pdata->trigger_levels[i], data->base +
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writeb(pdata->trigger_levels[i], data->base +
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reg->threshold_th0 + i * sizeof(reg->threshold_th0));
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reg->threshold_th0 + i * sizeof(reg->threshold_th0));
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@ -84,7 +84,6 @@ enum soc_type {
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* @therm_trip_mode_mask: mask bits of tripping mode in tmu_ctrl register.
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* @therm_trip_mode_mask: mask bits of tripping mode in tmu_ctrl register.
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* @therm_trip_en_shift: shift bits of tripping enable in tmu_ctrl register.
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* @therm_trip_en_shift: shift bits of tripping enable in tmu_ctrl register.
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* @tmu_cur_temp: register containing the current temperature of the TMU.
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* @tmu_cur_temp: register containing the current temperature of the TMU.
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* @threshold_temp: register containing the base threshold level.
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* @threshold_th0: Register containing first set of rising levels.
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* @threshold_th0: Register containing first set of rising levels.
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* @threshold_th1: Register containing second set of rising levels.
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* @threshold_th1: Register containing second set of rising levels.
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* @threshold_th2: Register containing third set of rising levels.
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* @threshold_th2: Register containing third set of rising levels.
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@ -116,8 +115,6 @@ struct exynos_tmu_registers {
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u32 tmu_cur_temp;
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u32 tmu_cur_temp;
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u32 threshold_temp;
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u32 threshold_th0;
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u32 threshold_th0;
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u32 threshold_th1;
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u32 threshold_th1;
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u32 threshold_th2;
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u32 threshold_th2;
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@ -28,7 +28,6 @@
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static const struct exynos_tmu_registers exynos4210_tmu_registers = {
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static const struct exynos_tmu_registers exynos4210_tmu_registers = {
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
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.threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
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.threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
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.tmu_inten = EXYNOS_TMU_REG_INTEN,
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.tmu_inten = EXYNOS_TMU_REG_INTEN,
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.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
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.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
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