renegade-project/linux-next
2
0
Fork 0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-19 10:44:14 +08:00
Code

MTD core changes:

Browse Source 
* Initial support for BCM4908 partitions
 
 Raw NAND controller drivers:
 * Intel: Fix an error handling path in 'ebu_dma_start()'
 * Tango: Remove the driver
 * Marvell: Convert comma to semicolon
 * MXC: Convert comma to semicolon
 * Qcom: Add support for Qcom SMEM parser
 
 Related MTD changes:
 * parsers: Add Qcom SMEM parser
 
 SPI NOR core changes:
 * Add non-uniform erase fixes.
 * Add Global Block Unlock command. It is defined by few flash
  vendors, and it is used for now just by sst.
 
 SPI NOR controller drivers changes:
 * intel-spi: Add support for Intel Alder Lake-P SPI serial flash.
 * hisi-sfc: Put child node np on error path.
 -----BEGIN PGP SIGNATURE-----
 
 iQJKBAABCAA0FiEEdgfidid8lnn52cLTZvlZhesYu8EFAmAyuDgWHHJpY2hhcmRA
 c2lnbWEtc3Rhci5hdAAKCRBm+VmF6xi7wf/WEACWtDmQVXZPoKijrYZBWXLv3dC2
 JEUT3QKwnDVf9QOLUjq5MdCxN/z3IqAjx1htVrR3DFExjgFkMbmxOMQxHp+d4BiP
 hZBIaC7UFocsgXY5iZ7OyZBoZoE8GQwpIiz8KMoXN1sqB6vrfn3NenbbDldsJgVx
 5jAWNarHm0ndHYtBEVwhOC9ogp1b8GR6/W8iAv2jt3Ap06FajSlaf2SOknxD1rY5
 pSosVxXFdWatWI88ZAj+v68o+yAj+Yd3wTunA1pPHPr9jlHNJ0JlpIlWH4XU0iir
 BBTFdF9v8/id7Lo+eFw05rfIQ/eMDlD93B0qHKcyIUjJOs1rj2JshFM/QbH64Mjv
 zDLfqacRZQgHNZJg8AfdCPGhjxwl60BTrXiASG5TYsvavvyEx/L1mtdJ2ZI+tizU
 kFNzdpdgEroZtTKMiA0scTRqciB6/IA7PmLpfhBf0Zzi+EENIB+bBwi+EH4aYmYC
 PYl2/wABNA+JkSypT+UJKcYnFt3FYRtTq5O4tUyLcwRzbHuYUqZTMi/QeD01ltvN
 4B5VbsOtAAfJSOMWGc7qbf34Hs7kED0TrfKbmtaZf580eso7+zpxdtxVnm5iBx7u
 V5M2TDOq7/81sXgnvc2i8qbOWtVI9GcRWfre+PgheMn97Wd4VvInfXawwShI1TGU
 PlCelptKmuc035eRBQ==
 =uQQ1
 -----END PGP SIGNATURE-----

Merge tag 'mtd/for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux

Pull MTD updates from Richard Weinberger:
 "MTD core changes:
   - Initial support for BCM4908 partitions

  Raw NAND controller drivers:
   - Intel: Fix an error handling path in 'ebu_dma_start()'
   - Tango: Remove the driver
   - Marvell: Convert comma to semicolon
   - MXC: Convert comma to semicolon
   - Qcom: Add support for Qcom SMEM parser

  Related MTD changes:
   - parsers: Add Qcom SMEM parser

  SPI NOR core changes:
   - Add non-uniform erase fixes.
   - Add Global Block Unlock command. It is defined by few flash
     vendors, and it is used for now just by sst.

  SPI NOR controller drivers changes:
   - intel-spi: Add support for Intel Alder Lake-P SPI serial flash.
   - hisi-sfc: Put child node np on error path"

* tag 'mtd/for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (23 commits)
  dt-bindings: mtd: add binding for BCM4908 partitions
  dt-bindings: mtd: move partition binding to its own file
  mtd: spi-nor: sst: Add support for Global Unlock on sst26vf
  mtd: spi-nor: Add Global Block Unlock command
  mtd: spi-nor: core: Add erase size check for erase command initialization
  mtd: spi-nor: core: Fix erase type discovery for overlaid region
  mtd: spi-nor: sfdp: Fix last erase region marking
  mtd: spi-nor: sfdp: Fix wrong erase type bitmask for overlaid region
  mtd: rawnand: intel: Fix an error handling path in 'ebu_dma_start()'
  mtd: rawnand: tango: Remove the driver
  mtd: rawnand: marvell: convert comma to semicolon
  mtd: st_spi_fsm: convert comma to semicolon
  mtd: convert comma to semicolon
  mtd: parsers: afs: Fix freeing the part name memory in failure
  mtd: parser: imagetag: fix error codes in bcm963xx_parse_imagetag_partitions()
  mtd: phram: use div_u64_rem to stop overwrite len in phram_setup
  mtd: remove redundant assignment to pointer eb
  mtd: spi-nor: hisi-sfc: Put child node np on error path
  mtd: spi-nor: intel-spi: Add support for Intel Alder Lake-P SPI serial flash
  mtd: rawnand: qcom: Add support for Qcom SMEM parser
  ...
This commit is contained in:
Linus Torvalds 2021-02-21 13:54:33 -08:00
commit 69e9b12a27
27 changed files with 457 additions and 793 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

70
Documentation/devicetree/bindings/mtd/partitions/brcm,bcm4908-partitions.yaml Normal file
View File

@ -0,0 +1,70 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/brcm,bcm4908-partitions.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM4908 partitioning
description: |
Broadcom BCM4908 CFE bootloader supports two firmware partitions. One is used
for regular booting, the other is treated as fallback.
This binding allows defining all fixed partitions and marking those containing
firmware. System can use that information e.g. for booting or flashing
purposes.
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
properties:
compatible:
const: brcm,bcm4908-partitions
"#address-cells":
enum: [ 1, 2 ]
"#size-cells":
enum: [ 1, 2 ]
patternProperties:
"^partition@[0-9a-f]+$":
$ref: "partition.yaml#"
properties:
compatible:
const: brcm,bcm4908-firmware
unevaluatedProperties: false
required:
- "#address-cells"
- "#size-cells"
additionalProperties: false
examples:
- |
partitions {
compatible = "brcm,bcm4908-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "cferom";
reg = <0x0 0x100000>;
};
partition@100000 {
compatible = "brcm,bcm4908-firmware";
reg = <0x100000 0xf00000>;
};
partition@1000000 {
compatible = "brcm,bcm4908-firmware";
reg = <0x1000000 0xf00000>;
};
partition@1f00000 {
label = "calibration";
reg = <0x1f00000 0x100000>;
};
};

33
Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml
View File

@ -27,38 +27,7 @@ properties:
patternProperties:
"@[0-9a-f]+$":
description: node describing a single flash partition
type: object
properties:
reg:
description: partition's offset and size within the flash
maxItems: 1
label:
description: The label / name for this partition. If omitted, the label
is taken from the node name (excluding the unit address).
read-only:
description: This parameter, if present, is a hint that this partition
should only be mounted read-only. This is usually used for flash
partitions containing early-boot firmware images or data which should
not be clobbered.
type: boolean
lock:
description: Do not unlock the partition at initialization time (not
supported on all devices)
type: boolean
slc-mode:
description: This parameter, if present, allows one to emulate SLC mode
on a partition attached to an MLC NAND thus making this partition
immune to paired-pages corruptions
type: boolean
required:
- reg
$ref: "partition.yaml#"
required:
- "#address-cells"

47
Documentation/devicetree/bindings/mtd/partitions/partition.yaml Normal file
View File

@ -0,0 +1,47 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/partition.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Partition
description: |
This binding describes a single flash partition. Each partition must have its
relative offset and size specified. Depending on partition function extra
properties can be used.
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
properties:
reg:
description: partition's offset and size within the flash
maxItems: 1
label:
description: The label / name for this partition. If omitted, the label
is taken from the node name (excluding the unit address).
read-only:
description: This parameter, if present, is a hint that this partition
should only be mounted read-only. This is usually used for flash
partitions containing early-boot firmware images or data which should
not be clobbered.
type: boolean
lock:
description: Do not unlock the partition at initialization time (not
supported on all devices)
type: boolean
slc-mode:
description: This parameter, if present, allows one to emulate SLC mode
on a partition attached to an MLC NAND thus making this partition
immune to paired-pages corruptions
type: boolean
required:
- reg
additionalProperties: true

33
Documentation/devicetree/bindings/mtd/partitions/qcom,smem-part.yaml Normal file
View File

@ -0,0 +1,33 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/qcom,smem-part.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SMEM NAND flash partition parser binding
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description: |
The Qualcomm SoCs supporting the NAND controller interface features a Shared
Memory (SMEM) based partition table scheme. The maximum partitions supported
varies between partition table revisions. V3 supports maximum 16 partitions
and V4 supports 48 partitions.
properties:
compatible:
const: qcom,smem-part
required:
- compatible
additionalProperties: false
examples:
- |
flash {
partitions {
compatible = "qcom,smem-part";
};
};

6
drivers/mtd/devices/phram.c
View File

@ -222,6 +222,7 @@ static int phram_setup(const char *val)
uint64_t start;
uint64_t len;
uint64_t erasesize = PAGE_SIZE;
uint32_t rem;
int i, ret;
if (strnlen(val, sizeof(buf)) >= sizeof(buf))
@ -263,8 +264,11 @@ static int phram_setup(const char *val)
}
}
if (erasesize)
div_u64_rem(len, (uint32_t)erasesize, &rem);
if (len == 0 || erasesize == 0 || erasesize > len
|| erasesize > UINT_MAX || do_div(len, (uint32_t)erasesize) != 0) {
|| erasesize > UINT_MAX || rem) {
parse_err("illegal erasesize or len\n");
goto error;
}

2
drivers/mtd/devices/st_spi_fsm.c
View File

@ -924,7 +924,7 @@ static int stfsm_read_status(struct stfsm *fsm, uint8_t cmd,
BUG_ON(bytes != 1 && bytes != 2);
seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
SEQ_OPC_OPCODE(cmd)),
SEQ_OPC_OPCODE(cmd));
stfsm_load_seq(fsm, seq);

8
drivers/mtd/maps/pci.c
View File

@ -90,8 +90,8 @@ intel_iq80310_init(struct pci_dev *dev, struct map_pci_info *map)
u32 win_base;
map->map.bankwidth = 1;
map->map.read = mtd_pci_read8,
map->map.write = mtd_pci_write8,
map->map.read = mtd_pci_read8;
map->map.write = mtd_pci_write8;
map->map.size = 0x00800000;
map->base = ioremap(pci_resource_start(dev, 0),
@ -185,8 +185,8 @@ intel_dc21285_init(struct pci_dev *dev, struct map_pci_info *map)
return -ENXIO;
map->map.bankwidth = 4;
map->map.read = mtd_pci_read32,
map->map.write = mtd_pci_write32,
map->map.read = mtd_pci_read32;
map->map.write = mtd_pci_write32;
map->map.size = len;
map->base = ioremap(base, len);

1
drivers/mtd/mtdswap.c
View File

@ -1053,7 +1053,6 @@ static int mtdswap_writesect(struct mtd_blktrans_dev *dev,
if (ret < 0)
return ret;
eb = d->eb_data + (newblock / d->pages_per_eblk);
d->page_data[page] = newblock;
return 0;

7
drivers/mtd/nand/raw/Kconfig
View File

@ -102,13 +102,6 @@ config MTD_NAND_S3C2410_CLKSTOP
when the is NAND chip selected or released, but will save
approximately 5mA of power when there is nothing happening.
config MTD_NAND_TANGO
tristate "Tango NAND controller"
depends on ARCH_TANGO || COMPILE_TEST
depends on HAS_IOMEM
help
Enables the NAND Flash controller on Tango chips.
config MTD_NAND_SHARPSL
tristate "Sharp SL Series (C7xx + others) NAND controller"
depends on ARCH_PXA || COMPILE_TEST

1
drivers/mtd/nand/raw/Makefile
View File

@ -10,7 +10,6 @@ obj-$(CONFIG_MTD_NAND_DENALI_PCI) += denali_pci.o
obj-$(CONFIG_MTD_NAND_DENALI_DT) += denali_dt.o
obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o
obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o
obj-$(CONFIG_MTD_NAND_TANGO) += tango_nand.o
obj-$(CONFIG_MTD_NAND_DAVINCI) += davinci_nand.o
obj-$(CONFIG_MTD_NAND_DISKONCHIP) += diskonchip.o
obj-$(CONFIG_MTD_NAND_FSMC) += fsmc_nand.o

6
drivers/mtd/nand/raw/intel-nand-controller.c
View File

@ -318,8 +318,10 @@ static int ebu_dma_start(struct ebu_nand_controller *ebu_host, u32 dir,
}
tx = dmaengine_prep_slave_single(chan, buf_dma, len, dir, flags);
if (!tx)
return -ENXIO;
if (!tx) {
ret = -ENXIO;
goto err_unmap;
}
tx->callback = callback;
tx->callback_param = ebu_host;

2
drivers/mtd/nand/raw/marvell_nand.c
View File

@ -2396,7 +2396,7 @@ static int marvell_nfc_setup_interface(struct nand_chip *chip, int chipnr,
* be greater than that to be sure tCCS delay is respected.
*/
nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min),
period_ns) - 2,
period_ns) - 2;
nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min),
period_ns);

2
drivers/mtd/nand/raw/mxc_nand.c
View File

@ -1731,7 +1731,7 @@ static int mxcnd_probe(struct platform_device *pdev)
this->legacy.chip_delay = 5;
nand_set_controller_data(this, host);
nand_set_flash_node(this, pdev->dev.of_node),
nand_set_flash_node(this, pdev->dev.of_node);
this->legacy.dev_ready = mxc_nand_dev_ready;
this->legacy.cmdfunc = mxc_nand_command;
this->legacy.read_byte = mxc_nand_read_byte;

4
drivers/mtd/nand/raw/qcom_nandc.c
View File

@ -2821,6 +2821,8 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
return 0;
}
static const char * const probes[] = { "qcomsmem", NULL };
static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc,
struct qcom_nand_host *host,
struct device_node *dn)
@ -2884,7 +2886,7 @@ static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc,
}
}
ret = mtd_device_register(mtd, NULL, 0);
ret = mtd_device_parse_register(mtd, probes, NULL, NULL, 0);
if (ret)
nand_cleanup(chip);

727
drivers/mtd/nand/raw/tango_nand.c
View File

@ -1,727 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2016 Sigma Designs
*/
#include <linux/io.h>
#include <linux/of.h>
#include <linux/clk.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/mtd/rawnand.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
/* Offsets relative to chip->base */
#define PBUS_CMD 0
#define PBUS_ADDR 4
#define PBUS_DATA 8
/* Offsets relative to reg_base */
#define NFC_STATUS 0x00
#define NFC_FLASH_CMD 0x04
#define NFC_DEVICE_CFG 0x08
#define NFC_TIMING1 0x0c
#define NFC_TIMING2 0x10
#define NFC_XFER_CFG 0x14
#define NFC_PKT_0_CFG 0x18
#define NFC_PKT_N_CFG 0x1c
#define NFC_BB_CFG 0x20
#define NFC_ADDR_PAGE 0x24
#define NFC_ADDR_OFFSET 0x28
#define NFC_XFER_STATUS 0x2c
/* NFC_STATUS values */
#define CMD_READY BIT(31)
/* NFC_FLASH_CMD values */
#define NFC_READ 1
#define NFC_WRITE 2
/* NFC_XFER_STATUS values */
#define PAGE_IS_EMPTY BIT(16)
/* Offsets relative to mem_base */
#define METADATA 0x000
#define ERROR_REPORT 0x1c0
/*
* Error reports are split in two bytes:
* byte 0 for the first packet in the page (PKT_0)
* byte 1 for other packets in the page (PKT_N, for N > 0)
* ERR_COUNT_PKT_N is the max error count over all but the first packet.
*/
#define ERR_COUNT_PKT_0(v) (((v) >> 0) & 0x3f)
#define ERR_COUNT_PKT_N(v) (((v) >> 8) & 0x3f)
#define DECODE_FAIL_PKT_0(v) (((v) & BIT(7)) == 0)
#define DECODE_FAIL_PKT_N(v) (((v) & BIT(15)) == 0)
/* Offsets relative to pbus_base */
#define PBUS_CS_CTRL 0x83c
#define PBUS_PAD_MODE 0x8f0
/* PBUS_CS_CTRL values */
#define PBUS_IORDY BIT(31)
/*
* PBUS_PAD_MODE values
* In raw mode, the driver communicates directly with the NAND chips.
* In NFC mode, the NAND Flash controller manages the communication.
* We use NFC mode for read and write; raw mode for everything else.
*/
#define MODE_RAW 0
#define MODE_NFC BIT(31)
#define METADATA_SIZE 4
#define BBM_SIZE 6
#define FIELD_ORDER 15
#define MAX_CS 4
struct tango_nfc {
struct nand_controller hw;
void __iomem *reg_base;
void __iomem *mem_base;
void __iomem *pbus_base;
struct tango_chip *chips[MAX_CS];
struct dma_chan *chan;
int freq_kHz;
};
#define to_tango_nfc(ptr) container_of(ptr, struct tango_nfc, hw)
struct tango_chip {
struct nand_chip nand_chip;
void __iomem *base;
u32 timing1;
u32 timing2;
u32 xfer_cfg;
u32 pkt_0_cfg;
u32 pkt_n_cfg;
u32 bb_cfg;
};
#define to_tango_chip(ptr) container_of(ptr, struct tango_chip, nand_chip)
#define XFER_CFG(cs, page_count, steps, metadata_size) \
((cs) << 24 | (page_count) << 16 | (steps) << 8 | (metadata_size))
#define PKT_CFG(size, strength) ((size) << 16 | (strength))
#define BB_CFG(bb_offset, bb_size) ((bb_offset) << 16 | (bb_size))
#define TIMING(t0, t1, t2, t3) ((t0) << 24 | (t1) << 16 | (t2) << 8 | (t3))
static void tango_select_target(struct nand_chip *chip, unsigned int cs)
{
struct tango_nfc *nfc = to_tango_nfc(chip->controller);
struct tango_chip *tchip = to_tango_chip(chip);
writel_relaxed(tchip->timing1, nfc->reg_base + NFC_TIMING1);
writel_relaxed(tchip->timing2, nfc->reg_base + NFC_TIMING2);
writel_relaxed(tchip->xfer_cfg, nfc->reg_base + NFC_XFER_CFG);
writel_relaxed(tchip->pkt_0_cfg, nfc->reg_base + NFC_PKT_0_CFG);
writel_relaxed(tchip->pkt_n_cfg, nfc->reg_base + NFC_PKT_N_CFG);
writel_relaxed(tchip->bb_cfg, nfc->reg_base + NFC_BB_CFG);
}
static int tango_waitrdy(struct nand_chip *chip, unsigned int timeout_ms)
{
struct tango_nfc *nfc = to_tango_nfc(chip->controller);
u32 status;
return readl_relaxed_poll_timeout(nfc->pbus_base + PBUS_CS_CTRL,
status, status & PBUS_IORDY, 20,
timeout_ms);
}
static int tango_exec_instr(struct nand_chip *chip,
const struct nand_op_instr *instr)
{
struct tango_chip *tchip = to_tango_chip(chip);
unsigned int i;
switch (instr->type) {
case NAND_OP_CMD_INSTR:
writeb_relaxed(instr->ctx.cmd.opcode, tchip->base + PBUS_CMD);
return 0;
case NAND_OP_ADDR_INSTR:
for (i = 0; i < instr->ctx.addr.naddrs; i++)
writeb_relaxed(instr->ctx.addr.addrs[i],
tchip->base + PBUS_ADDR);
return 0;
case NAND_OP_DATA_IN_INSTR:
ioread8_rep(tchip->base + PBUS_DATA, instr->ctx.data.buf.in,
instr->ctx.data.len);
return 0;
case NAND_OP_DATA_OUT_INSTR:
iowrite8_rep(tchip->base + PBUS_DATA, instr->ctx.data.buf.out,
instr->ctx.data.len);
return 0;
case NAND_OP_WAITRDY_INSTR:
return tango_waitrdy(chip,
instr->ctx.waitrdy.timeout_ms);
default:
break;
}
return -EINVAL;
}
static int tango_exec_op(struct nand_chip *chip,
const struct nand_operation *op,
bool check_only)
{
unsigned int i;
int ret = 0;
if (check_only)
return 0;
tango_select_target(chip, op->cs);
for (i = 0; i < op->ninstrs; i++) {
ret = tango_exec_instr(chip, &op->instrs[i]);
if (ret)
break;
}
return ret;
}
/*
* The controller does not check for bitflips in erased pages,
* therefore software must check instead.
*/
static int check_erased_page(struct nand_chip *chip, u8 *buf)
{
struct mtd_info *mtd = nand_to_mtd(chip);
u8 *meta = chip->oob_poi + BBM_SIZE;
u8 *ecc = chip->oob_poi + BBM_SIZE + METADATA_SIZE;
const int ecc_size = chip->ecc.bytes;
const int pkt_size = chip->ecc.size;
int i, res, meta_len, bitflips = 0;
for (i = 0; i < chip->ecc.steps; ++i) {
meta_len = i ? 0 : METADATA_SIZE;
res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size,
meta, meta_len,
chip->ecc.strength);
if (res < 0)
mtd->ecc_stats.failed++;
else
mtd->ecc_stats.corrected += res;
bitflips = max(res, bitflips);
buf += pkt_size;
ecc += ecc_size;
}
return bitflips;
}
static int decode_error_report(struct nand_chip *chip)
{
u32 status, res;
struct mtd_info *mtd = nand_to_mtd(chip);
struct tango_nfc *nfc = to_tango_nfc(chip->controller);
status = readl_relaxed(nfc->reg_base + NFC_XFER_STATUS);
if (status & PAGE_IS_EMPTY)
return 0;
res = readl_relaxed(nfc->mem_base + ERROR_REPORT);
if (DECODE_FAIL_PKT_0(res) || DECODE_FAIL_PKT_N(res))
return -EBADMSG;
/* ERR_COUNT_PKT_N is max, not sum, but that's all we have */
mtd->ecc_stats.corrected +=
ERR_COUNT_PKT_0(res) + ERR_COUNT_PKT_N(res);
return max(ERR_COUNT_PKT_0(res), ERR_COUNT_PKT_N(res));
}
static void tango_dma_callback(void *arg)
{
complete(arg);
}
static int do_dma(struct tango_nfc *nfc, enum dma_data_direction dir, int cmd,
const void *buf, int len, int page)
{
void __iomem *addr = nfc->reg_base + NFC_STATUS;
struct dma_chan *chan = nfc->chan;
struct dma_async_tx_descriptor *desc;
enum dma_transfer_direction tdir;
struct scatterlist sg;
struct completion tx_done;
int err = -EIO;
u32 res, val;
sg_init_one(&sg, buf, len);
if (dma_map_sg(chan->device->dev, &sg, 1, dir) != 1)
return -EIO;
tdir = dir == DMA_TO_DEVICE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
desc = dmaengine_prep_slave_sg(chan, &sg, 1, tdir, DMA_PREP_INTERRUPT);
if (!desc)
goto dma_unmap;
desc->callback = tango_dma_callback;
desc->callback_param = &tx_done;
init_completion(&tx_done);
writel_relaxed(MODE_NFC, nfc->pbus_base + PBUS_PAD_MODE);
writel_relaxed(page, nfc->reg_base + NFC_ADDR_PAGE);
writel_relaxed(0, nfc->reg_base + NFC_ADDR_OFFSET);
writel_relaxed(cmd, nfc->reg_base + NFC_FLASH_CMD);
dmaengine_submit(desc);
dma_async_issue_pending(chan);
res = wait_for_completion_timeout(&tx_done, HZ);
if (res > 0)
err = readl_poll_timeout(addr, val, val & CMD_READY, 0, 1000);
writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE);
dma_unmap:
dma_unmap_sg(chan->device->dev, &sg, 1, dir);
return err;
}
static int tango_read_page(struct nand_chip *chip, u8 *buf,
int oob_required, int page)
{
struct mtd_info *mtd = nand_to_mtd(chip);
struct tango_nfc *nfc = to_tango_nfc(chip->controller);
int err, res, len = mtd->writesize;
tango_select_target(chip, chip->cur_cs);
if (oob_required)
chip->ecc.read_oob(chip, page);
err = do_dma(nfc, DMA_FROM_DEVICE, NFC_READ, buf, len, page);
if (err)
return err;
res = decode_error_report(chip);
if (res < 0) {
chip->ecc.read_oob_raw(chip, page);
res = check_erased_page(chip, buf);
}
return res;
}
static int tango_write_page(struct nand_chip *chip, const u8 *buf,
int oob_required, int page)
{
struct mtd_info *mtd = nand_to_mtd(chip);
struct tango_nfc *nfc = to_tango_nfc(chip->controller);
const struct nand_sdr_timings *timings;
int err, len = mtd->writesize;
u8 status;
/* Calling tango_write_oob() would send PAGEPROG twice */
if (oob_required)
return -ENOTSUPP;
tango_select_target(chip, chip->cur_cs);
writel_relaxed(0xffffffff, nfc->mem_base + METADATA);
err = do_dma(nfc, DMA_TO_DEVICE, NFC_WRITE, buf, len, page);
if (err)
return err;
timings = nand_get_sdr_timings(nand_get_interface_config(chip));
err = tango_waitrdy(chip, PSEC_TO_MSEC(timings->tR_max));
if (err)
return err;
err = nand_status_op(chip, &status);
if (err)
return err;
return (status & NAND_STATUS_FAIL) ? -EIO : 0;
}
static void aux_read(struct nand_chip *chip, u8 **buf, int len, int *pos)
{
*pos += len;
if (!*buf) {
/* skip over "len" bytes */
nand_change_read_column_op(chip, *pos, NULL, 0, false);
} else {
struct tango_chip *tchip = to_tango_chip(chip);
ioread8_rep(tchip->base + PBUS_DATA, *buf, len);
*buf += len;
}
}
static void aux_write(struct nand_chip *chip, const u8 **buf, int len, int *pos)
{
*pos += len;
if (!*buf) {
/* skip over "len" bytes */
nand_change_write_column_op(chip, *pos, NULL, 0, false);
} else {
struct tango_chip *tchip = to_tango_chip(chip);
iowrite8_rep(tchip->base + PBUS_DATA, *buf, len);
*buf += len;
}
}
/*
* Physical page layout (not drawn to scale)
*
* NB: Bad Block Marker area splits PKT_N in two (N1, N2).
*
* +---+-----------------+-------+-----+-----------+-----+----+-------+
* | M | PKT_0 | ECC_0 | ... | N1 | BBM | N2 | ECC_N |
* +---+-----------------+-------+-----+-----------+-----+----+-------+
*
* Logical page layout:
*
* +-----+---+-------+-----+-------+
* oob = | BBM | M | ECC_0 | ... | ECC_N |
* +-----+---+-------+-----+-------+
*
* +-----------------+-----+-----------------+
* buf = | PKT_0 | ... | PKT_N |
* +-----------------+-----+-----------------+
*/
static void raw_read(struct nand_chip *chip, u8 *buf, u8 *oob)
{
struct mtd_info *mtd = nand_to_mtd(chip);
u8 *oob_orig = oob;
const int page_size = mtd->writesize;
const int ecc_size = chip->ecc.bytes;
const int pkt_size = chip->ecc.size;
int pos = 0; /* position within physical page */
int rem = page_size; /* bytes remaining until BBM area */
if (oob)
oob += BBM_SIZE;
aux_read(chip, &oob, METADATA_SIZE, &pos);
while (rem > pkt_size) {
aux_read(chip, &buf, pkt_size, &pos);
aux_read(chip, &oob, ecc_size, &pos);
rem = page_size - pos;
}
aux_read(chip, &buf, rem, &pos);
aux_read(chip, &oob_orig, BBM_SIZE, &pos);
aux_read(chip, &buf, pkt_size - rem, &pos);
aux_read(chip, &oob, ecc_size, &pos);
}
static void raw_write(struct nand_chip *chip, const u8 *buf, const u8 *oob)
{
struct mtd_info *mtd = nand_to_mtd(chip);
const u8 *oob_orig = oob;
const int page_size = mtd->writesize;
const int ecc_size = chip->ecc.bytes;
const int pkt_size = chip->ecc.size;
int pos = 0; /* position within physical page */
int rem = page_size; /* bytes remaining until BBM area */
if (oob)
oob += BBM_SIZE;
aux_write(chip, &oob, METADATA_SIZE, &pos);
while (rem > pkt_size) {
aux_write(chip, &buf, pkt_size, &pos);
aux_write(chip, &oob, ecc_size, &pos);
rem = page_size - pos;
}
aux_write(chip, &buf, rem, &pos);
aux_write(chip, &oob_orig, BBM_SIZE, &pos);
aux_write(chip, &buf, pkt_size - rem, &pos);
aux_write(chip, &oob, ecc_size, &pos);
}
static int tango_read_page_raw(struct nand_chip *chip, u8 *buf,
int oob_required, int page)
{
tango_select_target(chip, chip->cur_cs);
nand_read_page_op(chip, page, 0, NULL, 0);
raw_read(chip, buf, chip->oob_poi);
return 0;
}
static int tango_write_page_raw(struct nand_chip *chip, const u8 *buf,
int oob_required, int page)
{
tango_select_target(chip, chip->cur_cs);
nand_prog_page_begin_op(chip, page, 0, NULL, 0);
raw_write(chip, buf, chip->oob_poi);
return nand_prog_page_end_op(chip);
}
static int tango_read_oob(struct nand_chip *chip, int page)
{
tango_select_target(chip, chip->cur_cs);
nand_read_page_op(chip, page, 0, NULL, 0);
raw_read(chip, NULL, chip->oob_poi);
return 0;
}
static int tango_write_oob(struct nand_chip *chip, int page)
{
tango_select_target(chip, chip->cur_cs);
nand_prog_page_begin_op(chip, page, 0, NULL, 0);
raw_write(chip, NULL, chip->oob_poi);
return nand_prog_page_end_op(chip);
}
static int oob_ecc(struct mtd_info *mtd, int idx, struct mtd_oob_region *res)
{
struct nand_chip *chip = mtd_to_nand(mtd);
struct nand_ecc_ctrl *ecc = &chip->ecc;
if (idx >= ecc->steps)
return -ERANGE;
res->offset = BBM_SIZE + METADATA_SIZE + ecc->bytes * idx;
res->length = ecc->bytes;
return 0;
}
static int oob_free(struct mtd_info *mtd, int idx, struct mtd_oob_region *res)
{
return -ERANGE; /* no free space in spare area */
}
static const struct mtd_ooblayout_ops tango_nand_ooblayout_ops = {
.ecc = oob_ecc,
.free = oob_free,
};
static u32 to_ticks(int kHz, int ps)
{
return DIV_ROUND_UP_ULL((u64)kHz * ps, NSEC_PER_SEC);
}
static int tango_set_timings(struct nand_chip *chip, int csline,
const struct nand_interface_config *conf)
{
const struct nand_sdr_timings *sdr = nand_get_sdr_timings(conf);
struct tango_nfc *nfc = to_tango_nfc(chip->controller);
struct tango_chip *tchip = to_tango_chip(chip);
u32 Trdy, Textw, Twc, Twpw, Tacc, Thold, Trpw, Textr;
int kHz = nfc->freq_kHz;
if (IS_ERR(sdr))
return PTR_ERR(sdr);
if (csline == NAND_DATA_IFACE_CHECK_ONLY)
return 0;
Trdy = to_ticks(kHz, sdr->tCEA_max - sdr->tREA_max);
Textw = to_ticks(kHz, sdr->tWB_max);
Twc = to_ticks(kHz, sdr->tWC_min);
Twpw = to_ticks(kHz, sdr->tWC_min - sdr->tWP_min);
Tacc = to_ticks(kHz, sdr->tREA_max);
Thold = to_ticks(kHz, sdr->tREH_min);
Trpw = to_ticks(kHz, sdr->tRC_min - sdr->tREH_min);
Textr = to_ticks(kHz, sdr->tRHZ_max);
tchip->timing1 = TIMING(Trdy, Textw, Twc, Twpw);
tchip->timing2 = TIMING(Tacc, Thold, Trpw, Textr);
return 0;
}
static int tango_attach_chip(struct nand_chip *chip)
{
struct nand_ecc_ctrl *ecc = &chip->ecc;
ecc->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
ecc->algo = NAND_ECC_ALGO_BCH;
ecc->bytes = DIV_ROUND_UP(ecc->strength * FIELD_ORDER, BITS_PER_BYTE);
ecc->read_page_raw = tango_read_page_raw;
ecc->write_page_raw = tango_write_page_raw;
ecc->read_page = tango_read_page;
ecc->write_page = tango_write_page;
ecc->read_oob = tango_read_oob;
ecc->write_oob = tango_write_oob;
return 0;
}
static const struct nand_controller_ops tango_controller_ops = {
.attach_chip = tango_attach_chip,
.setup_interface = tango_set_timings,
.exec_op = tango_exec_op,
};
static int chip_init(struct device *dev, struct device_node *np)
{
u32 cs;
int err, res;
struct mtd_info *mtd;
struct nand_chip *chip;
struct tango_chip *tchip;
struct nand_ecc_ctrl *ecc;
struct tango_nfc *nfc = dev_get_drvdata(dev);
tchip = devm_kzalloc(dev, sizeof(*tchip), GFP_KERNEL);
if (!tchip)
return -ENOMEM;
res = of_property_count_u32_elems(np, "reg");
if (res < 0)
return res;
if (res != 1)
return -ENOTSUPP; /* Multi-CS chips are not supported */
err = of_property_read_u32_index(np, "reg", 0, &cs);
if (err)
return err;
if (cs >= MAX_CS)
return -EINVAL;
chip = &tchip->nand_chip;
ecc = &chip->ecc;
mtd = nand_to_mtd(chip);
chip->options = NAND_USES_DMA |
NAND_NO_SUBPAGE_WRITE |
NAND_WAIT_TCCS;
chip->controller = &nfc->hw;
tchip->base = nfc->pbus_base + (cs * 256);
nand_set_flash_node(chip, np);
mtd_set_ooblayout(mtd, &tango_nand_ooblayout_ops);
mtd->dev.parent = dev;
err = nand_scan(chip, 1);
if (err)
return err;
tchip->xfer_cfg = XFER_CFG(cs, 1, ecc->steps, METADATA_SIZE);
tchip->pkt_0_cfg = PKT_CFG(ecc->size + METADATA_SIZE, ecc->strength);
tchip->pkt_n_cfg = PKT_CFG(ecc->size, ecc->strength);
tchip->bb_cfg = BB_CFG(mtd->writesize, BBM_SIZE);
err = mtd_device_register(mtd, NULL, 0);
if (err) {
nand_cleanup(chip);
return err;
}
nfc->chips[cs] = tchip;
return 0;
}
static int tango_nand_remove(struct platform_device *pdev)
{
struct tango_nfc *nfc = platform_get_drvdata(pdev);
struct nand_chip *chip;
int cs, ret;
dma_release_channel(nfc->chan);
for (cs = 0; cs < MAX_CS; ++cs) {
if (nfc->chips[cs]) {
chip = &nfc->chips[cs]->nand_chip;
ret = mtd_device_unregister(nand_to_mtd(chip));
WARN_ON(ret);
nand_cleanup(chip);
}
}
return 0;
}
static int tango_nand_probe(struct platform_device *pdev)
{
int err;
struct clk *clk;
struct resource *res;
struct tango_nfc *nfc;
struct device_node *np;
nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL);
if (!nfc)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
nfc->reg_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(nfc->reg_base))
return PTR_ERR(nfc->reg_base);
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
nfc->mem_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(nfc->mem_base))
return PTR_ERR(nfc->mem_base);
res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
nfc->pbus_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(nfc->pbus_base))
return PTR_ERR(nfc->pbus_base);
writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE);
clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(clk))
return PTR_ERR(clk);
nfc->chan = dma_request_chan(&pdev->dev, "rxtx");
if (IS_ERR(nfc->chan))
return PTR_ERR(nfc->chan);
platform_set_drvdata(pdev, nfc);
nand_controller_init(&nfc->hw);
nfc->hw.ops = &tango_controller_ops;
nfc->freq_kHz = clk_get_rate(clk) / 1000;
for_each_child_of_node(pdev->dev.of_node, np) {
err = chip_init(&pdev->dev, np);
if (err) {
tango_nand_remove(pdev);
of_node_put(np);
return err;
}
}
return 0;
}
static const struct of_device_id tango_nand_ids[] = {
{ .compatible = "sigma,smp8758-nand" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, tango_nand_ids);
static struct platform_driver tango_nand_driver = {
.probe = tango_nand_probe,
.remove = tango_nand_remove,
.driver = {
.name = "tango-nand",
.of_match_table = tango_nand_ids,
},
};
module_platform_driver(tango_nand_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Sigma Designs");
MODULE_DESCRIPTION("Tango4 NAND Flash controller driver");

8
drivers/mtd/parsers/Kconfig
View File

@ -160,3 +160,11 @@ config MTD_REDBOOT_PARTS_READONLY
'FIS directory' images, enable this option.
endif # MTD_REDBOOT_PARTS
config MTD_QCOMSMEM_PARTS
tristate "Qualcomm SMEM NAND flash partition parser"
depends on MTD_NAND_QCOM || COMPILE_TEST
depends on QCOM_SMEM
help
This provides support for parsing partitions from Shared Memory (SMEM)
for NAND flash on Qualcomm platforms.

1
drivers/mtd/parsers/Makefile
View File

@ -9,3 +9,4 @@ obj-$(CONFIG_MTD_AFS_PARTS) += afs.o
obj-$(CONFIG_MTD_PARSER_TRX) += parser_trx.o
obj-$(CONFIG_MTD_SHARPSL_PARTS) += sharpslpart.o
obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o
obj-$(CONFIG_MTD_QCOMSMEM_PARTS) += qcomsmempart.o

4
drivers/mtd/parsers/afs.c
View File

@ -370,10 +370,8 @@ static int parse_afs_partitions(struct mtd_info *mtd,
return i;
out_free_parts:
while (i >= 0) {
while (--i >= 0)
kfree(parts[i].name);
i--;
}
kfree(parts);
*pparts = NULL;
return ret;

4
drivers/mtd/parsers/parser_imagetag.c
View File

@ -83,6 +83,7 @@ static int bcm963xx_parse_imagetag_partitions(struct mtd_info *master,
pr_err("invalid rootfs address: %*ph\n",
(int)sizeof(buf->flash_image_start),
buf->flash_image_start);
ret = -EINVAL;
goto out;
}
@ -92,6 +93,7 @@ static int bcm963xx_parse_imagetag_partitions(struct mtd_info *master,
pr_err("invalid kernel address: %*ph\n",
(int)sizeof(buf->kernel_address),
buf->kernel_address);
ret = -EINVAL;
goto out;
}
@ -100,6 +102,7 @@ static int bcm963xx_parse_imagetag_partitions(struct mtd_info *master,
pr_err("invalid kernel length: %*ph\n",
(int)sizeof(buf->kernel_length),
buf->kernel_length);
ret = -EINVAL;
goto out;
}
@ -108,6 +111,7 @@ static int bcm963xx_parse_imagetag_partitions(struct mtd_info *master,
pr_err("invalid total length: %*ph\n",
(int)sizeof(buf->total_length),
buf->total_length);
ret = -EINVAL;
goto out;
}

170
drivers/mtd/parsers/qcomsmempart.c Normal file
View File

@ -0,0 +1,170 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Qualcomm SMEM NAND flash partition parser
*
* Copyright (C) 2020, Linaro Ltd.
*/
#include <linux/ctype.h>
#include <linux/module.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/slab.h>
#include <linux/soc/qcom/smem.h>
#define SMEM_AARM_PARTITION_TABLE 9
#define SMEM_APPS 0
#define SMEM_FLASH_PART_MAGIC1 0x55ee73aa
#define SMEM_FLASH_PART_MAGIC2 0xe35ebddb
#define SMEM_FLASH_PTABLE_V3 3
#define SMEM_FLASH_PTABLE_V4 4
#define SMEM_FLASH_PTABLE_MAX_PARTS_V3 16
#define SMEM_FLASH_PTABLE_MAX_PARTS_V4 48
#define SMEM_FLASH_PTABLE_HDR_LEN (4 * sizeof(u32))
#define SMEM_FLASH_PTABLE_NAME_SIZE 16
/**
* struct smem_flash_pentry - SMEM Flash partition entry
* @name: Name of the partition
* @offset: Offset in blocks
* @length: Length of the partition in blocks
* @attr: Flags for this partition
*/
struct smem_flash_pentry {
char name[SMEM_FLASH_PTABLE_NAME_SIZE];
__le32 offset;
__le32 length;
u8 attr;
} __packed __aligned(4);
/**
* struct smem_flash_ptable - SMEM Flash partition table
* @magic1: Partition table Magic 1
* @magic2: Partition table Magic 2
* @version: Partition table version
* @numparts: Number of partitions in this ptable
* @pentry: Flash partition entries belonging to this ptable
*/
struct smem_flash_ptable {
__le32 magic1;
__le32 magic2;
__le32 version;
__le32 numparts;
struct smem_flash_pentry pentry[SMEM_FLASH_PTABLE_MAX_PARTS_V4];
} __packed __aligned(4);
static int parse_qcomsmem_part(struct mtd_info *mtd,
const struct mtd_partition **pparts,
struct mtd_part_parser_data *data)
{
struct smem_flash_pentry *pentry;
struct smem_flash_ptable *ptable;
size_t len = SMEM_FLASH_PTABLE_HDR_LEN;
struct mtd_partition *parts;
int ret, i, numparts;
char *name, *c;
pr_debug("Parsing partition table info from SMEM\n");
ptable = qcom_smem_get(SMEM_APPS, SMEM_AARM_PARTITION_TABLE, &len);
if (IS_ERR(ptable)) {
pr_err("Error reading partition table header\n");
return PTR_ERR(ptable);
}
/* Verify ptable magic */
if (le32_to_cpu(ptable->magic1) != SMEM_FLASH_PART_MAGIC1 ||
le32_to_cpu(ptable->magic2) != SMEM_FLASH_PART_MAGIC2) {
pr_err("Partition table magic verification failed\n");
return -EINVAL;
}
/* Ensure that # of partitions is less than the max we have allocated */
numparts = le32_to_cpu(ptable->numparts);
if (numparts > SMEM_FLASH_PTABLE_MAX_PARTS_V4) {
pr_err("Partition numbers exceed the max limit\n");
return -EINVAL;
}
/* Find out length of partition data based on table version */
if (le32_to_cpu(ptable->version) <= SMEM_FLASH_PTABLE_V3) {
len = SMEM_FLASH_PTABLE_HDR_LEN + SMEM_FLASH_PTABLE_MAX_PARTS_V3 *
sizeof(struct smem_flash_pentry);
} else if (le32_to_cpu(ptable->version) == SMEM_FLASH_PTABLE_V4) {
len = SMEM_FLASH_PTABLE_HDR_LEN + SMEM_FLASH_PTABLE_MAX_PARTS_V4 *
sizeof(struct smem_flash_pentry);
} else {
pr_err("Unknown ptable version (%d)", le32_to_cpu(ptable->version));
return -EINVAL;
}
/*
* Now that the partition table header has been parsed, verified
* and the length of the partition table calculated, read the
* complete partition table
*/
ptable = qcom_smem_get(SMEM_APPS, SMEM_AARM_PARTITION_TABLE, &len);
if (IS_ERR_OR_NULL(ptable)) {
pr_err("Error reading partition table\n");
return PTR_ERR(ptable);
}
parts = kcalloc(numparts, sizeof(*parts), GFP_KERNEL);
if (!parts)
return -ENOMEM;
for (i = 0; i < numparts; i++) {
pentry = &ptable->pentry[i];
if (pentry->name[0] == '\0')
continue;
name = kstrdup(pentry->name, GFP_KERNEL);
if (!name) {
ret = -ENOMEM;
goto out_free_parts;
}
/* Convert name to lower case */
for (c = name; *c != '\0'; c++)
*c = tolower(*c);
parts[i].name = name;
parts[i].offset = le32_to_cpu(pentry->offset) * mtd->erasesize;
parts[i].mask_flags = pentry->attr;
parts[i].size = le32_to_cpu(pentry->length) * mtd->erasesize;
pr_debug("%d: %s offs=0x%08x size=0x%08x attr:0x%08x\n",
i, pentry->name, le32_to_cpu(pentry->offset),
le32_to_cpu(pentry->length), pentry->attr);
}
pr_debug("SMEM partition table found: ver: %d len: %d\n",
le32_to_cpu(ptable->version), numparts);
*pparts = parts;
return numparts;
out_free_parts:
while (--i >= 0)
kfree(parts[i].name);
kfree(parts);
*pparts = NULL;
return ret;
}
static const struct of_device_id qcomsmem_of_match_table[] = {
{ .compatible = "qcom,smem-part" },
{},
};
MODULE_DEVICE_TABLE(of, qcomsmem_of_match_table);
static struct mtd_part_parser mtd_parser_qcomsmem = {
.parse_fn = parse_qcomsmem_part,
.name = "qcomsmem",
.of_match_table = qcomsmem_of_match_table,
};
module_mtd_part_parser(mtd_parser_qcomsmem);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
MODULE_DESCRIPTION("Qualcomm SMEM NAND flash partition parser");

4
drivers/mtd/spi-nor/controllers/hisi-sfc.c
View File

@ -399,8 +399,10 @@ static int hisi_spi_nor_register_all(struct hifmc_host *host)
for_each_available_child_of_node(dev->of_node, np) {
ret = hisi_spi_nor_register(np, host);
if (ret)
if (ret) {
of_node_put(np);
goto fail;
}
if (host->num_chip == HIFMC_MAX_CHIP_NUM) {
dev_warn(dev, "Flash device number exceeds the maximum chipselect number\n");

1
drivers/mtd/spi-nor/controllers/intel-spi-pci.c
View File

@ -73,6 +73,7 @@ static const struct pci_device_id intel_spi_pci_ids[] = {
{ PCI_VDEVICE(INTEL, 0x43a4), (unsigned long)&cnl_info },
{ PCI_VDEVICE(INTEL, 0x4b24), (unsigned long)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x4da4), (unsigned long)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x51a4), (unsigned long)&cnl_info },
{ PCI_VDEVICE(INTEL, 0x7aa4), (unsigned long)&cnl_info },
{ PCI_VDEVICE(INTEL, 0xa0a4), (unsigned long)&bxt_info },
{ PCI_VDEVICE(INTEL, 0xa1a4), (unsigned long)&bxt_info },

49
drivers/mtd/spi-nor/core.c
View File

@ -465,7 +465,7 @@ static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
*
* Return: 0 on success, -errno otherwise.
*/
static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
{
int ret;
@ -853,6 +853,43 @@ int spi_nor_wait_till_ready(struct spi_nor *nor)
DEFAULT_READY_WAIT_JIFFIES);
}
/**
* spi_nor_global_block_unlock() - Unlock Global Block Protection.
* @nor: pointer to 'struct spi_nor'.
*
* Return: 0 on success, -errno otherwise.
*/
int spi_nor_global_block_unlock(struct spi_nor *nor)
{
int ret;
ret = spi_nor_write_enable(nor);
if (ret)
return ret;
if (nor->spimem) {
struct spi_mem_op op =
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_GBULK, 0),
SPI_MEM_OP_NO_ADDR,
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_NO_DATA);
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_GBULK,
NULL, 0);
}
if (ret) {
dev_dbg(nor->dev, "error %d on Global Block Unlock\n", ret);
return ret;
}
return spi_nor_wait_till_ready(nor);
}
/**
* spi_nor_write_sr() - Write the Status Register.
* @nor: pointer to 'struct spi_nor'.
@ -1364,14 +1401,15 @@ spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map,
erase = &map->erase_type[i];
/* Alignment is not mandatory for overlaid regions */
if (region->offset & SNOR_OVERLAID_REGION &&
region->size <= len)
return erase;
/* Don't erase more than what the user has asked for. */
if (erase->size > len)
continue;
/* Alignment is not mandatory for overlaid regions */
if (region->offset & SNOR_OVERLAID_REGION)
return erase;
spi_nor_div_by_erase_size(erase, addr, &rem);
if (rem)
continue;
@ -1515,6 +1553,7 @@ static int spi_nor_init_erase_cmd_list(struct spi_nor *nor,
goto destroy_erase_cmd_list;
if (prev_erase != erase ||
erase->size != cmd->size ||
region->offset & SNOR_OVERLAID_REGION) {
cmd = spi_nor_init_erase_cmd(region, erase);
if (IS_ERR(cmd)) {

2
drivers/mtd/spi-nor/core.h
View File

@ -434,12 +434,14 @@ int spi_nor_write_disable(struct spi_nor *nor);
int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable);
int spi_nor_write_ear(struct spi_nor *nor, u8 ear);
int spi_nor_wait_till_ready(struct spi_nor *nor);
int spi_nor_global_block_unlock(struct spi_nor *nor);
int spi_nor_lock_and_prep(struct spi_nor *nor);
void spi_nor_unlock_and_unprep(struct spi_nor *nor);
int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor);
int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor);
int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor);
int spi_nor_read_sr(struct spi_nor *nor, u8 *sr);
int spi_nor_read_cr(struct spi_nor *nor, u8 *cr);
int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len);
int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1);

5
drivers/mtd/spi-nor/sfdp.c
View File

@ -788,7 +788,7 @@ spi_nor_region_check_overlay(struct spi_nor_erase_region *region,
int i;
for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
if (!(erase_type & BIT(i)))
if (!(erase[i].size && erase_type & BIT(erase[i].idx)))
continue;
if (region->size & erase[i].size_mask) {
spi_nor_region_mark_overlay(region);
@ -858,6 +858,7 @@ spi_nor_init_non_uniform_erase_map(struct spi_nor *nor,
offset = (region[i].offset & ~SNOR_ERASE_FLAGS_MASK) +
region[i].size;
}
spi_nor_region_mark_end(&region[i - 1]);
save_uniform_erase_type = map->uniform_erase_type;
map->uniform_erase_type = spi_nor_sort_erase_mask(map,
@ -881,8 +882,6 @@ spi_nor_init_non_uniform_erase_map(struct spi_nor *nor,
if (!(regions_erase_type & BIT(erase[i].idx)))
spi_nor_set_erase_type(&erase[i], 0, 0xFF);
spi_nor_region_mark_end(&region[i - 1]);
return 0;
}

52
drivers/mtd/spi-nor/sst.c
View File

@ -8,6 +8,53 @@
#include "core.h"
#define SST26VF_CR_BPNV BIT(3)
static int sst26vf_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
{
return -EOPNOTSUPP;
}
static int sst26vf_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
{
int ret;
/* We only support unlocking the entire flash array. */
if (ofs != 0 || len != nor->params->size)
return -EINVAL;
ret = spi_nor_read_cr(nor, nor->bouncebuf);
if (ret)
return ret;
if (!(nor->bouncebuf[0] & SST26VF_CR_BPNV)) {
dev_dbg(nor->dev, "Any block has been permanently locked\n");
return -EINVAL;
}
return spi_nor_global_block_unlock(nor);
}
static int sst26vf_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
{
return -EOPNOTSUPP;
}
static const struct spi_nor_locking_ops sst26vf_locking_ops = {
.lock = sst26vf_lock,
.unlock = sst26vf_unlock,
.is_locked = sst26vf_is_locked,
};
static void sst26vf_default_init(struct spi_nor *nor)
{
nor->params->locking_ops = &sst26vf_locking_ops;
}
static const struct spi_nor_fixups sst26vf_fixups = {
.default_init = sst26vf_default_init,
};
static const struct flash_info sst_parts[] = {
/* SST -- large erase sizes are "overlays", "sectors" are 4K */
{ "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8,
@ -39,8 +86,9 @@ static const struct flash_info sst_parts[] = {
{ "sst26vf016b", INFO(0xbf2641, 0, 64 * 1024, 32,
SECT_4K | SPI_NOR_DUAL_READ) },
{ "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128,
SECT_4K | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ) },
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE)
.fixups = &sst26vf_fixups },
};
static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,

1
include/linux/mtd/spi-nor.h
View File

@ -53,6 +53,7 @@
#define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
#define SPINOR_OP_SRSTEN 0x66 /* Software Reset Enable */
#define SPINOR_OP_SRST 0x99 /* Software Reset */
#define SPINOR_OP_GBULK 0x98 /* Global Block Unlock */
/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
#define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */