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clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks
HDMI driver must re-parent respective muxes during HDMI-PHY on/off to HDMI-PHY output clocks. To reference those clocks their definitions should be added. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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@ -2614,8 +2614,10 @@ static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = {
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FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT,
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100000000),
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/* PHY clocks from HDMI_PHY */
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FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 300000000),
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FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 166000000),
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FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
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NULL, CLK_IS_ROOT, 300000000),
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FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy",
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NULL, CLK_IS_ROOT, 166000000),
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};
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static struct samsung_mux_clock disp_mux_clks[] __initdata = {
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@ -765,7 +765,10 @@
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#define CLK_SCLK_RGB_VCLK 109
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#define CLK_SCLK_RGB_TV_VCLK 110
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#define DISP_NR_CLK 111
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#define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY 111
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#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY 112
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#define DISP_NR_CLK 113
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/* CMU_AUD */
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#define CLK_MOUT_AUD_PLL_USER 1
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