renegade-project/linux-next
2
0
Fork 0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-21 03:33:59 +08:00
Code

ALSA: ice1724 - Re-fix IRQ mask initialization

Browse Source 
The previous IRQ mask initialization was wrong.  It must set the bits
to be masked.

Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Takashi Iwai 2008-11-05 17:41:23 +01:00
parent 4074ea2149
commit 6834d7ce22
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
sound/pci/ice1712/ice1724.c
View File

@ -395,8 +395,8 @@ static irqreturn_t snd_vt1724_interrupt(int irq, void *dev_id)
"status = 0x%x\n", status); "status = 0x%x\n", status);
if (status & VT1724_IRQ_MPU_TX) { if (status & VT1724_IRQ_MPU_TX) {
printk(KERN_ERR "ice1724: Disabling MPU_TX\n"); printk(KERN_ERR "ice1724: Disabling MPU_TX\n");
outb(inb(ICEREG1724(ice, IRQMASK)) & outb(inb(ICEREG1724(ice, IRQMASK)) |
~VT1724_IRQ_MPU_TX, VT1724_IRQ_MPU_TX,
ICEREG1724(ice, IRQMASK)); ICEREG1724(ice, IRQMASK));
} }
break; break;
@ -2413,8 +2413,8 @@ static int __devinit snd_vt1724_create(struct snd_card *card,
return -EIO; return -EIO;
} }
/* clear interrupts -- otherwise you'll get irq problems later */ /* MPU_RX and TX irq masks are cleared later dynamically */
outb(0, ICEREG1724(ice, IRQMASK)); outb(VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX , ICEREG1724(ice, IRQMASK));
/* don't handle FIFO overrun/underruns (just yet), /* don't handle FIFO overrun/underruns (just yet),
* since they cause machine lockups * since they cause machine lockups