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https://github.com/edk2-porting/linux-next.git
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Merge branch 'pci/host-iproc' into next
* pci/host-iproc: PCI: Add Broadcom Northstar2 PAXC quirk for device class and MPSS PCI: iproc: Configure PCIe MPS settings PCI: iproc: Use of_device_get_match_data() to simplify probe
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commit
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@ -47,7 +47,6 @@ MODULE_DEVICE_TABLE(of, iproc_pcie_of_match_table);
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static int iproc_pcie_pltfm_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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const struct of_device_id *of_id;
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struct iproc_pcie *pcie;
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struct device_node *np = dev->of_node;
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struct resource reg;
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@ -55,16 +54,12 @@ static int iproc_pcie_pltfm_probe(struct platform_device *pdev)
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LIST_HEAD(res);
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int ret;
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of_id = of_match_device(iproc_pcie_of_match_table, dev);
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if (!of_id)
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return -EINVAL;
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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return -ENOMEM;
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pcie->dev = dev;
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pcie->type = (enum iproc_pcie_type)of_id->data;
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pcie->type = (enum iproc_pcie_type) of_device_get_match_data(dev);
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ret = of_address_to_resource(np, 0, ®);
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if (ret < 0) {
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@ -1205,7 +1205,7 @@ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
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struct device *dev;
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int ret;
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void *sysdata;
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struct pci_bus *bus;
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struct pci_bus *bus, *child;
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dev = pcie->dev;
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@ -1278,6 +1278,9 @@ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
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if (pcie->map_irq)
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pci_fixup_irqs(pci_common_swizzle, pcie->map_irq);
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list_for_each_entry(child, &bus->children, node)
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pcie_bus_configure_settings(child);
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pci_bus_add_devices(bus);
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return 0;
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@ -2240,6 +2240,27 @@ DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
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PCI_DEVICE_ID_TIGON3_5719,
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quirk_brcm_5719_limit_mrrs);
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#ifdef CONFIG_PCIE_IPROC_PLATFORM
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static void quirk_paxc_bridge(struct pci_dev *pdev)
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{
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/* The PCI config space is shared with the PAXC root port and the first
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* Ethernet device. So, we need to workaround this by telling the PCI
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* code that the bridge is not an Ethernet device.
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*/
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if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
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pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
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/* MPSS is not being set properly (as it is currently 0). This is
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* because that area of the PCI config space is hard coded to zero, and
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* is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS)
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* so that the MPS can be set to the real max value.
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*/
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pdev->pcie_mpss = 2;
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
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#endif
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/* Originally in EDAC sources for i82875P:
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* Intel tells BIOS developers to hide device 6 which
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* configures the overflow device access containing
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