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https://github.com/edk2-porting/linux-next.git
synced 2024-12-16 09:13:55 +08:00
nd_blk: change aperture mapping from WC to WB
This should result in a pretty sizeable performance gain for reads. For rough comparison I did some simple read testing using PMEM to compare reads of write combining (WC) mappings vs write-back (WB). This was done on a random lab machine. PMEM reads from a write combining mapping: # dd of=/dev/null if=/dev/pmem0 bs=4096 count=100000 100000+0 records in 100000+0 records out 409600000 bytes (410 MB) copied, 9.2855 s, 44.1 MB/s PMEM reads from a write-back mapping: # dd of=/dev/null if=/dev/pmem0 bs=4096 count=1000000 1000000+0 records in 1000000+0 records out 4096000000 bytes (4.1 GB) copied, 3.44034 s, 1.2 GB/s To be able to safely support a write-back aperture I needed to add support for the "read flush" _DSM flag, as outlined in the DSM spec: http://pmem.io/documents/NVDIMM_DSM_Interface_Example.pdf This flag tells the ND BLK driver that it needs to flush the cache lines associated with the aperture after the aperture is moved but before any new data is read. This ensures that any stale cache lines from the previous contents of the aperture will be discarded from the processor cache, and the new data will be read properly from the DIMM. We know that the cache lines are clean and will be discarded without any writeback because either a) the previous aperture operation was a read, and we never modified the contents of the aperture, or b) the previous aperture operation was a write and we must have written back the dirtied contents of the aperture to the DIMM before the I/O was completed. In order to add support for the "read flush" flag I needed to add a generic routine to invalidate cache lines, mmio_flush_range(). This is protected by the ARCH_HAS_MMIO_FLUSH Kconfig variable, and is currently only supported on x86. Signed-off-by: Ross Zwisler <ross.zwisler@linux.intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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e2e05394e4
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@ -28,6 +28,7 @@ config X86
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select ARCH_HAS_FAST_MULTIPLIER
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select ARCH_HAS_GCOV_PROFILE_ALL
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select ARCH_HAS_PMEM_API
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select ARCH_HAS_MMIO_FLUSH
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select ARCH_HAS_SG_CHAIN
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select ARCH_HAVE_NMI_SAFE_CMPXCHG
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select ARCH_MIGHT_HAVE_ACPI_PDC if ACPI
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@ -89,6 +89,8 @@ int set_pages_rw(struct page *page, int numpages);
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void clflush_cache_range(void *addr, unsigned int size);
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#define mmio_flush_range(addr, size) clflush_cache_range(addr, size)
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#ifdef CONFIG_DEBUG_RODATA
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void mark_rodata_ro(void);
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extern const int rodata_test_data;
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@ -248,8 +248,6 @@ static inline void flush_write_buffers(void)
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#endif
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}
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#define ARCH_MEMREMAP_PMEM MEMREMAP_WB
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#endif /* __KERNEL__ */
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extern void native_io_delay(void);
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@ -18,6 +18,8 @@
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#include <asm/cpufeature.h>
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#include <asm/special_insns.h>
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#define ARCH_MEMREMAP_PMEM MEMREMAP_WB
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#ifdef CONFIG_ARCH_HAS_PMEM_API
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/**
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* arch_memcpy_to_pmem - copy data to persistent memory
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@ -410,6 +410,7 @@ config ACPI_NFIT
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tristate "ACPI NVDIMM Firmware Interface Table (NFIT)"
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depends on PHYS_ADDR_T_64BIT
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depends on BLK_DEV
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depends on ARCH_HAS_MMIO_FLUSH
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select LIBNVDIMM
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help
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Infrastructure to probe ACPI 6 compliant platforms for
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@ -1017,7 +1017,7 @@ static u64 read_blk_stat(struct nfit_blk *nfit_blk, unsigned int bw)
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if (mmio->num_lines)
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offset = to_interleave_offset(offset, mmio);
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return readq(mmio->base + offset);
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return readq(mmio->addr.base + offset);
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}
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static void write_blk_ctl(struct nfit_blk *nfit_blk, unsigned int bw,
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@ -1042,11 +1042,11 @@ static void write_blk_ctl(struct nfit_blk *nfit_blk, unsigned int bw,
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if (mmio->num_lines)
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offset = to_interleave_offset(offset, mmio);
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writeq(cmd, mmio->base + offset);
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writeq(cmd, mmio->addr.base + offset);
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wmb_blk(nfit_blk);
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if (nfit_blk->dimm_flags & ND_BLK_DCR_LATCH)
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readq(mmio->base + offset);
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readq(mmio->addr.base + offset);
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}
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static int acpi_nfit_blk_single_io(struct nfit_blk *nfit_blk,
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@ -1078,11 +1078,16 @@ static int acpi_nfit_blk_single_io(struct nfit_blk *nfit_blk,
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}
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if (rw)
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memcpy_to_pmem(mmio->aperture + offset,
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memcpy_to_pmem(mmio->addr.aperture + offset,
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iobuf + copied, c);
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else
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else {
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if (nfit_blk->dimm_flags & ND_BLK_READ_FLUSH)
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mmio_flush_range((void __force *)
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mmio->addr.aperture + offset, c);
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memcpy_from_pmem(iobuf + copied,
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mmio->aperture + offset, c);
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mmio->addr.aperture + offset, c);
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}
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copied += c;
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len -= c;
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@ -1129,7 +1134,10 @@ static void nfit_spa_mapping_release(struct kref *kref)
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WARN_ON(!mutex_is_locked(&acpi_desc->spa_map_mutex));
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dev_dbg(acpi_desc->dev, "%s: SPA%d\n", __func__, spa->range_index);
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iounmap(spa_map->iomem);
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if (spa_map->type == SPA_MAP_APERTURE)
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memunmap((void __force *)spa_map->addr.aperture);
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else
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iounmap(spa_map->addr.base);
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release_mem_region(spa->address, spa->length);
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list_del(&spa_map->list);
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kfree(spa_map);
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@ -1175,7 +1183,7 @@ static void __iomem *__nfit_spa_map(struct acpi_nfit_desc *acpi_desc,
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spa_map = find_spa_mapping(acpi_desc, spa);
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if (spa_map) {
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kref_get(&spa_map->kref);
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return spa_map->iomem;
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return spa_map->addr.base;
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}
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spa_map = kzalloc(sizeof(*spa_map), GFP_KERNEL);
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@ -1191,20 +1199,19 @@ static void __iomem *__nfit_spa_map(struct acpi_nfit_desc *acpi_desc,
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if (!res)
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goto err_mem;
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if (type == SPA_MAP_APERTURE) {
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/*
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* TODO: memremap_pmem() support, but that requires cache
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* flushing when the aperture is moved.
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*/
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spa_map->iomem = ioremap_wc(start, n);
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} else
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spa_map->iomem = ioremap_nocache(start, n);
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spa_map->type = type;
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if (type == SPA_MAP_APERTURE)
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spa_map->addr.aperture = (void __pmem *)memremap(start, n,
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ARCH_MEMREMAP_PMEM);
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else
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spa_map->addr.base = ioremap_nocache(start, n);
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if (!spa_map->iomem)
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if (!spa_map->addr.base)
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goto err_map;
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list_add_tail(&spa_map->list, &acpi_desc->spa_maps);
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return spa_map->iomem;
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return spa_map->addr.base;
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err_map:
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release_mem_region(start, n);
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@ -1267,7 +1274,7 @@ static int acpi_nfit_blk_get_flags(struct nvdimm_bus_descriptor *nd_desc,
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nfit_blk->dimm_flags = flags.flags;
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else if (rc == -ENOTTY) {
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/* fall back to a conservative default */
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nfit_blk->dimm_flags = ND_BLK_DCR_LATCH;
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nfit_blk->dimm_flags = ND_BLK_DCR_LATCH | ND_BLK_READ_FLUSH;
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rc = 0;
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} else
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rc = -ENXIO;
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@ -1307,9 +1314,9 @@ static int acpi_nfit_blk_region_enable(struct nvdimm_bus *nvdimm_bus,
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/* map block aperture memory */
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nfit_blk->bdw_offset = nfit_mem->bdw->offset;
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mmio = &nfit_blk->mmio[BDW];
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mmio->base = nfit_spa_map(acpi_desc, nfit_mem->spa_bdw,
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mmio->addr.base = nfit_spa_map(acpi_desc, nfit_mem->spa_bdw,
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SPA_MAP_APERTURE);
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if (!mmio->base) {
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if (!mmio->addr.base) {
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dev_dbg(dev, "%s: %s failed to map bdw\n", __func__,
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nvdimm_name(nvdimm));
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return -ENOMEM;
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@ -1330,9 +1337,9 @@ static int acpi_nfit_blk_region_enable(struct nvdimm_bus *nvdimm_bus,
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nfit_blk->cmd_offset = nfit_mem->dcr->command_offset;
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nfit_blk->stat_offset = nfit_mem->dcr->status_offset;
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mmio = &nfit_blk->mmio[DCR];
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mmio->base = nfit_spa_map(acpi_desc, nfit_mem->spa_dcr,
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mmio->addr.base = nfit_spa_map(acpi_desc, nfit_mem->spa_dcr,
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SPA_MAP_CONTROL);
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if (!mmio->base) {
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if (!mmio->addr.base) {
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dev_dbg(dev, "%s: %s failed to map dcr\n", __func__,
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nvdimm_name(nvdimm));
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return -ENOMEM;
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@ -1399,7 +1406,7 @@ static void acpi_nfit_blk_region_disable(struct nvdimm_bus *nvdimm_bus,
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for (i = 0; i < 2; i++) {
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struct nfit_blk_mmio *mmio = &nfit_blk->mmio[i];
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if (mmio->base)
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if (mmio->addr.base)
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nfit_spa_unmap(acpi_desc, mmio->spa);
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}
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nd_blk_region_set_provider_data(ndbr, NULL);
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@ -41,6 +41,7 @@ enum nfit_uuids {
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};
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enum {
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ND_BLK_READ_FLUSH = 1,
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ND_BLK_DCR_LATCH = 2,
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};
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@ -117,12 +118,16 @@ enum nd_blk_mmio_selector {
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DCR,
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};
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struct nd_blk_addr {
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union {
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void __iomem *base;
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void __pmem *aperture;
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};
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};
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struct nfit_blk {
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struct nfit_blk_mmio {
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union {
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void __iomem *base;
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void __pmem *aperture;
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};
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struct nd_blk_addr addr;
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u64 size;
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u64 base_offset;
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u32 line_size;
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@ -149,7 +154,8 @@ struct nfit_spa_mapping {
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struct acpi_nfit_system_address *spa;
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struct list_head list;
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struct kref kref;
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void __iomem *iomem;
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enum spa_map_type type;
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struct nd_blk_addr addr;
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};
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static inline struct nfit_spa_mapping *to_spa_map(struct kref *kref)
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@ -531,4 +531,7 @@ config ARCH_HAS_SG_CHAIN
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config ARCH_HAS_PMEM_API
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bool
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config ARCH_HAS_MMIO_FLUSH
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bool
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endmenu
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@ -1,8 +1,10 @@
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ldflags-y += --wrap=ioremap_wc
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ldflags-y += --wrap=memremap
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ldflags-y += --wrap=devm_ioremap_nocache
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ldflags-y += --wrap=devm_memremap
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ldflags-y += --wrap=ioremap_nocache
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ldflags-y += --wrap=iounmap
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ldflags-y += --wrap=memunmap
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ldflags-y += --wrap=__devm_request_region
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ldflags-y += --wrap=__request_region
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ldflags-y += --wrap=__release_region
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@ -89,12 +89,25 @@ void *__wrap_devm_memremap(struct device *dev, resource_size_t offset,
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nfit_res = get_nfit_res(offset);
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rcu_read_unlock();
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if (nfit_res)
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return (void __iomem *) nfit_res->buf + offset
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- nfit_res->res->start;
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return nfit_res->buf + offset - nfit_res->res->start;
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return devm_memremap(dev, offset, size, flags);
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}
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EXPORT_SYMBOL(__wrap_devm_memremap);
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void *__wrap_memremap(resource_size_t offset, size_t size,
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unsigned long flags)
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{
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struct nfit_test_resource *nfit_res;
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rcu_read_lock();
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nfit_res = get_nfit_res(offset);
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rcu_read_unlock();
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if (nfit_res)
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return nfit_res->buf + offset - nfit_res->res->start;
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return memremap(offset, size, flags);
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}
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EXPORT_SYMBOL(__wrap_memremap);
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void __iomem *__wrap_ioremap_nocache(resource_size_t offset, unsigned long size)
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{
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return __nfit_test_ioremap(offset, size, ioremap_nocache);
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@ -120,6 +133,19 @@ void __wrap_iounmap(volatile void __iomem *addr)
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}
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EXPORT_SYMBOL(__wrap_iounmap);
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void __wrap_memunmap(void *addr)
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{
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struct nfit_test_resource *nfit_res;
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rcu_read_lock();
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nfit_res = get_nfit_res((unsigned long) addr);
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rcu_read_unlock();
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if (nfit_res)
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return;
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return memunmap(addr);
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}
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EXPORT_SYMBOL(__wrap_memunmap);
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static struct resource *nfit_test_request_region(struct device *dev,
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struct resource *parent, resource_size_t start,
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resource_size_t n, const char *name, int flags)
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@ -1029,9 +1029,13 @@ static int nfit_test_blk_do_io(struct nd_blk_region *ndbr, resource_size_t dpa,
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lane = nd_region_acquire_lane(nd_region);
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if (rw)
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memcpy(mmio->base + dpa, iobuf, len);
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else
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memcpy(iobuf, mmio->base + dpa, len);
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memcpy(mmio->addr.base + dpa, iobuf, len);
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else {
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memcpy(iobuf, mmio->addr.base + dpa, len);
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/* give us some some coverage of the mmio_flush_range() API */
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mmio_flush_range(mmio->addr.base + dpa, len);
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}
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nd_region_release_lane(nd_region, lane);
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return 0;
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