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net: sh_eth: add support for multicast filtering
Some controllers have TSU. It can filter multicast by hardware. This patch supports it. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yoshihiro Shimoda
David S. Miller
parent
6ba88021c3
commit
6743fe6df4
@ -1604,18 +1604,289 @@ static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
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}
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#if defined(SH_ETH_HAS_TSU)
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/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
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static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
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int entry)
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{
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return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
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}
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static u32 sh_eth_tsu_get_post_mask(int entry)
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{
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return 0x0f << (28 - ((entry % 8) * 4));
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}
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static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
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{
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return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
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}
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static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
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int entry)
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{
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struct sh_eth_private *mdp = netdev_priv(ndev);
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u32 tmp;
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void *reg_offset;
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reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
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tmp = ioread32(reg_offset);
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iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
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}
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static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
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int entry)
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{
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struct sh_eth_private *mdp = netdev_priv(ndev);
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u32 post_mask, ref_mask, tmp;
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void *reg_offset;
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reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
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post_mask = sh_eth_tsu_get_post_mask(entry);
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ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
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tmp = ioread32(reg_offset);
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iowrite32(tmp & ~post_mask, reg_offset);
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/* If other port enables, the function returns "true" */
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return tmp & ref_mask;
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}
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static int sh_eth_tsu_busy(struct net_device *ndev)
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{
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int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
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struct sh_eth_private *mdp = netdev_priv(ndev);
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while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
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udelay(10);
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timeout--;
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if (timeout <= 0) {
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dev_err(&ndev->dev, "%s: timeout\n", __func__);
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return -ETIMEDOUT;
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}
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}
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return 0;
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}
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static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
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const u8 *addr)
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{
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u32 val;
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val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
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iowrite32(val, reg);
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if (sh_eth_tsu_busy(ndev) < 0)
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return -EBUSY;
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val = addr[4] << 8 | addr[5];
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iowrite32(val, reg + 4);
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if (sh_eth_tsu_busy(ndev) < 0)
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return -EBUSY;
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return 0;
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}
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static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
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{
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u32 val;
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val = ioread32(reg);
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addr[0] = (val >> 24) & 0xff;
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addr[1] = (val >> 16) & 0xff;
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addr[2] = (val >> 8) & 0xff;
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addr[3] = val & 0xff;
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val = ioread32(reg + 4);
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addr[4] = (val >> 8) & 0xff;
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addr[5] = val & 0xff;
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}
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static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
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{
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struct sh_eth_private *mdp = netdev_priv(ndev);
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void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
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int i;
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u8 c_addr[ETH_ALEN];
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for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
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sh_eth_tsu_read_entry(reg_offset, c_addr);
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if (memcmp(addr, c_addr, ETH_ALEN) == 0)
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return i;
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}
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return -ENOENT;
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}
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static int sh_eth_tsu_find_empty(struct net_device *ndev)
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{
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u8 blank[ETH_ALEN];
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int entry;
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memset(blank, 0, sizeof(blank));
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entry = sh_eth_tsu_find_entry(ndev, blank);
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return (entry < 0) ? -ENOMEM : entry;
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}
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static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
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int entry)
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{
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struct sh_eth_private *mdp = netdev_priv(ndev);
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void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
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int ret;
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u8 blank[ETH_ALEN];
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sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
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~(1 << (31 - entry)), TSU_TEN);
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memset(blank, 0, sizeof(blank));
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ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
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{
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struct sh_eth_private *mdp = netdev_priv(ndev);
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void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
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int i, ret;
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if (!mdp->cd->tsu)
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return 0;
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i = sh_eth_tsu_find_entry(ndev, addr);
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if (i < 0) {
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/* No entry found, create one */
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i = sh_eth_tsu_find_empty(ndev);
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if (i < 0)
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return -ENOMEM;
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ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
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if (ret < 0)
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return ret;
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/* Enable the entry */
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sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
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(1 << (31 - i)), TSU_TEN);
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}
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/* Entry found or created, enable POST */
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sh_eth_tsu_enable_cam_entry_post(ndev, i);
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return 0;
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}
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static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
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{
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struct sh_eth_private *mdp = netdev_priv(ndev);
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int i, ret;
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if (!mdp->cd->tsu)
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return 0;
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i = sh_eth_tsu_find_entry(ndev, addr);
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if (i) {
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/* Entry found */
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if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
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goto done;
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/* Disable the entry if both ports was disabled */
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ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
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if (ret < 0)
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return ret;
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}
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done:
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return 0;
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}
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static int sh_eth_tsu_purge_all(struct net_device *ndev)
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{
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struct sh_eth_private *mdp = netdev_priv(ndev);
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int i, ret;
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if (unlikely(!mdp->cd->tsu))
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return 0;
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for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
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if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
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continue;
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/* Disable the entry if both ports was disabled */
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ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
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{
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struct sh_eth_private *mdp = netdev_priv(ndev);
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u8 addr[ETH_ALEN];
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void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
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int i;
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if (unlikely(!mdp->cd->tsu))
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return;
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for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
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sh_eth_tsu_read_entry(reg_offset, addr);
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if (is_multicast_ether_addr(addr))
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sh_eth_tsu_del_entry(ndev, addr);
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}
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}
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/* Multicast reception directions set */
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static void sh_eth_set_multicast_list(struct net_device *ndev)
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{
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struct sh_eth_private *mdp = netdev_priv(ndev);
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u32 ecmr_bits;
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int mcast_all = 0;
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unsigned long flags;
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spin_lock_irqsave(&mdp->lock, flags);
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/*
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* Initial condition is MCT = 1, PRM = 0.
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* Depending on ndev->flags, set PRM or clear MCT
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*/
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ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
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if (!(ndev->flags & IFF_MULTICAST)) {
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sh_eth_tsu_purge_mcast(ndev);
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mcast_all = 1;
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}
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if (ndev->flags & IFF_ALLMULTI) {
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sh_eth_tsu_purge_mcast(ndev);
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ecmr_bits &= ~ECMR_MCT;
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mcast_all = 1;
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}
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if (ndev->flags & IFF_PROMISC) {
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/* Set promiscuous. */
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sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_MCT) |
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ECMR_PRM, ECMR);
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sh_eth_tsu_purge_all(ndev);
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ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
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} else if (mdp->cd->tsu) {
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struct netdev_hw_addr *ha;
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netdev_for_each_mc_addr(ha, ndev) {
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if (mcast_all && is_multicast_ether_addr(ha->addr))
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continue;
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if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
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if (!mcast_all) {
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sh_eth_tsu_purge_mcast(ndev);
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ecmr_bits &= ~ECMR_MCT;
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mcast_all = 1;
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}
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}
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}
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} else {
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/* Normal, unicast/broadcast-only mode. */
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sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) |
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ECMR_MCT, ECMR);
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ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
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}
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/* update the ethernet mode */
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sh_eth_write(ndev, ecmr_bits, ECMR);
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spin_unlock_irqrestore(&mdp->lock, flags);
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}
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#endif /* SH_ETH_HAS_TSU */
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@ -1869,6 +2140,7 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
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}
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mdp->tsu_addr = ioremap(rtsu->start,
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resource_size(rtsu));
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mdp->port = devno % 2;
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}
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/* initialize first or needed device */
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@ -29,6 +29,8 @@
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#define RX_RING_SIZE 64 /* Rx ring size */
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#define ETHERSMALL 60
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#define PKT_BUF_SZ 1538
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#define SH_ETH_TSU_TIMEOUT_MS 500
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#define SH_ETH_TSU_CAM_ENTRIES 32
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enum {
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/* E-DMAC registers */
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@ -778,6 +780,7 @@ struct sh_eth_private {
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char post_rx; /* POST receive */
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char post_fw; /* POST forward */
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struct net_device_stats tsu_stats; /* TSU forward status */
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int port; /* for TSU */
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unsigned no_ether_link:1;
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unsigned ether_link_active_low:1;
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@ -811,6 +814,12 @@ static inline unsigned long sh_eth_read(struct net_device *ndev,
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return ioread32(mdp->addr + mdp->reg_offset[enum_index]);
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}
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static inline void *sh_eth_tsu_get_offset(struct sh_eth_private *mdp,
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int enum_index)
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{
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return mdp->tsu_addr + mdp->reg_offset[enum_index];
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}
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static inline void sh_eth_tsu_write(struct sh_eth_private *mdp,
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unsigned long data, int enum_index)
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{
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