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i.MX SoC changes for 5.8:

Browse Source 
- Add soc device support for Vybrid/VF platform.
 - Move the i.MX soc device registration code from mach-imx to
   drivers/soc/imx for possible future consolidation with i.MX8 code.
 - A small fixup to make pcm970_sja1000_platform_data static.
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Merge tag 'imx-soc-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/soc

i.MX SoC changes for 5.8:

- Add soc device support for Vybrid/VF platform.
- Move the i.MX soc device registration code from mach-imx to
  drivers/soc/imx for possible future consolidation with i.MX8 code.
- A small fixup to make pcm970_sja1000_platform_data static.

* tag 'imx-soc-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  soc: imx: move cpu code to drivers/soc/imx
  ARM: imx: move cpu definitions into a header
  ARM: imx: use device_initcall for imx_soc_device_init
  ARM: imx: pcm037: make pcm970_sja1000_platform_data static
  ARM: vf610: report soc info via soc device

Link: https://lore.kernel.org/r/20200523032516.11016-2-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2020-05-26 00:03:12 +02:00
commit 66ee9359b0
14 changed files with 285 additions and 217 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/mach-imx/common.h
View File

@ -49,7 +49,6 @@ void imx_aips_allow_unprivileged_access(const char *compat);
int mxc_device_init(void);
void imx_set_soc_revision(unsigned int rev);
void imx_init_revision_from_anatop(void);
struct device *imx_soc_device_init(void);
void imx6_enable_rbc(bool enable);
void imx_gpc_check_dt(void);
void imx_gpc_set_arm_power_in_lpm(bool power_off);

159
arch/arm/mach-imx/cpu.c
View File

@ -1,25 +1,13 @@
// SPDX-License-Identifier: GPL-2.0
#include <linux/err.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
#include "hardware.h"
#include "common.h"
#define OCOTP_UID_H 0x420
#define OCOTP_UID_L 0x410
#define OCOTP_ULP_UID_1 0x4b0
#define OCOTP_ULP_UID_2 0x4c0
#define OCOTP_ULP_UID_3 0x4d0
#define OCOTP_ULP_UID_4 0x4e0
unsigned int __mxc_cpu_type;
static unsigned int imx_soc_revision;
@ -82,150 +70,3 @@ void __init imx_aips_allow_unprivileged_access(
imx_set_aips(aips_base_addr);
}
}
struct device * __init imx_soc_device_init(void)
{
struct soc_device_attribute *soc_dev_attr;
const char *ocotp_compat = NULL;
struct soc_device *soc_dev;
struct device_node *root;
struct regmap *ocotp = NULL;
const char *soc_id;
u64 soc_uid = 0;
u32 val;
int ret;
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr)
return NULL;
soc_dev_attr->family = "Freescale i.MX";
root = of_find_node_by_path("/");
ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
of_node_put(root);
if (ret)
goto free_soc;
switch (__mxc_cpu_type) {
case MXC_CPU_MX1:
soc_id = "i.MX1";
break;
case MXC_CPU_MX21:
soc_id = "i.MX21";
break;
case MXC_CPU_MX25:
soc_id = "i.MX25";
break;
case MXC_CPU_MX27:
soc_id = "i.MX27";
break;
case MXC_CPU_MX31:
soc_id = "i.MX31";
break;
case MXC_CPU_MX35:
soc_id = "i.MX35";
break;
case MXC_CPU_MX51:
soc_id = "i.MX51";
break;
case MXC_CPU_MX53:
soc_id = "i.MX53";
break;
case MXC_CPU_IMX6SL:
ocotp_compat = "fsl,imx6sl-ocotp";
soc_id = "i.MX6SL";
break;
case MXC_CPU_IMX6DL:
ocotp_compat = "fsl,imx6q-ocotp";
soc_id = "i.MX6DL";
break;
case MXC_CPU_IMX6SX:
ocotp_compat = "fsl,imx6sx-ocotp";
soc_id = "i.MX6SX";
break;
case MXC_CPU_IMX6Q:
ocotp_compat = "fsl,imx6q-ocotp";
soc_id = "i.MX6Q";
break;
case MXC_CPU_IMX6UL:
ocotp_compat = "fsl,imx6ul-ocotp";
soc_id = "i.MX6UL";
break;
case MXC_CPU_IMX6ULL:
ocotp_compat = "fsl,imx6ull-ocotp";
soc_id = "i.MX6ULL";
break;
case MXC_CPU_IMX6ULZ:
ocotp_compat = "fsl,imx6ull-ocotp";
soc_id = "i.MX6ULZ";
break;
case MXC_CPU_IMX6SLL:
ocotp_compat = "fsl,imx6sll-ocotp";
soc_id = "i.MX6SLL";
break;
case MXC_CPU_IMX7D:
ocotp_compat = "fsl,imx7d-ocotp";
soc_id = "i.MX7D";
break;
case MXC_CPU_IMX7ULP:
ocotp_compat = "fsl,imx7ulp-ocotp";
soc_id = "i.MX7ULP";
break;
default:
soc_id = "Unknown";
}
soc_dev_attr->soc_id = soc_id;
if (ocotp_compat) {
ocotp = syscon_regmap_lookup_by_compatible(ocotp_compat);
if (IS_ERR(ocotp))
pr_err("%s: failed to find %s regmap!\n", __func__, ocotp_compat);
}
if (!IS_ERR_OR_NULL(ocotp)) {
if (__mxc_cpu_type == MXC_CPU_IMX7ULP) {
regmap_read(ocotp, OCOTP_ULP_UID_4, &val);
soc_uid = val & 0xffff;
regmap_read(ocotp, OCOTP_ULP_UID_3, &val);
soc_uid <<= 16;
soc_uid |= val & 0xffff;
regmap_read(ocotp, OCOTP_ULP_UID_2, &val);
soc_uid <<= 16;
soc_uid |= val & 0xffff;
regmap_read(ocotp, OCOTP_ULP_UID_1, &val);
soc_uid <<= 16;
soc_uid |= val & 0xffff;
} else {
regmap_read(ocotp, OCOTP_UID_H, &val);
soc_uid = val;
regmap_read(ocotp, OCOTP_UID_L, &val);
soc_uid <<= 32;
soc_uid |= val;
}
}
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
(imx_soc_revision >> 4) & 0xf,
imx_soc_revision & 0xf);
if (!soc_dev_attr->revision)
goto free_soc;
soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid);
if (!soc_dev_attr->serial_number)
goto free_rev;
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev))
goto free_serial_number;
return soc_device_to_device(soc_dev);
free_serial_number:
kfree(soc_dev_attr->serial_number);
free_rev:
kfree(soc_dev_attr->revision);
free_soc:
kfree(soc_dev_attr);
return NULL;
}

8
arch/arm/mach-imx/mach-imx6q.c
View File

@ -245,21 +245,15 @@ static void __init imx6q_axi_init(void)
static void __init imx6q_init_machine(void)
{
struct device *parent;
if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0);
else
imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
imx_get_soc_revision());
parent = imx_soc_device_init();
if (parent == NULL)
pr_warn("failed to initialize soc device\n");
imx6q_enet_phy_init();
of_platform_default_populate(NULL, NULL, parent);
of_platform_default_populate(NULL, NULL, NULL);
imx_anatop_init();
cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init();

8
arch/arm/mach-imx/mach-imx6sl.c
View File

@ -45,13 +45,7 @@ static void __init imx6sl_init_late(void)
static void __init imx6sl_init_machine(void)
{
struct device *parent;
parent = imx_soc_device_init();
if (parent == NULL)
pr_warn("failed to initialize soc device\n");
of_platform_default_populate(NULL, NULL, parent);
of_platform_default_populate(NULL, NULL, NULL);
if (cpu_is_imx6sl())
imx6sl_fec_init();

8
arch/arm/mach-imx/mach-imx6sx.c
View File

@ -63,13 +63,7 @@ static inline void imx6sx_enet_init(void)
static void __init imx6sx_init_machine(void)
{
struct device *parent;
parent = imx_soc_device_init();
if (parent == NULL)
pr_warn("failed to initialize soc device\n");
of_platform_default_populate(NULL, NULL, parent);
of_platform_default_populate(NULL, NULL, NULL);
imx6sx_enet_init();
imx_anatop_init();

8
arch/arm/mach-imx/mach-imx6ul.c
View File

@ -55,13 +55,7 @@ static inline void imx6ul_enet_init(void)
static void __init imx6ul_init_machine(void)
{
struct device *parent;
parent = imx_soc_device_init();
if (parent == NULL)
pr_warn("failed to initialize soc device\n");
of_platform_default_populate(NULL, NULL, parent);
of_platform_default_populate(NULL, NULL, NULL);
imx6ul_enet_init();
imx_anatop_init();
imx6ul_pm_init();

6
arch/arm/mach-imx/mach-imx7d.c
View File

@ -78,12 +78,6 @@ static inline void imx7d_enet_init(void)
static void __init imx7d_init_machine(void)
{
struct device *parent;
parent = imx_soc_device_init();
if (parent == NULL)
pr_warn("failed to initialize soc device\n");
imx_anatop_init();
imx7d_enet_init();
}

2
arch/arm/mach-imx/mach-imx7ulp.c
View File

@ -57,7 +57,7 @@ static void __init imx7ulp_init_machine(void)
mxc_set_cpu_type(MXC_CPU_IMX7ULP);
imx7ulp_set_revision();
of_platform_default_populate(NULL, NULL, imx_soc_device_init());
of_platform_default_populate(NULL, NULL, NULL);
}
static const char *const imx7ulp_dt_compat[] __initconst = {

2
arch/arm/mach-imx/mach-pcm037.c
View File

@ -404,7 +404,7 @@ static struct resource pcm970_sja1000_resources[] = {
},
};
struct sja1000_platform_data pcm970_sja1000_platform_data = {
static struct sja1000_platform_data pcm970_sja1000_platform_data = {
.osc_freq = 16000000,
.ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
.cdr = CDR_CBP,

47
arch/arm/mach-imx/mach-vf610.c
View File

@ -3,11 +3,57 @@
* Copyright 2012-2013 Freescale Semiconductor, Inc.
*/
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/io.h>
#include <linux/irqchip.h>
#include <asm/mach/arch.h>
#include <asm/hardware/cache-l2x0.h>
#include "common.h"
#include "hardware.h"
#define MSCM_CPxCOUNT 0x00c
#define MSCM_CPxCFG1 0x014
static void __init vf610_detect_cpu(void)
{
struct device_node *np;
u32 cpxcount, cpxcfg1;
unsigned int cpu_type;
void __iomem *mscm;
np = of_find_compatible_node(NULL, NULL, "fsl,vf610-mscm-cpucfg");
if (WARN_ON(!np))
return;
mscm = of_iomap(np, 0);
of_node_put(np);
if (WARN_ON(!mscm))
return;
cpxcount = readl_relaxed(mscm + MSCM_CPxCOUNT);
cpxcfg1 = readl_relaxed(mscm + MSCM_CPxCFG1);
iounmap(mscm);
cpu_type = cpxcount ? MXC_CPU_VF600 : MXC_CPU_VF500;
if (cpxcfg1)
cpu_type |= MXC_CPU_VFx10;
mxc_set_cpu_type(cpu_type);
}
static void __init vf610_init_machine(void)
{
vf610_detect_cpu();
of_platform_default_populate(NULL, NULL, NULL);
}
static const char * const vf610_dt_compat[] __initconst = {
"fsl,vf500",
"fsl,vf510",
@ -20,5 +66,6 @@ static const char * const vf610_dt_compat[] __initconst = {
DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF5xx/VF6xx (Device Tree)")
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.init_machine = vf610_init_machine,
.dt_compat = vf610_dt_compat,
MACHINE_END

22
arch/arm/mach-imx/mxc.h
View File

@ -8,35 +8,15 @@
#define __ASM_ARCH_MXC_H__
#include <linux/types.h>
#include <soc/imx/cpu.h>
#ifndef __ASM_ARCH_MXC_HARDWARE_H__
#error "Do not include directly."
#endif
#define MXC_CPU_MX1 1
#define MXC_CPU_MX21 21
#define MXC_CPU_MX25 25
#define MXC_CPU_MX27 27
#define MXC_CPU_MX31 31
#define MXC_CPU_MX35 35
#define MXC_CPU_MX51 51
#define MXC_CPU_MX53 53
#define MXC_CPU_IMX6SL 0x60
#define MXC_CPU_IMX6DL 0x61
#define MXC_CPU_IMX6SX 0x62
#define MXC_CPU_IMX6Q 0x63
#define MXC_CPU_IMX6UL 0x64
#define MXC_CPU_IMX6ULL 0x65
/* virtual cpu id for i.mx6ulz */
#define MXC_CPU_IMX6ULZ 0x6b
#define MXC_CPU_IMX6SLL 0x67
#define MXC_CPU_IMX7D 0x72
#define MXC_CPU_IMX7ULP 0xff
#define IMX_DDR_TYPE_LPDDR2 1
#ifndef __ASSEMBLY__
extern unsigned int __mxc_cpu_type;
#ifdef CONFIG_SOC_IMX6SL
static inline bool cpu_is_imx6sl(void)

3
drivers/soc/imx/Makefile
View File

@ -1,4 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
ifeq ($(CONFIG_ARM),y)
obj-$(CONFIG_ARCH_MXC) += soc-imx.o
endif
obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o

192
drivers/soc/imx/soc-imx.c Normal file
View File

@ -0,0 +1,192 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020 NXP
*/
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
#include <soc/imx/cpu.h>
#include <soc/imx/revision.h>
#define OCOTP_UID_H 0x420
#define OCOTP_UID_L 0x410
#define OCOTP_ULP_UID_1 0x4b0
#define OCOTP_ULP_UID_2 0x4c0
#define OCOTP_ULP_UID_3 0x4d0
#define OCOTP_ULP_UID_4 0x4e0
static int __init imx_soc_device_init(void)
{
struct soc_device_attribute *soc_dev_attr;
const char *ocotp_compat = NULL;
struct soc_device *soc_dev;
struct device_node *root;
struct regmap *ocotp = NULL;
const char *soc_id;
u64 soc_uid = 0;
u32 val;
int ret;
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr)
return -ENOMEM;
soc_dev_attr->family = "Freescale i.MX";
root = of_find_node_by_path("/");
ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
of_node_put(root);
if (ret)
goto free_soc;
switch (__mxc_cpu_type) {
case MXC_CPU_MX1:
soc_id = "i.MX1";
break;
case MXC_CPU_MX21:
soc_id = "i.MX21";
break;
case MXC_CPU_MX25:
soc_id = "i.MX25";
break;
case MXC_CPU_MX27:
soc_id = "i.MX27";
break;
case MXC_CPU_MX31:
soc_id = "i.MX31";
break;
case MXC_CPU_MX35:
soc_id = "i.MX35";
break;
case MXC_CPU_MX51:
soc_id = "i.MX51";
break;
case MXC_CPU_MX53:
soc_id = "i.MX53";
break;
case MXC_CPU_IMX6SL:
ocotp_compat = "fsl,imx6sl-ocotp";
soc_id = "i.MX6SL";
break;
case MXC_CPU_IMX6DL:
ocotp_compat = "fsl,imx6q-ocotp";
soc_id = "i.MX6DL";
break;
case MXC_CPU_IMX6SX:
ocotp_compat = "fsl,imx6sx-ocotp";
soc_id = "i.MX6SX";
break;
case MXC_CPU_IMX6Q:
ocotp_compat = "fsl,imx6q-ocotp";
soc_id = "i.MX6Q";
break;
case MXC_CPU_IMX6UL:
ocotp_compat = "fsl,imx6ul-ocotp";
soc_id = "i.MX6UL";
break;
case MXC_CPU_IMX6ULL:
ocotp_compat = "fsl,imx6ull-ocotp";
soc_id = "i.MX6ULL";
break;
case MXC_CPU_IMX6ULZ:
ocotp_compat = "fsl,imx6ull-ocotp";
soc_id = "i.MX6ULZ";
break;
case MXC_CPU_IMX6SLL:
ocotp_compat = "fsl,imx6sll-ocotp";
soc_id = "i.MX6SLL";
break;
case MXC_CPU_IMX7D:
ocotp_compat = "fsl,imx7d-ocotp";
soc_id = "i.MX7D";
break;
case MXC_CPU_IMX7ULP:
ocotp_compat = "fsl,imx7ulp-ocotp";
soc_id = "i.MX7ULP";
break;
case MXC_CPU_VF500:
ocotp_compat = "fsl,vf610-ocotp";
soc_id = "VF500";
break;
case MXC_CPU_VF510:
ocotp_compat = "fsl,vf610-ocotp";
soc_id = "VF510";
break;
case MXC_CPU_VF600:
ocotp_compat = "fsl,vf610-ocotp";
soc_id = "VF600";
break;
case MXC_CPU_VF610:
ocotp_compat = "fsl,vf610-ocotp";
soc_id = "VF610";
break;
default:
soc_id = "Unknown";
}
soc_dev_attr->soc_id = soc_id;
if (ocotp_compat) {
ocotp = syscon_regmap_lookup_by_compatible(ocotp_compat);
if (IS_ERR(ocotp))
pr_err("%s: failed to find %s regmap!\n", __func__, ocotp_compat);
}
if (!IS_ERR_OR_NULL(ocotp)) {
if (__mxc_cpu_type == MXC_CPU_IMX7ULP) {
regmap_read(ocotp, OCOTP_ULP_UID_4, &val);
soc_uid = val & 0xffff;
regmap_read(ocotp, OCOTP_ULP_UID_3, &val);
soc_uid <<= 16;
soc_uid |= val & 0xffff;
regmap_read(ocotp, OCOTP_ULP_UID_2, &val);
soc_uid <<= 16;
soc_uid |= val & 0xffff;
regmap_read(ocotp, OCOTP_ULP_UID_1, &val);
soc_uid <<= 16;
soc_uid |= val & 0xffff;
} else {
regmap_read(ocotp, OCOTP_UID_H, &val);
soc_uid = val;
regmap_read(ocotp, OCOTP_UID_L, &val);
soc_uid <<= 32;
soc_uid |= val;
}
}
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
(imx_get_soc_revision() >> 4) & 0xf,
imx_get_soc_revision() & 0xf);
if (!soc_dev_attr->revision) {
ret = -ENOMEM;
goto free_soc;
}
soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid);
if (!soc_dev_attr->serial_number) {
ret = -ENOMEM;
goto free_rev;
}
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev)) {
ret = PTR_ERR(soc_dev);
goto free_serial_number;
}
return 0;
free_serial_number:
kfree(soc_dev_attr->serial_number);
free_rev:
kfree(soc_dev_attr->revision);
free_soc:
kfree(soc_dev_attr);
return ret;
}
device_initcall(imx_soc_device_init);

36
include/soc/imx/cpu.h Normal file
View File

@ -0,0 +1,36 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __IMX_CPU_H__
#define __IMX_CPU_H__
#define MXC_CPU_MX1 1
#define MXC_CPU_MX21 21
#define MXC_CPU_MX25 25
#define MXC_CPU_MX27 27
#define MXC_CPU_MX31 31
#define MXC_CPU_MX35 35
#define MXC_CPU_MX51 51
#define MXC_CPU_MX53 53
#define MXC_CPU_IMX6SL 0x60
#define MXC_CPU_IMX6DL 0x61
#define MXC_CPU_IMX6SX 0x62
#define MXC_CPU_IMX6Q 0x63
#define MXC_CPU_IMX6UL 0x64
#define MXC_CPU_IMX6ULL 0x65
/* virtual cpu id for i.mx6ulz */
#define MXC_CPU_IMX6ULZ 0x6b
#define MXC_CPU_IMX6SLL 0x67
#define MXC_CPU_IMX7D 0x72
#define MXC_CPU_IMX7ULP 0xff
#define MXC_CPU_VFx10 0x010
#define MXC_CPU_VF500 0x500
#define MXC_CPU_VF510 (MXC_CPU_VF500 | MXC_CPU_VFx10)
#define MXC_CPU_VF600 0x600
#define MXC_CPU_VF610 (MXC_CPU_VF600 | MXC_CPU_VFx10)
#ifndef __ASSEMBLY__
extern unsigned int __mxc_cpu_type;
#endif
#endif