mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-20 19:23:57 +08:00
ath9k_hw: remove the old tx descriptor API
Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Felix Fietkau
John W. Linville
parent
493cf04fd3
commit
66ac69c8c3
@ -270,35 +270,6 @@ ar9002_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i)
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| SM(i->rtscts_rate, AR_RTSCTSRate);
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}
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static void ar9002_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
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bool is_firstseg, bool is_lastseg,
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const void *ds0, dma_addr_t buf_addr,
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unsigned int qcu)
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{
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struct ar5416_desc *ads = AR5416DESC(ds);
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ads->ds_data = buf_addr;
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if (is_firstseg) {
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ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore);
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} else if (is_lastseg) {
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ads->ds_ctl0 = 0;
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ads->ds_ctl1 = seglen;
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ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
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ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
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} else {
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ads->ds_ctl0 = 0;
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ads->ds_ctl1 = seglen | AR_TxMore;
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ads->ds_ctl2 = 0;
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ads->ds_ctl3 = 0;
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}
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ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
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ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
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ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
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ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
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ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
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}
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static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
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struct ath_tx_status *ts)
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{
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@ -371,145 +342,6 @@ static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
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return 0;
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}
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static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
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u32 pktLen, enum ath9k_pkt_type type,
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u32 txPower, u8 keyIx,
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enum ath9k_key_type keyType, u32 flags)
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{
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struct ar5416_desc *ads = AR5416DESC(ds);
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if (txPower > 63)
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txPower = 63;
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ads->ds_ctl0 = (pktLen & AR_FrameLen)
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| (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
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| SM(txPower, AR_XmitPower)
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| (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
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| (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
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| (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
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ads->ds_ctl1 =
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(keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
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| SM(type, AR_FrameType)
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| (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
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| (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
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| (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
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ads->ds_ctl6 = SM(keyType, AR_EncrType);
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if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
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ads->ds_ctl8 = 0;
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ads->ds_ctl9 = 0;
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ads->ds_ctl10 = 0;
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ads->ds_ctl11 = 0;
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}
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}
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static void ar9002_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val)
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{
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struct ar5416_desc *ads = AR5416DESC(ds);
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if (val)
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ads->ds_ctl0 |= AR_ClrDestMask;
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else
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ads->ds_ctl0 &= ~AR_ClrDestMask;
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}
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static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
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void *lastds,
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u32 durUpdateEn, u32 rtsctsRate,
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u32 rtsctsDuration,
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struct ath9k_11n_rate_series series[],
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u32 nseries, u32 flags)
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{
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struct ar5416_desc *ads = AR5416DESC(ds);
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struct ar5416_desc *last_ads = AR5416DESC(lastds);
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u32 ds_ctl0;
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if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
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ds_ctl0 = ads->ds_ctl0;
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if (flags & ATH9K_TXDESC_RTSENA) {
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ds_ctl0 &= ~AR_CTSEnable;
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ds_ctl0 |= AR_RTSEnable;
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} else {
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ds_ctl0 &= ~AR_RTSEnable;
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ds_ctl0 |= AR_CTSEnable;
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}
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ads->ds_ctl0 = ds_ctl0;
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} else {
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ads->ds_ctl0 =
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(ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
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}
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ads->ds_ctl2 = set11nTries(series, 0)
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| set11nTries(series, 1)
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| set11nTries(series, 2)
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| set11nTries(series, 3)
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| (durUpdateEn ? AR_DurUpdateEna : 0)
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| SM(0, AR_BurstDur);
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ads->ds_ctl3 = set11nRate(series, 0)
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| set11nRate(series, 1)
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| set11nRate(series, 2)
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| set11nRate(series, 3);
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ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
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| set11nPktDurRTSCTS(series, 1);
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ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
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| set11nPktDurRTSCTS(series, 3);
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ads->ds_ctl7 = set11nRateFlags(series, 0)
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| set11nRateFlags(series, 1)
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| set11nRateFlags(series, 2)
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| set11nRateFlags(series, 3)
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| SM(rtsctsRate, AR_RTSCTSRate);
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last_ads->ds_ctl2 = ads->ds_ctl2;
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last_ads->ds_ctl3 = ads->ds_ctl3;
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}
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static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
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u32 aggrLen)
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{
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struct ar5416_desc *ads = AR5416DESC(ds);
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ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
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ads->ds_ctl6 &= ~AR_AggrLen;
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ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
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}
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static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
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u32 numDelims)
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{
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struct ar5416_desc *ads = AR5416DESC(ds);
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unsigned int ctl6;
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ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
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ctl6 = ads->ds_ctl6;
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ctl6 &= ~AR_PadDelim;
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ctl6 |= SM(numDelims, AR_PadDelim);
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ads->ds_ctl6 = ctl6;
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}
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static void ar9002_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
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{
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struct ar5416_desc *ads = AR5416DESC(ds);
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ads->ds_ctl1 |= AR_IsAggr;
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ads->ds_ctl1 &= ~AR_MoreAggr;
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ads->ds_ctl6 &= ~AR_PadDelim;
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}
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static void ar9002_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
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{
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struct ar5416_desc *ads = AR5416DESC(ds);
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ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
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}
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void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
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u32 size, u32 flags)
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{
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@ -534,13 +366,5 @@ void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
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ops->set_desc_link = ar9002_hw_set_desc_link;
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ops->get_isr = ar9002_hw_get_isr;
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ops->set_txdesc = ar9002_set_txdesc;
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ops->fill_txdesc = ar9002_hw_fill_txdesc;
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ops->proc_txdesc = ar9002_hw_proc_txdesc;
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ops->set11n_txdesc = ar9002_hw_set11n_txdesc;
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ops->set11n_ratescenario = ar9002_hw_set11n_ratescenario;
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ops->set11n_aggr_first = ar9002_hw_set11n_aggr_first;
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ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle;
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ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last;
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ops->clr11n_aggr = ar9002_hw_clr11n_aggr;
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ops->set_clrdmask = ar9002_hw_set_clrdmask;
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}
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@ -311,46 +311,6 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
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return true;
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}
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static void ar9003_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
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bool is_firstseg, bool is_lastseg,
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const void *ds0, dma_addr_t buf_addr,
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unsigned int qcu)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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unsigned int descid = 0;
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ads->info = (ATHEROS_VENDOR_ID << AR_DescId_S) |
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(1 << AR_TxRxDesc_S) |
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(1 << AR_CtrlStat_S) |
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(qcu << AR_TxQcuNum_S) | 0x17;
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ads->data0 = buf_addr;
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ads->data1 = 0;
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ads->data2 = 0;
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ads->data3 = 0;
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ads->ctl3 = (seglen << AR_BufLen_S);
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ads->ctl3 &= AR_BufLen;
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/* Fill in pointer checksum and descriptor id */
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ads->ctl10 = (descid << AR_TxDescId_S);
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if (is_firstseg) {
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ads->ctl12 |= (is_lastseg ? 0 : AR_TxMore);
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} else if (is_lastseg) {
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ads->ctl11 = 0;
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ads->ctl12 = 0;
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ads->ctl13 = AR9003TXC_CONST(ds0)->ctl13;
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ads->ctl14 = AR9003TXC_CONST(ds0)->ctl14;
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} else {
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/* XXX Intermediate descriptor in a multi-descriptor frame.*/
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ads->ctl11 = 0;
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ads->ctl12 = AR_TxMore;
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ads->ctl13 = 0;
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ads->ctl14 = 0;
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}
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}
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static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
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struct ath_tx_status *ts)
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{
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@ -435,161 +395,6 @@ static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
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return 0;
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}
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static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
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u32 pktlen, enum ath9k_pkt_type type, u32 txpower,
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u8 keyIx, enum ath9k_key_type keyType, u32 flags)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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if (txpower > ah->txpower_limit)
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txpower = ah->txpower_limit;
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if (txpower > 63)
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txpower = 63;
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ads->ctl11 = (pktlen & AR_FrameLen)
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| (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
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| SM(txpower, AR_XmitPower)
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| (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
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| (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
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| (flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0);
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ads->ctl12 =
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(keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
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| SM(type, AR_FrameType)
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| (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
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| (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
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| (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
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ads->ctl17 = SM(keyType, AR_EncrType) |
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(flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0);
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ads->ctl18 = 0;
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ads->ctl19 = AR_Not_Sounding;
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ads->ctl20 = 0;
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ads->ctl21 = 0;
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ads->ctl22 = 0;
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}
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static void ar9003_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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if (val)
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ads->ctl11 |= AR_ClrDestMask;
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else
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ads->ctl11 &= ~AR_ClrDestMask;
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}
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static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
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void *lastds,
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u32 durUpdateEn, u32 rtsctsRate,
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u32 rtsctsDuration,
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struct ath9k_11n_rate_series series[],
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u32 nseries, u32 flags)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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struct ar9003_txc *last_ads = (struct ar9003_txc *) lastds;
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u_int32_t ctl11;
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if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
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ctl11 = ads->ctl11;
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if (flags & ATH9K_TXDESC_RTSENA) {
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ctl11 &= ~AR_CTSEnable;
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ctl11 |= AR_RTSEnable;
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} else {
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ctl11 &= ~AR_RTSEnable;
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ctl11 |= AR_CTSEnable;
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}
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ads->ctl11 = ctl11;
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} else {
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ads->ctl11 = (ads->ctl11 & ~(AR_RTSEnable | AR_CTSEnable));
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}
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ads->ctl13 = set11nTries(series, 0)
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| set11nTries(series, 1)
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| set11nTries(series, 2)
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| set11nTries(series, 3)
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| (durUpdateEn ? AR_DurUpdateEna : 0)
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| SM(0, AR_BurstDur);
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ads->ctl14 = set11nRate(series, 0)
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| set11nRate(series, 1)
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| set11nRate(series, 2)
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| set11nRate(series, 3);
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ads->ctl15 = set11nPktDurRTSCTS(series, 0)
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| set11nPktDurRTSCTS(series, 1);
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ads->ctl16 = set11nPktDurRTSCTS(series, 2)
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| set11nPktDurRTSCTS(series, 3);
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ads->ctl18 = set11nRateFlags(series, 0)
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| set11nRateFlags(series, 1)
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| set11nRateFlags(series, 2)
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| set11nRateFlags(series, 3)
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| SM(rtsctsRate, AR_RTSCTSRate);
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ads->ctl19 = AR_Not_Sounding;
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last_ads->ctl13 = ads->ctl13;
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last_ads->ctl14 = ads->ctl14;
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}
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static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
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u32 aggrLen)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
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ads->ctl17 &= ~AR_AggrLen;
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ads->ctl17 |= SM(aggrLen, AR_AggrLen);
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}
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static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
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u32 numDelims)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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unsigned int ctl17;
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ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
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/*
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* We use a stack variable to manipulate ctl6 to reduce uncached
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* read modify, modfiy, write.
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*/
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ctl17 = ads->ctl17;
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ctl17 &= ~AR_PadDelim;
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ctl17 |= SM(numDelims, AR_PadDelim);
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ads->ctl17 = ctl17;
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}
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static void ar9003_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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ads->ctl12 |= AR_IsAggr;
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ads->ctl12 &= ~AR_MoreAggr;
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ads->ctl17 &= ~AR_PadDelim;
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}
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static void ar9003_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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ads->ctl12 &= (~AR_IsAggr & ~AR_MoreAggr);
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}
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void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains)
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{
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struct ar9003_txc *ads = ds;
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ads->ctl12 |= SM(chains, AR_PAPRDChainMask);
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}
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EXPORT_SYMBOL(ar9003_hw_set_paprd_txdesc);
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void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
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{
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struct ath_hw_ops *ops = ath9k_hw_ops(hw);
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@ -598,15 +403,7 @@ void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
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ops->set_desc_link = ar9003_hw_set_desc_link;
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ops->get_isr = ar9003_hw_get_isr;
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ops->set_txdesc = ar9003_set_txdesc;
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ops->fill_txdesc = ar9003_hw_fill_txdesc;
|
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ops->proc_txdesc = ar9003_hw_proc_txdesc;
|
||||
ops->set11n_txdesc = ar9003_hw_set11n_txdesc;
|
||||
ops->set11n_ratescenario = ar9003_hw_set11n_ratescenario;
|
||||
ops->set11n_aggr_first = ar9003_hw_set11n_aggr_first;
|
||||
ops->set11n_aggr_middle = ar9003_hw_set11n_aggr_middle;
|
||||
ops->set11n_aggr_last = ar9003_hw_set11n_aggr_last;
|
||||
ops->clr11n_aggr = ar9003_hw_clr11n_aggr;
|
||||
ops->set_clrdmask = ar9003_hw_set_clrdmask;
|
||||
}
|
||||
|
||||
void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
|
||||
|
||||
@ -60,70 +60,12 @@ static inline void ath9k_hw_set_txdesc(struct ath_hw *ah, void *ds,
|
||||
return ath9k_hw_ops(ah)->set_txdesc(ah, ds, i);
|
||||
}
|
||||
|
||||
static inline void ath9k_hw_filltxdesc(struct ath_hw *ah, void *ds, u32 seglen,
|
||||
bool is_firstseg, bool is_lastseg,
|
||||
const void *ds0, dma_addr_t buf_addr,
|
||||
unsigned int qcu)
|
||||
{
|
||||
ath9k_hw_ops(ah)->fill_txdesc(ah, ds, seglen, is_firstseg, is_lastseg,
|
||||
ds0, buf_addr, qcu);
|
||||
}
|
||||
|
||||
static inline int ath9k_hw_txprocdesc(struct ath_hw *ah, void *ds,
|
||||
struct ath_tx_status *ts)
|
||||
{
|
||||
return ath9k_hw_ops(ah)->proc_txdesc(ah, ds, ts);
|
||||
}
|
||||
|
||||
static inline void ath9k_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
|
||||
u32 pktLen, enum ath9k_pkt_type type,
|
||||
u32 txPower, u32 keyIx,
|
||||
enum ath9k_key_type keyType,
|
||||
u32 flags)
|
||||
{
|
||||
ath9k_hw_ops(ah)->set11n_txdesc(ah, ds, pktLen, type, txPower, keyIx,
|
||||
keyType, flags);
|
||||
}
|
||||
|
||||
static inline void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
|
||||
void *lastds,
|
||||
u32 durUpdateEn, u32 rtsctsRate,
|
||||
u32 rtsctsDuration,
|
||||
struct ath9k_11n_rate_series series[],
|
||||
u32 nseries, u32 flags)
|
||||
{
|
||||
ath9k_hw_ops(ah)->set11n_ratescenario(ah, ds, lastds, durUpdateEn,
|
||||
rtsctsRate, rtsctsDuration, series,
|
||||
nseries, flags);
|
||||
}
|
||||
|
||||
static inline void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
|
||||
u32 aggrLen)
|
||||
{
|
||||
ath9k_hw_ops(ah)->set11n_aggr_first(ah, ds, aggrLen);
|
||||
}
|
||||
|
||||
static inline void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
|
||||
u32 numDelims)
|
||||
{
|
||||
ath9k_hw_ops(ah)->set11n_aggr_middle(ah, ds, numDelims);
|
||||
}
|
||||
|
||||
static inline void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
|
||||
{
|
||||
ath9k_hw_ops(ah)->set11n_aggr_last(ah, ds);
|
||||
}
|
||||
|
||||
static inline void ath9k_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
|
||||
{
|
||||
ath9k_hw_ops(ah)->clr11n_aggr(ah, ds);
|
||||
}
|
||||
|
||||
static inline void ath9k_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val)
|
||||
{
|
||||
ath9k_hw_ops(ah)->set_clrdmask(ah, ds, val);
|
||||
}
|
||||
|
||||
static inline void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
|
||||
struct ath_hw_antcomb_conf *antconf)
|
||||
{
|
||||
|
||||
@ -618,30 +618,8 @@ struct ath_hw_ops {
|
||||
bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
|
||||
void (*set_txdesc)(struct ath_hw *ah, void *ds,
|
||||
struct ath_tx_info *i);
|
||||
void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
|
||||
bool is_firstseg, bool is_is_lastseg,
|
||||
const void *ds0, dma_addr_t buf_addr,
|
||||
unsigned int qcu);
|
||||
int (*proc_txdesc)(struct ath_hw *ah, void *ds,
|
||||
struct ath_tx_status *ts);
|
||||
void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
|
||||
u32 pktLen, enum ath9k_pkt_type type,
|
||||
u32 txPower, u8 keyIx,
|
||||
enum ath9k_key_type keyType,
|
||||
u32 flags);
|
||||
void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
|
||||
void *lastds,
|
||||
u32 durUpdateEn, u32 rtsctsRate,
|
||||
u32 rtsctsDuration,
|
||||
struct ath9k_11n_rate_series series[],
|
||||
u32 nseries, u32 flags);
|
||||
void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
|
||||
u32 aggrLen);
|
||||
void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
|
||||
u32 numDelims);
|
||||
void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
|
||||
void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
|
||||
void (*set_clrdmask)(struct ath_hw *ah, void *ds, bool val);
|
||||
void (*antdiv_comb_conf_get)(struct ath_hw *ah,
|
||||
struct ath_hw_antcomb_conf *antconf);
|
||||
void (*antdiv_comb_conf_set)(struct ath_hw *ah,
|
||||
|
||||
@ -62,18 +62,6 @@ void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_txstart);
|
||||
|
||||
void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds)
|
||||
{
|
||||
struct ar5416_desc *ads = AR5416DESC(ds);
|
||||
|
||||
ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
|
||||
ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
|
||||
ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
|
||||
ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
|
||||
ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
|
||||
|
||||
u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
|
||||
{
|
||||
u32 npend;
|
||||
|
||||
@ -712,7 +712,6 @@ enum ath9k_int;
|
||||
u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);
|
||||
void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);
|
||||
void ath9k_hw_txstart(struct ath_hw *ah, u32 q);
|
||||
void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds);
|
||||
u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);
|
||||
bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel);
|
||||
bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user