mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-19 02:34:01 +08:00
Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86: always define DECLARE_PCI_UNMAP* macros x86: fixup config space size of CPU functions for AMD family 11h x86, bts: fix wrmsr and spinlock over kmalloc x86, pebs: fix PEBS record size configuration x86, bts: turn macro into static inline function x86, bts: exclude ds.c from build when disabled arch/x86/kernel/pci-calgary_64.c: change simple_strtol to simple_strtoul x86: use limited register constraint for setnz xen: pin correct PGD on suspend x86: revert irq number limitation x86: fixing __cpuinit/__init tangle, xsave_cntxt_init() x86: fix __cpuinit/__init tangle in init_thread_xstate() oprofile: fix an overflow in ppro code
This commit is contained in:
commit
66a45cc4cc
@ -74,7 +74,7 @@ static int kbd_pending(void)
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{
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u8 pending;
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asm volatile("int $0x16; setnz %0"
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: "=rm" (pending)
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: "=qm" (pending)
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: "a" (0x0100));
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return pending;
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}
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@ -23,12 +23,13 @@
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#ifndef _ASM_X86_DS_H
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#define _ASM_X86_DS_H
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#ifdef CONFIG_X86_DS
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#include <linux/types.h>
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#include <linux/init.h>
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#ifdef CONFIG_X86_DS
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struct task_struct;
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/*
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@ -232,7 +233,8 @@ extern void ds_free(struct ds_context *context);
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#else /* CONFIG_X86_DS */
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#define ds_init_intel(config) do {} while (0)
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struct cpuinfo_x86;
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static inline void __cpuinit ds_init_intel(struct cpuinfo_x86 *ignored) {}
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#endif /* CONFIG_X86_DS */
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#endif /* _ASM_X86_DS_H */
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@ -34,8 +34,6 @@ extern void pci_iommu_alloc(void);
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*/
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#define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys)
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#if defined(CONFIG_GART_IOMMU) || defined(CONFIG_CALGARY_IOMMU)
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#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
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dma_addr_t ADDR_NAME;
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#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
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@ -49,18 +47,6 @@ extern void pci_iommu_alloc(void);
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#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
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(((PTR)->LEN_NAME) = (VAL))
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#else
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/* No IOMMU */
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#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
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#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
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#define pci_unmap_addr(PTR, ADDR_NAME) (0)
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#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
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#define pci_unmap_len(PTR, LEN_NAME) (0)
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#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
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#endif
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#endif /* __KERNEL__ */
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#endif /* _ASM_X86_PCI_64_H */
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@ -41,7 +41,7 @@ obj-$(CONFIG_X86_TRAMPOLINE) += trampoline.o
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obj-y += process.o
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obj-y += i387.o xsave.o
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obj-y += ptrace.o
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obj-y += ds.o
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obj-$(CONFIG_X86_DS) += ds.o
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obj-$(CONFIG_X86_32) += tls.o
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obj-$(CONFIG_IA32_EMULATION) += tls.o
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obj-y += step.o
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@ -21,8 +21,6 @@
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*/
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#ifdef CONFIG_X86_DS
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#include <asm/ds.h>
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#include <linux/errno.h>
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@ -211,14 +209,15 @@ static DEFINE_PER_CPU(struct ds_context *, system_context);
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static inline struct ds_context *ds_get_context(struct task_struct *task)
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{
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struct ds_context *context;
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unsigned long irq;
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spin_lock(&ds_lock);
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spin_lock_irqsave(&ds_lock, irq);
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context = (task ? task->thread.ds_ctx : this_system_context);
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if (context)
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context->count++;
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spin_unlock(&ds_lock);
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spin_unlock_irqrestore(&ds_lock, irq);
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return context;
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}
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@ -226,55 +225,46 @@ static inline struct ds_context *ds_get_context(struct task_struct *task)
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/*
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* Same as ds_get_context, but allocates the context and it's DS
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* structure, if necessary; returns NULL; if out of memory.
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*
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* pre: requires ds_lock to be held
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*/
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static inline struct ds_context *ds_alloc_context(struct task_struct *task)
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{
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struct ds_context **p_context =
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(task ? &task->thread.ds_ctx : &this_system_context);
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struct ds_context *context = *p_context;
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unsigned long irq;
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if (!context) {
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spin_unlock(&ds_lock);
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context = kzalloc(sizeof(*context), GFP_KERNEL);
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if (!context) {
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spin_lock(&ds_lock);
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if (!context)
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return NULL;
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}
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context->ds = kzalloc(ds_cfg.sizeof_ds, GFP_KERNEL);
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if (!context->ds) {
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kfree(context);
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spin_lock(&ds_lock);
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return NULL;
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}
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spin_lock(&ds_lock);
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/*
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* Check for race - another CPU could have allocated
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* it meanwhile:
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*/
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spin_lock_irqsave(&ds_lock, irq);
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if (*p_context) {
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kfree(context->ds);
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kfree(context);
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return *p_context;
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context = *p_context;
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} else {
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*p_context = context;
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context->this = p_context;
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context->task = task;
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if (task)
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set_tsk_thread_flag(task, TIF_DS_AREA_MSR);
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if (!task || (task == current))
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wrmsrl(MSR_IA32_DS_AREA,
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(unsigned long)context->ds);
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}
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*p_context = context;
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context->this = p_context;
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context->task = task;
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if (task)
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set_tsk_thread_flag(task, TIF_DS_AREA_MSR);
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if (!task || (task == current))
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wrmsr(MSR_IA32_DS_AREA, (unsigned long)context->ds, 0);
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get_tracer(task);
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spin_unlock_irqrestore(&ds_lock, irq);
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}
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context->count++;
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@ -288,10 +278,12 @@ static inline struct ds_context *ds_alloc_context(struct task_struct *task)
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*/
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static inline void ds_put_context(struct ds_context *context)
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{
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unsigned long irq;
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if (!context)
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return;
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spin_lock(&ds_lock);
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spin_lock_irqsave(&ds_lock, irq);
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if (--context->count)
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goto out;
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@ -313,7 +305,7 @@ static inline void ds_put_context(struct ds_context *context)
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kfree(context->ds);
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kfree(context);
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out:
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spin_unlock(&ds_lock);
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spin_unlock_irqrestore(&ds_lock, irq);
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}
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@ -384,6 +376,7 @@ static int ds_request(struct task_struct *task, void *base, size_t size,
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struct ds_context *context;
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unsigned long buffer, adj;
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const unsigned long alignment = (1 << 3);
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unsigned long irq;
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int error = 0;
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if (!ds_cfg.sizeof_ds)
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@ -398,26 +391,27 @@ static int ds_request(struct task_struct *task, void *base, size_t size,
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return -EOPNOTSUPP;
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spin_lock(&ds_lock);
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error = -ENOMEM;
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context = ds_alloc_context(task);
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if (!context)
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goto out_unlock;
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return -ENOMEM;
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spin_lock_irqsave(&ds_lock, irq);
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error = -EPERM;
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if (!check_tracer(task))
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goto out_unlock;
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get_tracer(task);
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error = -EALREADY;
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if (context->owner[qual] == current)
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goto out_unlock;
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goto out_put_tracer;
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error = -EPERM;
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if (context->owner[qual] != NULL)
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goto out_unlock;
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goto out_put_tracer;
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context->owner[qual] = current;
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spin_unlock(&ds_lock);
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spin_unlock_irqrestore(&ds_lock, irq);
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error = -ENOMEM;
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@ -465,10 +459,17 @@ static int ds_request(struct task_struct *task, void *base, size_t size,
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out_release:
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context->owner[qual] = NULL;
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ds_put_context(context);
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put_tracer(task);
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return error;
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out_put_tracer:
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spin_unlock_irqrestore(&ds_lock, irq);
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ds_put_context(context);
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put_tracer(task);
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return error;
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out_unlock:
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spin_unlock(&ds_lock);
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spin_unlock_irqrestore(&ds_lock, irq);
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ds_put_context(context);
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return error;
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}
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@ -818,13 +819,21 @@ static const struct ds_configuration ds_cfg_var = {
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.sizeof_ds = sizeof(long) * 12,
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.sizeof_field = sizeof(long),
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.sizeof_rec[ds_bts] = sizeof(long) * 3,
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#ifdef __i386__
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.sizeof_rec[ds_pebs] = sizeof(long) * 10
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#else
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.sizeof_rec[ds_pebs] = sizeof(long) * 18
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#endif
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};
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static const struct ds_configuration ds_cfg_64 = {
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.sizeof_ds = 8 * 12,
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.sizeof_field = 8,
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.sizeof_rec[ds_bts] = 8 * 3,
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#ifdef __i386__
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.sizeof_rec[ds_pebs] = 8 * 10
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#else
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.sizeof_rec[ds_pebs] = 8 * 18
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#endif
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};
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static inline void
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@ -878,4 +887,3 @@ void ds_free(struct ds_context *context)
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while (leftovers--)
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ds_put_context(context);
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}
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#endif /* CONFIG_X86_DS */
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@ -58,7 +58,7 @@ void __cpuinit mxcsr_feature_mask_init(void)
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stts();
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}
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void __init init_thread_xstate(void)
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void __cpuinit init_thread_xstate(void)
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{
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if (!HAVE_HWFP) {
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xstate_size = sizeof(struct i387_soft_struct);
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@ -3608,27 +3608,7 @@ int __init io_apic_get_redir_entries (int ioapic)
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int __init probe_nr_irqs(void)
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{
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int idx;
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int nr = 0;
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#ifndef CONFIG_XEN
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int nr_min = 32;
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#else
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int nr_min = NR_IRQS;
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#endif
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for (idx = 0; idx < nr_ioapics; idx++)
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nr += io_apic_get_redir_entries(idx) + 1;
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/* double it for hotplug and msi and nmi */
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nr <<= 1;
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/* something wrong ? */
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if (nr < nr_min)
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nr = nr_min;
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if (WARN_ON(nr > NR_IRQS))
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nr = NR_IRQS;
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return nr;
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return NR_IRQS;
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}
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/* --------------------------------------------------------------------------
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@ -1567,7 +1567,7 @@ static int __init calgary_parse_options(char *p)
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++p;
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if (*p == '\0')
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break;
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bridge = simple_strtol(p, &endp, 0);
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bridge = simple_strtoul(p, &endp, 0);
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if (p == endp)
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break;
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@ -310,7 +310,7 @@ static void __init setup_xstate_init(void)
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/*
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* Enable and initialize the xsave feature.
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*/
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void __init xsave_cntxt_init(void)
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void __ref xsave_cntxt_init(void)
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{
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unsigned int eax, ebx, ecx, edx;
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@ -69,7 +69,7 @@ static void ppro_setup_ctrs(struct op_msrs const * const msrs)
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int i;
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if (!reset_value) {
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reset_value = kmalloc(sizeof(unsigned) * num_counters,
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reset_value = kmalloc(sizeof(reset_value[0]) * num_counters,
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GFP_ATOMIC);
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if (!reset_value)
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return;
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@ -496,21 +496,24 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015,
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pci_siemens_interrupt_controller);
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/*
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* Regular PCI devices have 256 bytes, but AMD Family 10h Opteron ext config
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* have 4096 bytes. Even if the device is capable, that doesn't mean we can
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* access it. Maybe we don't have a way to generate extended config space
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* accesses. So check it
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* Regular PCI devices have 256 bytes, but AMD Family 10h/11h CPUs have
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* 4096 bytes configuration space for each function of their processor
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* configuration space.
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*/
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static void fam10h_pci_cfg_space_size(struct pci_dev *dev)
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static void amd_cpu_pci_cfg_space_size(struct pci_dev *dev)
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{
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dev->cfg_size = pci_cfg_space_size_ext(dev);
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1200, fam10h_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1201, fam10h_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1202, fam10h_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1203, fam10h_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1204, fam10h_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1200, amd_cpu_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1201, amd_cpu_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1202, amd_cpu_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1203, amd_cpu_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1204, amd_cpu_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1300, amd_cpu_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1301, amd_cpu_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1302, amd_cpu_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1303, amd_cpu_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1304, amd_cpu_pci_cfg_space_size);
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/*
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* SB600: Disable BAR1 on device 14.0 to avoid HPET resources from
|
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|
@ -661,12 +661,11 @@ void xen_set_pgd(pgd_t *ptr, pgd_t val)
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* For 64-bit, we must skip the Xen hole in the middle of the address
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* space, just after the big x86-64 virtual hole.
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*/
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static int xen_pgd_walk(struct mm_struct *mm,
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int (*func)(struct mm_struct *mm, struct page *,
|
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enum pt_level),
|
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unsigned long limit)
|
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static int __xen_pgd_walk(struct mm_struct *mm, pgd_t *pgd,
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int (*func)(struct mm_struct *mm, struct page *,
|
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enum pt_level),
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unsigned long limit)
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{
|
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pgd_t *pgd = mm->pgd;
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int flush = 0;
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unsigned hole_low, hole_high;
|
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unsigned pgdidx_limit, pudidx_limit, pmdidx_limit;
|
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@ -753,6 +752,14 @@ out:
|
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return flush;
|
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}
|
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|
||||
static int xen_pgd_walk(struct mm_struct *mm,
|
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int (*func)(struct mm_struct *mm, struct page *,
|
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enum pt_level),
|
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unsigned long limit)
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{
|
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return __xen_pgd_walk(mm, mm->pgd, func, limit);
|
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}
|
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|
||||
/* If we're using split pte locks, then take the page's lock and
|
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return a pointer to it. Otherwise return NULL. */
|
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static spinlock_t *xen_pte_lock(struct page *page, struct mm_struct *mm)
|
||||
@ -854,7 +861,7 @@ static void __xen_pgd_pin(struct mm_struct *mm, pgd_t *pgd)
|
||||
|
||||
xen_mc_batch();
|
||||
|
||||
if (xen_pgd_walk(mm, xen_pin_page, USER_LIMIT)) {
|
||||
if (__xen_pgd_walk(mm, pgd, xen_pin_page, USER_LIMIT)) {
|
||||
/* re-enable interrupts for flushing */
|
||||
xen_mc_issue(0);
|
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||||
@ -998,7 +1005,7 @@ static void __xen_pgd_unpin(struct mm_struct *mm, pgd_t *pgd)
|
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PT_PMD);
|
||||
#endif
|
||||
|
||||
xen_pgd_walk(mm, xen_unpin_page, USER_LIMIT);
|
||||
__xen_pgd_walk(mm, pgd, xen_unpin_page, USER_LIMIT);
|
||||
|
||||
xen_mc_issue(0);
|
||||
}
|
||||
|
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