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ARC: [arcfpga] RIP legacy ISS based SMP extension
With ISS long unsupported, no point in having extension based on it Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta
parent
40b552d95a
commit
6623146cb7
@ -14,20 +14,3 @@ menuconfig ARC_PLAT_FPGA_LEGACY
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These are based on FPGA or ISS. e.g.
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- ARCAngel4
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- ML509
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- MetaWare ISS
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if ARC_PLAT_FPGA_LEGACY
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config ISS_SMP_EXTN
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bool "ARC SMP Extensions (ISS Models only)"
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default n
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depends on SMP
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help
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SMP Extensions to ARC700, in a "simulation only" Model, supported in
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ARC ISS (Instruction Set Simulator).
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The SMP extensions include:
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-IDU (Interrupt Distribution Unit)
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-XTL (To enable CPU start/stop/set-PC for another CPU)
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It doesn't provide coherent Caches and/or Atomic Ops (LLOCK/SCOND)
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endif
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@ -6,7 +6,4 @@
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# published by the Free Software Foundation.
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#
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KBUILD_CFLAGS += -Iarch/arc/plat-arcfpga/include
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obj-y := platform.o
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obj-$(CONFIG_ISS_SMP_EXTN) += smp.o
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@ -1,118 +0,0 @@
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Rajeshwar Ranga: Interrupt Distribution Unit API's
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*/
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#ifndef __PLAT_ARCFPGA_SMP_H
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#define __PLAT_ARCFPGA_SMP_H
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#ifdef CONFIG_SMP
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#include <linux/types.h>
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#include <asm/arcregs.h>
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#define ARC_AUX_IDU_REG_CMD 0x2000
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#define ARC_AUX_IDU_REG_PARAM 0x2001
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#define ARC_AUX_XTL_REG_CMD 0x2002
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#define ARC_AUX_XTL_REG_PARAM 0x2003
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#define ARC_REG_MP_BCR 0x2021
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#define ARC_XTL_CMD_WRITE_PC 0x04
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#define ARC_XTL_CMD_CLEAR_HALT 0x02
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/*
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* Build Configuration Register which identifies the sub-components
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*/
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struct bcr_mp {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int mp_arch:16, pad:5, sdu:1, idu:1, scu:1, ver:8;
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#else
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unsigned int ver:8, scu:1, idu:1, sdu:1, pad:5, mp_arch:16;
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#endif
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};
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/* IDU supports 256 common interrupts */
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#define NR_IDU_IRQS 256
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/*
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* The Aux Regs layout is same bit-by-bit in both BE/LE modes.
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* However when casted as a bitfield encoded "C" struct, gcc treats it as
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* memory, generating different code for BE/LE, requiring strcture adj (see
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* include/asm/arcregs.h)
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*
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* However when manually "carving" the value for a Aux, no special handling
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* of BE is needed because of the property discribed above
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*/
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#define IDU_SET_COMMAND(irq, cmd) \
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do { \
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uint32_t __val; \
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__val = (((irq & 0xFF) << 8) | (cmd & 0xFF)); \
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write_aux_reg(ARC_AUX_IDU_REG_CMD, __val); \
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} while (0)
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#define IDU_SET_PARAM(par) write_aux_reg(ARC_AUX_IDU_REG_PARAM, par)
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#define IDU_GET_PARAM() read_aux_reg(ARC_AUX_IDU_REG_PARAM)
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/* IDU Commands */
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#define IDU_DISABLE 0x00
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#define IDU_ENABLE 0x01
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#define IDU_IRQ_CLEAR 0x02
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#define IDU_IRQ_ASSERT 0x03
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#define IDU_IRQ_WMODE 0x04
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#define IDU_IRQ_STATUS 0x05
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#define IDU_IRQ_ACK 0x06
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#define IDU_IRQ_PEND 0x07
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#define IDU_IRQ_RMODE 0x08
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#define IDU_IRQ_WBITMASK 0x09
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#define IDU_IRQ_RBITMASK 0x0A
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#define idu_enable() IDU_SET_COMMAND(0, IDU_ENABLE)
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#define idu_disable() IDU_SET_COMMAND(0, IDU_DISABLE)
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#define idu_irq_assert(irq) IDU_SET_COMMAND((irq), IDU_IRQ_ASSERT)
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#define idu_irq_clear(irq) IDU_SET_COMMAND((irq), IDU_IRQ_CLEAR)
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/* IDU Interrupt Mode - Destination Encoding */
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#define IDU_IRQ_MOD_DISABLE 0x00
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#define IDU_IRQ_MOD_ROUND_RECP 0x01
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#define IDU_IRQ_MOD_TCPU_FIRSTRECP 0x02
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#define IDU_IRQ_MOD_TCPU_ALLRECP 0x03
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/* IDU Interrupt Mode - Triggering Mode */
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#define IDU_IRQ_MODE_LEVEL_TRIG 0x00
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#define IDU_IRQ_MODE_PULSE_TRIG 0x01
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#define IDU_IRQ_MODE_PARAM(dest_mode, trig_mode) \
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(((trig_mode & 0x01) << 15) | (dest_mode & 0xFF))
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struct idu_irq_config {
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uint8_t irq;
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uint8_t dest_mode;
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uint8_t trig_mode;
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};
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struct idu_irq_status {
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uint8_t irq;
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bool enabled;
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bool status;
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bool ack;
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bool pend;
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uint8_t next_rr;
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};
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extern void idu_irq_set_tgtcpu(uint8_t irq, uint32_t mask);
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extern void idu_irq_set_mode(uint8_t irq, uint8_t dest_mode, uint8_t trig_mode);
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extern void iss_model_init_smp(unsigned int cpu);
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extern void iss_model_init_early_smp(void);
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#endif /* CONFIG_SMP */
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#endif
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@ -10,7 +10,6 @@
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#include <linux/init.h>
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#include <asm/mach_desc.h>
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#include <plat/smp.h>
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/*----------------------- Machine Descriptions ------------------------------
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*
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@ -28,10 +27,6 @@ static const char *legacy_fpga_compat[] __initconst = {
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MACHINE_START(LEGACY_FPGA, "legacy_fpga")
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.dt_compat = legacy_fpga_compat,
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#ifdef CONFIG_ISS_SMP_EXTN
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.init_early = iss_model_init_early_smp,
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.init_smp = iss_model_init_smp,
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#endif
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MACHINE_END
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static const char *simulation_compat[] __initconst = {
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@ -1,186 +0,0 @@
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/*
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* ARC700 Simulation-only Extensions for SMP
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*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Vineet Gupta - 2012 : split off arch common and plat specific SMP
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* Rajeshwar Ranga - 2007 : Interrupt Distribution Unit API's
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*/
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#include <linux/smp.h>
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#include <linux/irq.h>
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#include <plat/smp.h>
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#define IDU_INTERRUPT_0 16
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static char smp_cpuinfo_buf[128];
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/*
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*-------------------------------------------------------------------
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* Platform specific callbacks expected by arch SMP code
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*-------------------------------------------------------------------
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*/
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/*
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* Master kick starting another CPU
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*/
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static void iss_model_smp_wakeup_cpu(int cpu, unsigned long pc)
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{
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/* setup the start PC */
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write_aux_reg(ARC_AUX_XTL_REG_PARAM, pc);
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/* Trigger WRITE_PC cmd for this cpu */
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write_aux_reg(ARC_AUX_XTL_REG_CMD,
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(ARC_XTL_CMD_WRITE_PC | (cpu << 8)));
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/* Take the cpu out of Halt */
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write_aux_reg(ARC_AUX_XTL_REG_CMD,
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(ARC_XTL_CMD_CLEAR_HALT | (cpu << 8)));
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}
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static inline int get_hw_config_num_irq(void)
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{
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uint32_t val = read_aux_reg(ARC_REG_VECBASE_BCR);
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switch (val & 0x03) {
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case 0:
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return 16;
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case 1:
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return 32;
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case 2:
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return 8;
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default:
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return 0;
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}
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return 0;
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}
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/*
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* Any SMP specific init any CPU does when it comes up.
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* Here we setup the CPU to enable Inter-Processor-Interrupts
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* Called for each CPU
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* -Master : init_IRQ()
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* -Other(s) : start_kernel_secondary()
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*/
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void iss_model_init_smp(unsigned int cpu)
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{
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/* Check if CPU is configured for more than 16 interrupts */
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if (NR_IRQS <= 16 || get_hw_config_num_irq() <= 16)
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panic("[arcfpga] IRQ system can't support IDU IPI\n");
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idu_disable();
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/****************************************************************
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* IDU provides a set of Common IRQs, each of which can be dynamically
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* attached to (1|many|all) CPUs.
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* The Common IRQs [0-15] are mapped as CPU pvt [16-31]
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*
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* Here we use a simple 1:1 mapping:
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* A CPU 'x' is wired to Common IRQ 'x'.
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* So an IDU ASSERT on IRQ 'x' will trigger Interupt on CPU 'x', which
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* makes up for our simple IPI plumbing.
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*
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* TBD: Have a dedicated multicast IRQ for sending IPIs to all CPUs
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* w/o having to do one-at-a-time
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******************************************************************/
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/*
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* Claim an IRQ which would trigger IPI on this CPU.
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* In IDU parlance it involves setting up a cpu bitmask for the IRQ
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* The bitmap here contains only 1 CPU (self).
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*/
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idu_irq_set_tgtcpu(cpu, 0x1 << cpu);
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/* Set the IRQ destination to use the bitmask above */
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idu_irq_set_mode(cpu, 7, /* XXX: IDU_IRQ_MOD_TCPU_ALLRECP: ISS bug */
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IDU_IRQ_MODE_PULSE_TRIG);
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idu_enable();
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/* Attach the arch-common IPI ISR to our IDU IRQ */
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smp_ipi_irq_setup(cpu, IDU_INTERRUPT_0 + cpu);
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}
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static void iss_model_ipi_send(int cpu)
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{
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idu_irq_assert(cpu);
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}
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static void iss_model_ipi_clear(int irq)
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{
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idu_irq_clear(IDU_INTERRUPT_0 + smp_processor_id());
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}
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void iss_model_init_early_smp(void)
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{
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#define IS_AVAIL1(var, str) ((var) ? str : "")
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struct bcr_mp mp;
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READ_BCR(ARC_REG_MP_BCR, mp);
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sprintf(smp_cpuinfo_buf, "Extn [ISS-SMP]: v%d, arch(%d) %s %s %s\n",
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mp.ver, mp.mp_arch, IS_AVAIL1(mp.scu, "SCU"),
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IS_AVAIL1(mp.idu, "IDU"), IS_AVAIL1(mp.sdu, "SDU"));
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plat_smp_ops.info = smp_cpuinfo_buf;
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plat_smp_ops.cpu_kick = iss_model_smp_wakeup_cpu;
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plat_smp_ops.ipi_send = iss_model_ipi_send;
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plat_smp_ops.ipi_clear = iss_model_ipi_clear;
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}
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/*
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*-------------------------------------------------------------------
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* Low level Platform IPI Providers
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*-------------------------------------------------------------------
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*/
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/* Set the Mode for the Common IRQ */
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void idu_irq_set_mode(uint8_t irq, uint8_t dest_mode, uint8_t trig_mode)
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{
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uint32_t par = IDU_IRQ_MODE_PARAM(dest_mode, trig_mode);
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IDU_SET_PARAM(par);
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IDU_SET_COMMAND(irq, IDU_IRQ_WMODE);
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}
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/* Set the target cpu Bitmask for Common IRQ */
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void idu_irq_set_tgtcpu(uint8_t irq, uint32_t mask)
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{
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IDU_SET_PARAM(mask);
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IDU_SET_COMMAND(irq, IDU_IRQ_WBITMASK);
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}
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/* Get the Interrupt Acknowledged status for IRQ (as CPU Bitmask) */
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bool idu_irq_get_ack(uint8_t irq)
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{
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uint32_t val;
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IDU_SET_COMMAND(irq, IDU_IRQ_ACK);
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val = IDU_GET_PARAM();
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return val & (1 << irq);
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}
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/*
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* Get the Interrupt Pending status for IRQ (as CPU Bitmask)
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* -Pending means CPU has not yet noticed the IRQ (e.g. disabled)
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* -After Interrupt has been taken, the IPI expcitily needs to be
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* cleared, to be acknowledged.
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*/
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bool idu_irq_get_pend(uint8_t irq)
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{
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uint32_t val;
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IDU_SET_COMMAND(irq, IDU_IRQ_PEND);
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val = IDU_GET_PARAM();
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return val & (1 << irq);
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}
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