mirror of
https://github.com/edk2-porting/linux-next.git
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net: ethernet: stmmac: add adaptation for stm32mp157c.
Glue codes to support stm32mp157c device and stay compatible with stm32 mcu familly Signed-off-by: Christophe Roullier <christophe.roullier@st.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Christophe Roullier
David S. Miller
parent
a98ac8bd24
commit
6528e02cc9
@ -16,49 +16,180 @@
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#include <linux/of_net.h>
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#include <linux/pm_wakeirq.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/stmmac.h>
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#include "stmmac_platform.h"
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#define MII_PHY_SEL_MASK BIT(23)
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#define SYSCFG_MCU_ETH_MASK BIT(23)
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#define SYSCFG_MP1_ETH_MASK GENMASK(23, 16)
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#define SYSCFG_PMCR_ETH_CLK_SEL BIT(16)
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#define SYSCFG_PMCR_ETH_REF_CLK_SEL BIT(17)
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#define SYSCFG_PMCR_ETH_SEL_MII BIT(20)
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#define SYSCFG_PMCR_ETH_SEL_RGMII BIT(21)
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#define SYSCFG_PMCR_ETH_SEL_RMII BIT(23)
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#define SYSCFG_PMCR_ETH_SEL_GMII 0
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#define SYSCFG_MCU_ETH_SEL_MII 0
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#define SYSCFG_MCU_ETH_SEL_RMII 1
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struct stm32_dwmac {
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struct clk *clk_tx;
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struct clk *clk_rx;
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struct clk *clk_eth_ck;
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struct clk *clk_ethstp;
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struct clk *syscfg_clk;
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bool int_phyclk; /* Clock from RCC to drive PHY */
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u32 mode_reg; /* MAC glue-logic mode register */
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struct regmap *regmap;
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u32 speed;
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const struct stm32_ops *ops;
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struct device *dev;
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};
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struct stm32_ops {
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int (*set_mode)(struct plat_stmmacenet_data *plat_dat);
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int (*clk_prepare)(struct stm32_dwmac *dwmac, bool prepare);
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int (*suspend)(struct stm32_dwmac *dwmac);
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void (*resume)(struct stm32_dwmac *dwmac);
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int (*parse_data)(struct stm32_dwmac *dwmac,
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struct device *dev);
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u32 syscfg_eth_mask;
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};
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static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat)
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{
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struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
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u32 reg = dwmac->mode_reg;
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u32 val;
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int ret;
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val = (plat_dat->interface == PHY_INTERFACE_MODE_MII) ? 0 : 1;
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ret = regmap_update_bits(dwmac->regmap, reg, MII_PHY_SEL_MASK, val);
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if (ret)
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return ret;
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if (dwmac->ops->set_mode) {
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ret = dwmac->ops->set_mode(plat_dat);
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if (ret)
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return ret;
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}
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ret = clk_prepare_enable(dwmac->clk_tx);
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if (ret)
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return ret;
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ret = clk_prepare_enable(dwmac->clk_rx);
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if (ret)
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clk_disable_unprepare(dwmac->clk_tx);
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if (!dwmac->dev->power.is_suspended) {
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ret = clk_prepare_enable(dwmac->clk_rx);
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if (ret) {
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clk_disable_unprepare(dwmac->clk_tx);
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return ret;
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}
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}
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if (dwmac->ops->clk_prepare) {
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ret = dwmac->ops->clk_prepare(dwmac, true);
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if (ret) {
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clk_disable_unprepare(dwmac->clk_rx);
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clk_disable_unprepare(dwmac->clk_tx);
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}
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}
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return ret;
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}
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static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, bool prepare)
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{
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int ret = 0;
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if (prepare) {
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ret = clk_prepare_enable(dwmac->syscfg_clk);
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if (ret)
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return ret;
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if (dwmac->int_phyclk) {
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ret = clk_prepare_enable(dwmac->clk_eth_ck);
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if (ret) {
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clk_disable_unprepare(dwmac->syscfg_clk);
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return ret;
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}
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}
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} else {
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clk_disable_unprepare(dwmac->syscfg_clk);
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if (dwmac->int_phyclk)
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clk_disable_unprepare(dwmac->clk_eth_ck);
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}
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return ret;
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}
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static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
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{
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struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
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u32 reg = dwmac->mode_reg;
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int val;
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switch (plat_dat->interface) {
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case PHY_INTERFACE_MODE_MII:
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val = SYSCFG_PMCR_ETH_SEL_MII;
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pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
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break;
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case PHY_INTERFACE_MODE_GMII:
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val = SYSCFG_PMCR_ETH_SEL_GMII;
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if (dwmac->int_phyclk)
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val |= SYSCFG_PMCR_ETH_CLK_SEL;
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pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n");
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break;
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case PHY_INTERFACE_MODE_RMII:
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val = SYSCFG_PMCR_ETH_SEL_RMII;
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if (dwmac->int_phyclk)
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val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;
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pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
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break;
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case PHY_INTERFACE_MODE_RGMII:
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val = SYSCFG_PMCR_ETH_SEL_RGMII;
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if (dwmac->int_phyclk)
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val |= SYSCFG_PMCR_ETH_CLK_SEL;
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pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n");
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break;
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default:
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pr_debug("SYSCFG init : Do not manage %d interface\n",
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plat_dat->interface);
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/* Do not manage others interfaces */
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return -EINVAL;
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}
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return regmap_update_bits(dwmac->regmap, reg,
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dwmac->ops->syscfg_eth_mask, val);
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}
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static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat)
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{
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struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
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u32 reg = dwmac->mode_reg;
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int val;
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switch (plat_dat->interface) {
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case PHY_INTERFACE_MODE_MII:
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val = SYSCFG_MCU_ETH_SEL_MII;
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pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
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break;
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case PHY_INTERFACE_MODE_RMII:
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val = SYSCFG_MCU_ETH_SEL_RMII;
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pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
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break;
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default:
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pr_debug("SYSCFG init : Do not manage %d interface\n",
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plat_dat->interface);
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/* Do not manage others interfaces */
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return -EINVAL;
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}
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return regmap_update_bits(dwmac->regmap, reg,
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dwmac->ops->syscfg_eth_mask, val);
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}
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static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac)
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{
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clk_disable_unprepare(dwmac->clk_tx);
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clk_disable_unprepare(dwmac->clk_rx);
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if (dwmac->ops->clk_prepare)
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dwmac->ops->clk_prepare(dwmac, false);
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}
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static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
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@ -70,15 +201,22 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
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/* Get TX/RX clocks */
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dwmac->clk_tx = devm_clk_get(dev, "mac-clk-tx");
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if (IS_ERR(dwmac->clk_tx)) {
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dev_err(dev, "No tx clock provided...\n");
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dev_err(dev, "No ETH Tx clock provided...\n");
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return PTR_ERR(dwmac->clk_tx);
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}
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dwmac->clk_rx = devm_clk_get(dev, "mac-clk-rx");
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if (IS_ERR(dwmac->clk_rx)) {
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dev_err(dev, "No rx clock provided...\n");
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dev_err(dev, "No ETH Rx clock provided...\n");
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return PTR_ERR(dwmac->clk_rx);
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}
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if (dwmac->ops->parse_data) {
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err = dwmac->ops->parse_data(dwmac, dev);
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if (err)
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return err;
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}
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/* Get mode register */
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dwmac->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon");
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if (IS_ERR(dwmac->regmap))
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@ -91,11 +229,46 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
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return err;
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}
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static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
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struct device *dev)
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{
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struct device_node *np = dev->of_node;
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dwmac->int_phyclk = of_property_read_bool(np, "st,int-phyclk");
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/* Check if internal clk from RCC selected */
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if (dwmac->int_phyclk) {
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/* Get ETH_CLK clocks */
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dwmac->clk_eth_ck = devm_clk_get(dev, "eth-ck");
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if (IS_ERR(dwmac->clk_eth_ck)) {
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dev_err(dev, "No ETH CK clock provided...\n");
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return PTR_ERR(dwmac->clk_eth_ck);
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}
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}
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/* Clock used for low power mode */
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dwmac->clk_ethstp = devm_clk_get(dev, "ethstp");
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if (IS_ERR(dwmac->clk_ethstp)) {
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dev_err(dev, "No ETH peripheral clock provided for CStop mode ...\n");
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return PTR_ERR(dwmac->clk_ethstp);
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}
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/* Clock for sysconfig */
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dwmac->syscfg_clk = devm_clk_get(dev, "syscfg-clk");
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if (IS_ERR(dwmac->syscfg_clk)) {
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dev_err(dev, "No syscfg clock provided...\n");
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return PTR_ERR(dwmac->syscfg_clk);
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}
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return 0;
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}
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static int stm32_dwmac_probe(struct platform_device *pdev)
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{
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struct plat_stmmacenet_data *plat_dat;
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struct stmmac_resources stmmac_res;
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struct stm32_dwmac *dwmac;
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const struct stm32_ops *data;
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int ret;
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ret = stmmac_get_platform_resources(pdev, &stmmac_res);
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@ -112,6 +285,16 @@ static int stm32_dwmac_probe(struct platform_device *pdev)
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goto err_remove_config_dt;
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}
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data = of_device_get_match_data(&pdev->dev);
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if (!data) {
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dev_err(&pdev->dev, "no of match data provided\n");
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ret = -EINVAL;
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goto err_remove_config_dt;
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}
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dwmac->ops = data;
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dwmac->dev = &pdev->dev;
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ret = stm32_dwmac_parse_data(dwmac, &pdev->dev);
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if (ret) {
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dev_err(&pdev->dev, "Unable to parse OF data\n");
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@ -149,15 +332,48 @@ static int stm32_dwmac_remove(struct platform_device *pdev)
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return ret;
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}
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static int stm32mp1_suspend(struct stm32_dwmac *dwmac)
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{
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int ret = 0;
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ret = clk_prepare_enable(dwmac->clk_ethstp);
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if (ret)
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return ret;
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clk_disable_unprepare(dwmac->clk_tx);
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clk_disable_unprepare(dwmac->syscfg_clk);
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if (dwmac->int_phyclk)
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clk_disable_unprepare(dwmac->clk_eth_ck);
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return ret;
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}
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static void stm32mp1_resume(struct stm32_dwmac *dwmac)
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{
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clk_disable_unprepare(dwmac->clk_ethstp);
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}
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static int stm32mcu_suspend(struct stm32_dwmac *dwmac)
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{
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clk_disable_unprepare(dwmac->clk_tx);
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clk_disable_unprepare(dwmac->clk_rx);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int stm32_dwmac_suspend(struct device *dev)
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{
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struct net_device *ndev = dev_get_drvdata(dev);
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struct stmmac_priv *priv = netdev_priv(ndev);
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struct stm32_dwmac *dwmac = priv->plat->bsp_priv;
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int ret;
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ret = stmmac_suspend(dev);
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stm32_dwmac_clk_disable(priv->plat->bsp_priv);
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if (dwmac->ops->suspend)
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ret = dwmac->ops->suspend(dwmac);
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return ret;
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}
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@ -166,8 +382,12 @@ static int stm32_dwmac_resume(struct device *dev)
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{
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struct net_device *ndev = dev_get_drvdata(dev);
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struct stmmac_priv *priv = netdev_priv(ndev);
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struct stm32_dwmac *dwmac = priv->plat->bsp_priv;
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int ret;
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if (dwmac->ops->resume)
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dwmac->ops->resume(dwmac);
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ret = stm32_dwmac_init(priv->plat);
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if (ret)
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return ret;
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@ -181,8 +401,24 @@ static int stm32_dwmac_resume(struct device *dev)
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static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops,
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stm32_dwmac_suspend, stm32_dwmac_resume);
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static struct stm32_ops stm32mcu_dwmac_data = {
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.set_mode = stm32mcu_set_mode,
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.suspend = stm32mcu_suspend,
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.syscfg_eth_mask = SYSCFG_MCU_ETH_MASK
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};
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static struct stm32_ops stm32mp1_dwmac_data = {
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.set_mode = stm32mp1_set_mode,
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.clk_prepare = stm32mp1_clk_prepare,
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.suspend = stm32mp1_suspend,
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.resume = stm32mp1_resume,
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.parse_data = stm32mp1_parse_data,
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.syscfg_eth_mask = SYSCFG_MP1_ETH_MASK
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};
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static const struct of_device_id stm32_dwmac_match[] = {
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{ .compatible = "st,stm32-dwmac"},
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{ .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data},
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{ .compatible = "st,stm32mp1-dwmac", .data = &stm32mp1_dwmac_data},
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{ }
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};
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MODULE_DEVICE_TABLE(of, stm32_dwmac_match);
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@ -199,5 +435,6 @@ static struct platform_driver stm32_dwmac_driver = {
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module_platform_driver(stm32_dwmac_driver);
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MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@gmail.com>");
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MODULE_DESCRIPTION("STMicroelectronics MCU DWMAC Specific Glue layer");
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MODULE_AUTHOR("Christophe Roullier <christophe.roullier@st.com>");
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MODULE_DESCRIPTION("STMicroelectronics STM32 DWMAC Specific Glue layer");
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MODULE_LICENSE("GPL v2");
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