mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-24 05:04:00 +08:00
clk: sunxi-ng: h3: Allow parent change for ve clock
Cedrus driver wants to set VE clock higher than it's possible without changing parent rate. In order to correct that, allow changing parent rate for VE clock. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This commit is contained in:
parent
0380126eb9
commit
64f28430cf
@ -481,7 +481,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
|
||||
0x134, 0, 5, 8, 3, BIT(15), 0);
|
||||
|
||||
static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
|
||||
0x13c, 16, 3, BIT(31), 0);
|
||||
0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
|
||||
|
||||
static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
|
||||
0x140, BIT(31), CLK_SET_RATE_PARENT);
|
||||
|
Loading…
Reference in New Issue
Block a user