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ARM: imx: add suspend in ocram support for i.mx6sl

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i.MX6SL's suspend in ocram function is derived from i.MX6Q,
it can lower the DDR IO power from ~10mA@1.2V to ~1mA@1.2V,
measured on i.MX6SL EVK board, SH5.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Anson Huang 2014-01-17 11:39:07 +08:00 committed by Shawn Guo
parent da9e926135
commit 64b0868139
3 changed files with 61 additions and 4 deletions
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2
arch/arm/mach-imx/Makefile
View File

@ -105,7 +105,7 @@ obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o suspend-imx6.o obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o suspend-imx6.o
# i.MX6SL reuses i.MX6Q code # i.MX6SL reuses i.MX6Q code
obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o suspend-imx6.o
# i.MX5 based machines # i.MX5 based machines
obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o

20
arch/arm/mach-imx/pm-imx6q.c
View File

@ -121,6 +121,14 @@ static const u32 imx6dl_mmdc_io_offset[] __initconst = {
0x74c, /* GPR_ADDS */ 0x74c, /* GPR_ADDS */
}; };
static const u32 imx6sl_mmdc_io_offset[] __initconst = {
0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */
};
static const struct imx6_pm_socdata imx6q_pm_data __initconst = { static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
.cpu_type = MXC_CPU_IMX6Q, .cpu_type = MXC_CPU_IMX6Q,
.mmdc_compat = "fsl,imx6q-mmdc", .mmdc_compat = "fsl,imx6q-mmdc",
@ -141,6 +149,16 @@ static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
.mmdc_io_offset = imx6dl_mmdc_io_offset, .mmdc_io_offset = imx6dl_mmdc_io_offset,
}; };
static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
.cpu_type = MXC_CPU_IMX6SL,
.mmdc_compat = "fsl,imx6sl-mmdc",
.src_compat = "fsl,imx6sl-src",
.iomuxc_compat = "fsl,imx6sl-iomuxc",
.gpc_compat = "fsl,imx6sl-gpc",
.mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
.mmdc_io_offset = imx6sl_mmdc_io_offset,
};
/* /*
* This structure is for passing necessary data for low level ocram * This structure is for passing necessary data for low level ocram
* suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
@ -530,5 +548,5 @@ void __init imx6dl_pm_init(void)
void __init imx6sl_pm_init(void) void __init imx6sl_pm_init(void)
{ {
imx6_pm_common_init(NULL); imx6_pm_common_init(&imx6sl_pm_data);
} }

43
arch/arm/mach-imx/suspend-imx6.S
View File

@ -63,6 +63,7 @@
#define MX6Q_SRC_GPR1 0x20 #define MX6Q_SRC_GPR1 0x20
#define MX6Q_SRC_GPR2 0x24 #define MX6Q_SRC_GPR2 0x24
#define MX6Q_MMDC_MAPSR 0x404 #define MX6Q_MMDC_MAPSR 0x404
#define MX6Q_MMDC_MPDGCTRL0 0x83c
#define MX6Q_GPC_IMR1 0x08 #define MX6Q_GPC_IMR1 0x08
#define MX6Q_GPC_IMR2 0x0c #define MX6Q_GPC_IMR2 0x0c
#define MX6Q_GPC_IMR3 0x10 #define MX6Q_GPC_IMR3 0x10
@ -107,14 +108,36 @@
ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
cmp r3, #MXC_CPU_IMX6SL
bne 4f
/* reset read FIFO, RST_RD_FIFO */
ldr r7, =MX6Q_MMDC_MPDGCTRL0
ldr r6, [r11, r7]
orr r6, r6, #(1 << 31)
str r6, [r11, r7]
2:
ldr r6, [r11, r7]
ands r6, r6, #(1 << 31)
bne 2b
/* reset FIFO a second time */
ldr r6, [r11, r7]
orr r6, r6, #(1 << 31)
str r6, [r11, r7]
3:
ldr r6, [r11, r7]
ands r6, r6, #(1 << 31)
bne 3b
4:
/* let DDR out of self-refresh */ /* let DDR out of self-refresh */
ldr r7, [r11, #MX6Q_MMDC_MAPSR] ldr r7, [r11, #MX6Q_MMDC_MAPSR]
bic r7, r7, #(1 << 21) bic r7, r7, #(1 << 21)
str r7, [r11, #MX6Q_MMDC_MAPSR] str r7, [r11, #MX6Q_MMDC_MAPSR]
2: 5:
ldr r7, [r11, #MX6Q_MMDC_MAPSR] ldr r7, [r11, #MX6Q_MMDC_MAPSR]
ands r7, r7, #(1 << 25) ands r7, r7, #(1 << 25)
bne 2b bne 5b
/* enable DDR auto power saving */ /* enable DDR auto power saving */
ldr r7, [r11, #MX6Q_MMDC_MAPSR] ldr r7, [r11, #MX6Q_MMDC_MAPSR]
@ -182,12 +205,27 @@ poll_dvfs_set:
ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET
add r8, r8, r0 add r8, r8, r0
/* i.MX6SL's last 3 IOs need special setting */
cmp r3, #MXC_CPU_IMX6SL
subeq r7, r7, #0x3
set_mmdc_io_lpm: set_mmdc_io_lpm:
ldr r9, [r8], #0x8 ldr r9, [r8], #0x8
str r6, [r11, r9] str r6, [r11, r9]
subs r7, r7, #0x1 subs r7, r7, #0x1
bne set_mmdc_io_lpm bne set_mmdc_io_lpm
cmp r3, #MXC_CPU_IMX6SL
bne set_mmdc_io_lpm_done
ldr r6, =0x1000
ldr r9, [r8], #0x8
str r6, [r11, r9]
ldr r9, [r8], #0x8
str r6, [r11, r9]
ldr r6, =0x80000
ldr r9, [r8]
str r6, [r11, r9]
set_mmdc_io_lpm_done:
/* /*
* mask all GPC interrupts before * mask all GPC interrupts before
* enabling the RBC counters to * enabling the RBC counters to
@ -282,6 +320,7 @@ resume:
str r7, [r11, #MX6Q_SRC_GPR1] str r7, [r11, #MX6Q_SRC_GPR1]
str r7, [r11, #MX6Q_SRC_GPR2] str r7, [r11, #MX6Q_SRC_GPR2]
ldr r3, [r0, #PM_INFO_CPU_TYPE_OFFSET]
mov r5, #0x1 mov r5, #0x1
resume_mmdc resume_mmdc