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drm/i915: Throw out some useless variables
Drop some useless 'reg' variables when we only use them once. v2: A few more, including a few variable moves Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä
Daniel Vetter
parent
85fa792bee
commit
649636ef82
@ -713,9 +713,8 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
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static u32 g4x_get_vblank_counter(struct drm_device *dev, int pipe)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int reg = PIPE_FRMCOUNT_G4X(pipe);
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return I915_READ(reg);
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return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
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}
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/* raw reads, only for fast reads of display block, no need for forcewake etc. */
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@ -1157,12 +1157,10 @@ static const char *state_string(bool enabled)
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void assert_pll(struct drm_i915_private *dev_priv,
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enum pipe pipe, bool state)
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{
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int reg;
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u32 val;
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bool cur_state;
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reg = DPLL(pipe);
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val = I915_READ(reg);
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val = I915_READ(DPLL(pipe));
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cur_state = !!(val & DPLL_VCO_ENABLE);
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I915_STATE_WARN(cur_state != state,
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"PLL state assertion failure (expected %s, current %s)\n",
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@ -1219,20 +1217,16 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
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static void assert_fdi_tx(struct drm_i915_private *dev_priv,
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enum pipe pipe, bool state)
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{
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int reg;
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u32 val;
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bool cur_state;
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enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
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pipe);
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if (HAS_DDI(dev_priv->dev)) {
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/* DDI does not have a specific FDI_TX register */
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reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
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val = I915_READ(reg);
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u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
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cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
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} else {
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reg = FDI_TX_CTL(pipe);
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val = I915_READ(reg);
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u32 val = I915_READ(FDI_TX_CTL(pipe));
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cur_state = !!(val & FDI_TX_ENABLE);
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}
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I915_STATE_WARN(cur_state != state,
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@ -1245,12 +1239,10 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
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static void assert_fdi_rx(struct drm_i915_private *dev_priv,
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enum pipe pipe, bool state)
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{
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int reg;
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u32 val;
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bool cur_state;
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reg = FDI_RX_CTL(pipe);
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val = I915_READ(reg);
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val = I915_READ(FDI_RX_CTL(pipe));
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cur_state = !!(val & FDI_RX_ENABLE);
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I915_STATE_WARN(cur_state != state,
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"FDI RX state assertion failure (expected %s, current %s)\n",
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@ -1262,7 +1254,6 @@ static void assert_fdi_rx(struct drm_i915_private *dev_priv,
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static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
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enum pipe pipe)
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{
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int reg;
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u32 val;
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/* ILK FDI PLL is always enabled */
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@ -1273,20 +1264,17 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
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if (HAS_DDI(dev_priv->dev))
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return;
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reg = FDI_TX_CTL(pipe);
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val = I915_READ(reg);
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val = I915_READ(FDI_TX_CTL(pipe));
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I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
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}
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void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
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enum pipe pipe, bool state)
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{
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int reg;
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u32 val;
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bool cur_state;
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reg = FDI_RX_CTL(pipe);
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val = I915_READ(reg);
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val = I915_READ(FDI_RX_CTL(pipe));
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cur_state = !!(val & FDI_RX_PLL_ENABLE);
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I915_STATE_WARN(cur_state != state,
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"FDI RX PLL assertion failure (expected %s, current %s)\n",
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@ -1356,8 +1344,6 @@ static void assert_cursor(struct drm_i915_private *dev_priv,
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void assert_pipe(struct drm_i915_private *dev_priv,
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enum pipe pipe, bool state)
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{
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int reg;
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u32 val;
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bool cur_state;
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enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
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pipe);
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@ -1371,8 +1357,7 @@ void assert_pipe(struct drm_i915_private *dev_priv,
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POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
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cur_state = false;
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} else {
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reg = PIPECONF(cpu_transcoder);
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val = I915_READ(reg);
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u32 val = I915_READ(PIPECONF(cpu_transcoder));
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cur_state = !!(val & PIPECONF_ENABLE);
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}
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@ -1384,12 +1369,10 @@ void assert_pipe(struct drm_i915_private *dev_priv,
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static void assert_plane(struct drm_i915_private *dev_priv,
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enum plane plane, bool state)
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{
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int reg;
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u32 val;
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bool cur_state;
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reg = DSPCNTR(plane);
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val = I915_READ(reg);
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val = I915_READ(DSPCNTR(plane));
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cur_state = !!(val & DISPLAY_PLANE_ENABLE);
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I915_STATE_WARN(cur_state != state,
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"plane %c assertion failure (expected %s, current %s)\n",
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@ -1403,14 +1386,11 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
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enum pipe pipe)
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{
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struct drm_device *dev = dev_priv->dev;
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int reg, i;
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u32 val;
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int cur_pipe;
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int i;
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/* Primary planes are fixed to pipes on gen4+ */
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if (INTEL_INFO(dev)->gen >= 4) {
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reg = DSPCNTR(pipe);
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val = I915_READ(reg);
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u32 val = I915_READ(DSPCNTR(pipe));
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I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
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"plane %c assertion failure, should be disabled but not\n",
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plane_name(pipe));
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@ -1419,9 +1399,8 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
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/* Need to check both planes against the pipe */
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for_each_pipe(dev_priv, i) {
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reg = DSPCNTR(i);
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val = I915_READ(reg);
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cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
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u32 val = I915_READ(DSPCNTR(i));
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enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
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DISPPLANE_SEL_PIPE_SHIFT;
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I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
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"plane %c assertion failure, should be off on pipe %c but is still active\n",
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@ -1433,33 +1412,29 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
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enum pipe pipe)
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{
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struct drm_device *dev = dev_priv->dev;
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int reg, sprite;
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u32 val;
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int sprite;
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if (INTEL_INFO(dev)->gen >= 9) {
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for_each_sprite(dev_priv, pipe, sprite) {
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val = I915_READ(PLANE_CTL(pipe, sprite));
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u32 val = I915_READ(PLANE_CTL(pipe, sprite));
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I915_STATE_WARN(val & PLANE_CTL_ENABLE,
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"plane %d assertion failure, should be off on pipe %c but is still active\n",
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sprite, pipe_name(pipe));
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}
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} else if (IS_VALLEYVIEW(dev)) {
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for_each_sprite(dev_priv, pipe, sprite) {
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reg = SPCNTR(pipe, sprite);
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val = I915_READ(reg);
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u32 val = I915_READ(SPCNTR(pipe, sprite));
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I915_STATE_WARN(val & SP_ENABLE,
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"sprite %c assertion failure, should be off on pipe %c but is still active\n",
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sprite_name(pipe, sprite), pipe_name(pipe));
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}
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} else if (INTEL_INFO(dev)->gen >= 7) {
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reg = SPRCTL(pipe);
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val = I915_READ(reg);
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u32 val = I915_READ(SPRCTL(pipe));
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I915_STATE_WARN(val & SPRITE_ENABLE,
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"sprite %c assertion failure, should be off on pipe %c but is still active\n",
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plane_name(pipe), pipe_name(pipe));
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} else if (INTEL_INFO(dev)->gen >= 5) {
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reg = DVSCNTR(pipe);
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val = I915_READ(reg);
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u32 val = I915_READ(DVSCNTR(pipe));
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I915_STATE_WARN(val & DVS_ENABLE,
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"sprite %c assertion failure, should be off on pipe %c but is still active\n",
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plane_name(pipe), pipe_name(pipe));
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@ -1488,12 +1463,10 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
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static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
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enum pipe pipe)
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{
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int reg;
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u32 val;
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bool enabled;
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reg = PCH_TRANSCONF(pipe);
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val = I915_READ(reg);
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val = I915_READ(PCH_TRANSCONF(pipe));
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enabled = !!(val & TRANS_ENABLE);
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I915_STATE_WARN(enabled,
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"transcoder assertion failed, should be off on pipe %c but is still active\n",
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@ -1600,21 +1573,18 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
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static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
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enum pipe pipe)
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{
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int reg;
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u32 val;
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assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
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assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
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assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
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reg = PCH_ADPA;
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val = I915_READ(reg);
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val = I915_READ(PCH_ADPA);
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I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
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"PCH VGA enabled on transcoder %c, should be disabled\n",
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pipe_name(pipe));
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reg = PCH_LVDS;
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val = I915_READ(reg);
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val = I915_READ(PCH_LVDS);
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I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
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"PCH LVDS enabled on transcoder %c, should be disabled\n",
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pipe_name(pipe));
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@ -14949,13 +14919,12 @@ intel_check_plane_mapping(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 reg, val;
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u32 val;
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if (INTEL_INFO(dev)->num_pipes == 1)
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return true;
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reg = DSPCNTR(!crtc->plane);
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val = I915_READ(reg);
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val = I915_READ(DSPCNTR(!crtc->plane));
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if ((val & DISPLAY_PLANE_ENABLE) &&
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(!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
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@ -574,8 +574,6 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
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edp_notifier);
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 pp_div;
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u32 pp_ctrl_reg, pp_div_reg;
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if (!is_edp(intel_dp) || code != SYS_RESTART)
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return 0;
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@ -584,6 +582,8 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
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if (IS_VALLEYVIEW(dev)) {
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enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
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u32 pp_ctrl_reg, pp_div_reg;
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u32 pp_div;
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pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
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pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
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@ -5536,7 +5536,6 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
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struct intel_dp *intel_dp = dev_priv->drrs.dp;
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struct intel_crtc_state *config = NULL;
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struct intel_crtc *intel_crtc = NULL;
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u32 reg, val;
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enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
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if (refresh_rate <= 0) {
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@ -5598,9 +5597,10 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
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DRM_ERROR("Unsupported refreshrate type\n");
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}
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} else if (INTEL_INFO(dev)->gen > 6) {
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reg = PIPECONF(intel_crtc->config->cpu_transcoder);
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val = I915_READ(reg);
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u32 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
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u32 val;
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val = I915_READ(reg);
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if (index > DRRS_HIGH_RR) {
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if (IS_VALLEYVIEW(dev))
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val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
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