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drm/pl111: Handle the Versatile RGB/BGR565 mode

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The ARM Versatile series can do RGB/BGR565 with an external
"PLD" (Programmable Logical Device). However the CLCD does not
have control bits for this, so it needs to be set into the
ordinary 16BPP mode, then the RGB/BGR565 handling of the pixel
data is handled by configuring the PLD through the external
register.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20180206093540.8147-2-linus.walleij@linaro.org
This commit is contained in:
Linus Walleij 2018-02-06 10:35:37 +01:00
parent 3d95f76a11
commit 6470b7ddec
1 changed files with 13 additions and 2 deletions
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15
drivers/gpu/drm/pl111/pl111_display.c
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@ -199,10 +199,17 @@ static void pl111_display_enable(struct drm_simple_display_pipe *pipe,
cntl |= CNTL_LCDBPP24 | CNTL_BGR;
break;
case DRM_FORMAT_BGR565:
cntl |= CNTL_LCDBPP16_565;
if (priv->variant->is_pl110)
cntl |= CNTL_LCDBPP16;
else
cntl |= CNTL_LCDBPP16_565;
break;
case DRM_FORMAT_RGB565:
cntl |= CNTL_LCDBPP16_565 | CNTL_BGR;
if (priv->variant->is_pl110)
cntl |= CNTL_LCDBPP16;
else
cntl |= CNTL_LCDBPP16_565;
cntl |= CNTL_BGR;
break;
case DRM_FORMAT_ABGR1555:
case DRM_FORMAT_XBGR1555:
@ -226,6 +233,10 @@ static void pl111_display_enable(struct drm_simple_display_pipe *pipe,
break;
}
/* The PL110 in Integrator/Versatile does the BGR routing externally */
if (priv->variant->external_bgr)
cntl &= ~CNTL_BGR;
/* Power sequence: first enable and chill */
writel(cntl, priv->regs + priv->ctrl);