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Intel ID: PSIRT-TA-201910-001
CVEID: CVE-2019-14615 Summary of Vulnerability ------------------------ Insufficient control flow in certain data structures for some Intel(R) Processors with Intel Processor Graphics may allow an unauthenticated user to potentially enable information disclosure via local access Products affected: ------------------ Intel CPU’s with Gen7, Gen7.5 and Gen9 Graphics. Public Disclosure Schedule: --------------------------- Intel is pursuing a coordinated disclosure of this vulnerability. The targeted public disclosure date is January 14 2020 Mitigation Summary ------------------ This patch provides mitigation for Gen9 hardware only. Patches for Gen7 and Gen7.5 will be provided later. Note that Gen8 is not impacted due to a previously implemented workaround. The mitigation involves using an existing hardware feature to forcibly clear down all EU state at each context switch. -----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJeGHjXAAoJEID/Kx9323OZezwH/iLlbczb6HW7AbloQVa7KRNL cZ4VHHXmMEQPSprxFuOS21/hVW1rKZzbjTGGI0qbm4qNT3LiK92E0dcoMs1Tp9Xd eElZpkeO36pqdxc/a256N3xrpmhiMnmk33F36k4qGpt6YUxvFUyZ50re0e3pO03j wGJ1cMIbAKJQmMC23yQdD44y1TH32fGeUQvwbLgktHAS/r1DxqyaZZq1hSpOiZdV TqhFLQAXUw2Cxy3FmF7KgcedcZfii1Rq5Gz7iQeyix3CbNM9r+1UGqsjGacDcXS9 /GxhBCSKf35pOj7ZxgtLPCCdL5mSAtvQO/E+yLx3F9axG9bzzNGkLpEsWeCshp8= =3jTf -----END PGP SIGNATURE----- Merge tag 'Intel-CVE-2019-14615' from bundle by Akeem Abodunrin. Merge Intel Gen9 graphics fix from Akeem Abodunrin: "Insufficient control flow in certain data structures for some Intel Processors with Intel Processor Graphics may allow an unauthenticated user to potentially enable information disclosure via local access This provides mitigation for Gen9 hardware. Note that Gen8 is not impacted due to a previously implemented workaround. The mitigation involves using an existing hardware feature to forcibly clear down all EU state at each context switch" * tag 'Intel-CVE-2019-14615' of emailed bundle from Akeem G Abodunrin <akeem.g.abodunrin@intel.com>: drm/i915/gen9: Clear residual context state on context switch
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@ -2664,6 +2664,14 @@ static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
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/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
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batch = gen8_emit_flush_coherentl3_wa(engine, batch);
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/* WaClearSlmSpaceAtContextSwitch:skl,bxt,kbl,glk,cfl */
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batch = gen8_emit_pipe_control(batch,
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PIPE_CONTROL_FLUSH_L3 |
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PIPE_CONTROL_STORE_DATA_INDEX |
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PIPE_CONTROL_CS_STALL |
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PIPE_CONTROL_QW_WRITE,
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LRC_PPHWSP_SCRATCH_ADDR);
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batch = emit_lri(batch, lri, ARRAY_SIZE(lri));
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/* WaMediaPoolStateCmdInWABB:bxt,glk */
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