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ARM: SoC updates for 5.15

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There are three noteworthy updates for 32-bit arm platforms this time:
 
  - The Microchip SAMA7 family based on Cortex-A7 gets introduced, a new
    cousin to the older SAM9 (ARM9xx based) and SAMA5 (Cortex-A5 based)
    SoCs.
 
  - The ixp4xx platform (based on Intel XScale) is finally converted to
    device tree, and all the old board files are getting removed now.
 
  - The Cirrus Logic EP93xx platform loses support for the old
    MaverickCrunch FPU. Support for compiling user space applications
    was already removed in gcc-4.9, and the kernel support for old
    applications could not be built with clang ias. After confirming
    that there are no remaining users, removing this from the kernel
    seemed better than adding support for unused features to clang.
 
 There are minor updates to the aspeed, omap and samsung platforms
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'soc-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC updates from Arnd Bergmann:
 "There are three noteworthy updates for 32-bit arm platforms this time:

   - The Microchip SAMA7 family based on Cortex-A7 gets introduced, a
     new cousin to the older SAM9 (ARM9xx based) and SAMA5 (Cortex-A5
     based) SoCs.

   - The ixp4xx platform (based on Intel XScale) is finally converted to
     device tree, and all the old board files are getting removed now.

   - The Cirrus Logic EP93xx platform loses support for the old
     MaverickCrunch FPU. Support for compiling user space applications
     was already removed in gcc-4.9, and the kernel support for old
     applications could not be built with clang ias. After confirming
     that there are no remaining users, removing this from the kernel
     seemed better than adding support for unused features to clang.

  There are minor updates to the aspeed, omap and samsung platforms"

* tag 'soc-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (48 commits)
  soc: aspeed-lpc-ctrl: Fix clock cleanup in error path
  ARM: s3c: delete unneed local variable "delay"
  soc: aspeed: Re-enable FWH2AHB on AST2600
  soc: aspeed: socinfo: Add AST2625 variant
  soc: aspeed: p2a-ctrl: Fix boundary check for mmap
  soc: aspeed: lpc-ctrl: Fix boundary check for mmap
  ARM: ixp4xx: Delete the Freecom FSG-3 boardfiles
  ARM: ixp4xx: Delete GTWX5715 board files
  ARM: ixp4xx: Delete Coyote and IXDPG425 boardfiles
  ARM: ixp4xx: Delete Intel reference design boardfiles
  ARM: ixp4xx: Delete Avila boardfiles
  ARM: ixp4xx: Delete the Arcom Vulcan boardfiles
  ARM: ixp4xx: Delete Gateway WG302v2 boardfiles
  ARM: ixp4xx: Delete Omicron boardfiles
  ARM: ixp4xx: Delete the D-Link DSM-G600 boardfiles
  ARM: ixp4xx: Delete NAS100D boardfiles
  ARM: ixp4xx: Delete NSLU2 boardfiles
  arm: omap2: Drop the unused OMAP_PACKAGE_* KConfig entries
  arm: omap2: Drop obsolete MACH_OMAP3_PANDORA entry
  ARM: ep93xx: remove MaverickCrunch support
  ...
This commit is contained in:
Linus Torvalds 2021-09-01 15:19:43 -07:00
commit 634135a07b
68 changed files with 1133 additions and 4773 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
MAINTAINERS
View File

@ -16545,6 +16545,12 @@ F: drivers/phy/samsung/phy-s5pv210-usb2.c
F: drivers/phy/samsung/phy-samsung-usb2.c
F: drivers/phy/samsung/phy-samsung-usb2.h
SANCLOUD BEAGLEBONE ENHANCED DEVICE TREE
M: Paul Barker <paul.barker@sancloud.com>
R: Marc Murphy <marc.murphy@sancloud.com>
S: Supported
F: arch/arm/boot/dts/am335x-sancloud*
SC1200 WDT DRIVER
M: Zwane Mwaikambo <zwanem@gmail.com>
S: Maintained

10
arch/arm/Kconfig.debug
View File

@ -193,6 +193,14 @@ choice
their output to the USART1 port on SAMV7 based
machines.
config DEBUG_AT91_SAMA7G5_FLEXCOM3
bool "Kernel low-level debugging on SAMA7G5 FLEXCOM3"
select DEBUG_AT91_UART
depends on SOC_SAMA7G5
help
Say Y here if you want kernel low-level debugging support
on the FLEXCOM3 port of SAMA7G5.
config DEBUG_BCM2835
bool "Kernel low-level debugging on BCM2835 PL011 UART"
depends on ARCH_BCM2835 && ARCH_MULTI_V6
@ -1668,6 +1676,7 @@ config DEBUG_UART_PHYS
default 0xd4017000 if DEBUG_MMP_UART2
default 0xd4018000 if DEBUG_MMP_UART3
default 0xe0000000 if DEBUG_SPEAR13XX
default 0xe1824200 if DEBUG_AT91_SAMA7G5_FLEXCOM3
default 0xe4007000 if DEBUG_HIP04_UART
default 0xe6c40000 if DEBUG_RMOBILE_SCIFA0
default 0xe6c50000 if DEBUG_RMOBILE_SCIFA1
@ -1729,6 +1738,7 @@ config DEBUG_UART_VIRT
default 0xc8821000 if DEBUG_RV1108_UART1
default 0xc8912000 if DEBUG_RV1108_UART0
default 0xe0010fe0 if ARCH_RPC
default 0xe0824200 if DEBUG_AT91_SAMA7G5_FLEXCOM3
default 0xf0010000 if DEBUG_ASM9260_UART
default 0xf0100000 if DEBUG_DIGICOLOR_UA0
default 0xf01fb000 if DEBUG_NOMADIK_UART

1
arch/arm/configs/ep93xx_defconfig
View File

@ -12,7 +12,6 @@ CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_ARCH_EP93XX=y
CONFIG_CRUNCH=y
CONFIG_MACH_ADSSPHERE=y
CONFIG_MACH_EDB9301=y
CONFIG_MACH_EDB9302=y

8
arch/arm/include/asm/fpstate.h
View File

@ -77,14 +77,6 @@ union fp_state {
#define FP_SIZE (sizeof(union fp_state) / sizeof(int))
struct crunch_state {
unsigned int mvdx[16][2];
unsigned int mvax[4][3];
unsigned int dspsc[2];
};
#define CRUNCH_SIZE sizeof(struct crunch_state)
#endif
#endif

8
arch/arm/include/asm/thread_info.h
View File

@ -65,9 +65,6 @@ struct thread_info {
__u32 syscall; /* syscall number */
__u8 used_cp[16]; /* thread used copro */
unsigned long tp_value[2]; /* TLS registers */
#ifdef CONFIG_CRUNCH
struct crunch_state crunchstate;
#endif
union fp_state fpstate __attribute__((aligned(8)));
union vfp_state vfpstate;
#ifdef CONFIG_ARM_THUMBEE
@ -107,11 +104,6 @@ static inline struct thread_info *current_thread_info(void)
((unsigned long)(task_thread_info(tsk)->cpu_context.r7))
#endif
extern void crunch_task_disable(struct thread_info *);
extern void crunch_task_copy(struct thread_info *, void *);
extern void crunch_task_restore(struct thread_info *, void *);
extern void crunch_task_release(struct thread_info *);
extern void iwmmxt_task_disable(struct thread_info *);
extern void iwmmxt_task_copy(struct thread_info *, void *);
extern void iwmmxt_task_restore(struct thread_info *, void *);

14
arch/arm/include/asm/ucontext.h
View File

@ -43,17 +43,6 @@ struct ucontext {
*/
#define DUMMY_MAGIC 0xb0d9ed01
#ifdef CONFIG_CRUNCH
#define CRUNCH_MAGIC 0x5065cf03
#define CRUNCH_STORAGE_SIZE (CRUNCH_SIZE + 8)
struct crunch_sigframe {
unsigned long magic;
unsigned long size;
struct crunch_state storage;
} __attribute__((__aligned__(8)));
#endif
#ifdef CONFIG_IWMMXT
/* iwmmxt_area is 0x98 bytes long, preceded by 8 bytes of signature */
#define IWMMXT_MAGIC 0x12ef842a
@ -92,9 +81,6 @@ struct vfp_sigframe
* one of these.
*/
struct aux_sigframe {
#ifdef CONFIG_CRUNCH
struct crunch_sigframe crunch;
#endif
#ifdef CONFIG_IWMMXT
struct iwmmxt_sigframe iwmmxt;
#endif

2
arch/arm/include/uapi/asm/hwcap.h
View File

@ -15,7 +15,7 @@
#define HWCAP_EDSP (1 << 7)
#define HWCAP_JAVA (1 << 8)
#define HWCAP_IWMMXT (1 << 9)
#define HWCAP_CRUNCH (1 << 10)
#define HWCAP_CRUNCH (1 << 10) /* Obsolete */
#define HWCAP_THUMBEE (1 << 11)
#define HWCAP_NEON (1 << 12)
#define HWCAP_VFPv3 (1 << 13)

4
arch/arm/include/uapi/asm/ptrace.h
View File

@ -26,8 +26,8 @@
#define PTRACE_GET_THREAD_AREA 22
#define PTRACE_SET_SYSCALL 23
/* PTRACE_SYSCALL is 24 */
#define PTRACE_GETCRUNCHREGS 25
#define PTRACE_SETCRUNCHREGS 26
#define PTRACE_GETCRUNCHREGS 25 /* obsolete */
#define PTRACE_SETCRUNCHREGS 26 /* obsolete */
#define PTRACE_GETVFPREGS 27
#define PTRACE_SETVFPREGS 28
#define PTRACE_GETHBPREGS 29

3
arch/arm/kernel/asm-offsets.c
View File

@ -63,9 +63,6 @@ int main(void)
#ifdef CONFIG_IWMMXT
DEFINE(TI_IWMMXT_STATE, offsetof(struct thread_info, fpstate.iwmmxt));
#endif
#ifdef CONFIG_CRUNCH
DEFINE(TI_CRUNCH_STATE, offsetof(struct thread_info, crunchstate));
#endif
#ifdef CONFIG_STACKPROTECTOR_PER_TASK
DEFINE(TI_STACK_CANARY, offsetof(struct thread_info, stack_canary));
#endif

6
arch/arm/kernel/entry-armv.S
View File

@ -618,15 +618,9 @@ call_fpe:
W(b) do_fpe @ CP#1 (FPE)
W(b) do_fpe @ CP#2 (FPE)
ret.w lr @ CP#3
#ifdef CONFIG_CRUNCH
b crunch_task_enable @ CP#4 (MaverickCrunch)
b crunch_task_enable @ CP#5 (MaverickCrunch)
b crunch_task_enable @ CP#6 (MaverickCrunch)
#else
ret.w lr @ CP#4
ret.w lr @ CP#5
ret.w lr @ CP#6
#endif
ret.w lr @ CP#7
ret.w lr @ CP#8
ret.w lr @ CP#9

36
arch/arm/kernel/ptrace.c
View File

@ -318,32 +318,6 @@ static int ptrace_setwmmxregs(struct task_struct *tsk, void __user *ufp)
#endif
#ifdef CONFIG_CRUNCH
/*
* Get the child Crunch state.
*/
static int ptrace_getcrunchregs(struct task_struct *tsk, void __user *ufp)
{
struct thread_info *thread = task_thread_info(tsk);
crunch_task_disable(thread); /* force it to ram */
return copy_to_user(ufp, &thread->crunchstate, CRUNCH_SIZE)
? -EFAULT : 0;
}
/*
* Set the child Crunch state.
*/
static int ptrace_setcrunchregs(struct task_struct *tsk, void __user *ufp)
{
struct thread_info *thread = task_thread_info(tsk);
crunch_task_release(thread); /* force a reload */
return copy_from_user(&thread->crunchstate, ufp, CRUNCH_SIZE)
? -EFAULT : 0;
}
#endif
#ifdef CONFIG_HAVE_HW_BREAKPOINT
/*
* Convert a virtual register number into an index for a thread_info
@ -815,16 +789,6 @@ long arch_ptrace(struct task_struct *child, long request,
ret = 0;
break;
#ifdef CONFIG_CRUNCH
case PTRACE_GETCRUNCHREGS:
ret = ptrace_getcrunchregs(child, datap);
break;
case PTRACE_SETCRUNCHREGS:
ret = ptrace_setcrunchregs(child, datap);
break;
#endif
#ifdef CONFIG_VFP
case PTRACE_GETVFPREGS:
ret = copy_regset_to_user(child,

42
arch/arm/kernel/signal.c
View File

@ -25,40 +25,6 @@ extern const unsigned long sigreturn_codes[17];
static unsigned long signal_return_offset;
#ifdef CONFIG_CRUNCH
static int preserve_crunch_context(struct crunch_sigframe __user *frame)
{
char kbuf[sizeof(*frame) + 8];
struct crunch_sigframe *kframe;
/* the crunch context must be 64 bit aligned */
kframe = (struct crunch_sigframe *)((unsigned long)(kbuf + 8) & ~7);
kframe->magic = CRUNCH_MAGIC;
kframe->size = CRUNCH_STORAGE_SIZE;
crunch_task_copy(current_thread_info(), &kframe->storage);
return __copy_to_user(frame, kframe, sizeof(*frame));
}
static int restore_crunch_context(char __user **auxp)
{
struct crunch_sigframe __user *frame =
(struct crunch_sigframe __user *)*auxp;
char kbuf[sizeof(*frame) + 8];
struct crunch_sigframe *kframe;
/* the crunch context must be 64 bit aligned */
kframe = (struct crunch_sigframe *)((unsigned long)(kbuf + 8) & ~7);
if (__copy_from_user(kframe, frame, sizeof(*frame)))
return -1;
if (kframe->magic != CRUNCH_MAGIC ||
kframe->size != CRUNCH_STORAGE_SIZE)
return -1;
*auxp += CRUNCH_STORAGE_SIZE;
crunch_task_restore(current_thread_info(), &kframe->storage);
return 0;
}
#endif
#ifdef CONFIG_IWMMXT
static int preserve_iwmmxt_context(struct iwmmxt_sigframe __user *frame)
@ -205,10 +171,6 @@ static int restore_sigframe(struct pt_regs *regs, struct sigframe __user *sf)
err |= !valid_user_regs(regs);
aux = (char __user *) sf->uc.uc_regspace;
#ifdef CONFIG_CRUNCH
if (err == 0)
err |= restore_crunch_context(&aux);
#endif
#ifdef CONFIG_IWMMXT
if (err == 0)
err |= restore_iwmmxt_context(&aux);
@ -321,10 +283,6 @@ setup_sigframe(struct sigframe __user *sf, struct pt_regs *regs, sigset_t *set)
err |= __copy_to_user(&sf->uc.uc_sigmask, set, sizeof(*set));
aux = (struct aux_sigframe __user *) sf->uc.uc_regspace;
#ifdef CONFIG_CRUNCH
if (err == 0)
err |= preserve_crunch_context(&aux->crunch);
#endif
#ifdef CONFIG_IWMMXT
if (err == 0)
err |= preserve_iwmmxt_context(&aux->iwmmxt);

18
arch/arm/mach-at91/Kconfig
View File

@ -57,6 +57,16 @@ config SOC_SAMA5D4
help
Select this if you are using one of Microchip's SAMA5D4 family SoC.
config SOC_SAMA7G5
bool "SAMA7G5 family"
depends on ARCH_MULTI_V7
select HAVE_AT91_GENERATED_CLK
select HAVE_AT91_SAM9X60_PLL
select HAVE_AT91_UTMI
select SOC_SAMA7
help
Select this if you are using one of Microchip's SAMA7G5 family SoC.
config SOC_AT91RM9200
bool "AT91RM9200"
depends on ARCH_MULTI_V4T
@ -191,4 +201,12 @@ config SOC_SAMA5
config ATMEL_PM
bool
config SOC_SAMA7
bool
select ARM_GIC
select ATMEL_PM if PM
select ATMEL_SDRAMC
select MEMORY
select SOC_SAM_V7
select SRAM if PM
endif

1
arch/arm/mach-at91/Makefile
View File

@ -8,6 +8,7 @@ obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o
obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o
obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o
obj-$(CONFIG_SOC_SAMA5) += sama5.o
obj-$(CONFIG_SOC_SAMA7) += sama7.o
obj-$(CONFIG_SOC_SAMV7) += samv7.o
# Power Management

2
arch/arm/mach-at91/generic.h
View File

@ -14,12 +14,14 @@ extern void __init at91sam9_pm_init(void);
extern void __init sam9x60_pm_init(void);
extern void __init sama5_pm_init(void);
extern void __init sama5d2_pm_init(void);
extern void __init sama7_pm_init(void);
#else
static inline void __init at91rm9200_pm_init(void) { }
static inline void __init at91sam9_pm_init(void) { }
static inline void __init sam9x60_pm_init(void) { }
static inline void __init sama5_pm_init(void) { }
static inline void __init sama5d2_pm_init(void) { }
static inline void __init sama7_pm_init(void) { }
#endif
#endif /* _AT91_GENERIC_H */

347
arch/arm/mach-at91/pm.c
View File

@ -10,6 +10,7 @@
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
#include <linux/of_platform.h>
#include <linux/parser.h>
#include <linux/suspend.h>
@ -27,13 +28,55 @@
#include "generic.h"
#include "pm.h"
#define BACKUP_DDR_PHY_CALIBRATION (9)
/**
* struct at91_pm_bu - AT91 power management backup unit data structure
* @suspended: true if suspended to backup mode
* @reserved: reserved
* @canary: canary data for memory checking after exit from backup mode
* @resume: resume API
* @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words
* of the memory
*/
struct at91_pm_bu {
int suspended;
unsigned long reserved;
phys_addr_t canary;
phys_addr_t resume;
unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION];
};
/**
* struct at91_soc_pm - AT91 SoC power management data structure
* @config_shdwc_ws: wakeup sources configuration function for SHDWC
* @config_pmc_ws: wakeup srouces configuration function for PMC
* @ws_ids: wakup sources of_device_id array
* @data: PM data to be used on last phase of suspend
* @bu: backup unit mapped data (for backup mode)
* @memcs: memory chip select
*/
struct at91_soc_pm {
int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
const struct of_device_id *ws_ids;
struct at91_pm_bu *bu;
struct at91_pm_data data;
void *memcs;
};
/**
* enum at91_pm_iomaps: IOs that needs to be mapped for different PM modes
* @AT91_PM_IOMAP_SHDWC: SHDWC controller
* @AT91_PM_IOMAP_SFRBU: SFRBU controller
*/
enum at91_pm_iomaps {
AT91_PM_IOMAP_SHDWC,
AT91_PM_IOMAP_SFRBU,
};
#define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name)
static struct at91_soc_pm soc_pm = {
.data = {
.standby_mode = AT91_PM_STANDBY,
@ -71,13 +114,6 @@ static int at91_pm_valid_state(suspend_state_t state)
static int canary = 0xA5A5A5A5;
static struct at91_pm_bu {
int suspended;
unsigned long reserved;
phys_addr_t canary;
phys_addr_t resume;
} *pm_bu;
struct wakeup_source_info {
unsigned int pmc_fsmr_bit;
unsigned int shdwc_mr_bit;
@ -116,6 +152,17 @@ static const struct of_device_id sam9x60_ws_ids[] = {
{ /* sentinel */ }
};
static const struct of_device_id sama7g5_ws_ids[] = {
{ .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] },
{ .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] },
{ .compatible = "usb-ohci", .data = &ws_info[2] },
{ .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
{ .compatible = "usb-ehci", .data = &ws_info[2] },
{ .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] },
{ .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] },
{ /* sentinel */ }
};
static int at91_pm_config_ws(unsigned int pm_mode, bool set)
{
const struct wakeup_source_info *wsi;
@ -206,6 +253,8 @@ static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
*/
static int at91_pm_begin(suspend_state_t state)
{
int ret;
switch (state) {
case PM_SUSPEND_MEM:
soc_pm.data.mode = soc_pm.data.suspend_mode;
@ -219,7 +268,16 @@ static int at91_pm_begin(suspend_state_t state)
soc_pm.data.mode = -1;
}
return at91_pm_config_ws(soc_pm.data.mode, true);
ret = at91_pm_config_ws(soc_pm.data.mode, true);
if (ret)
return ret;
if (soc_pm.data.mode == AT91_PM_BACKUP)
soc_pm.bu->suspended = 1;
else if (soc_pm.bu)
soc_pm.bu->suspended = 0;
return 0;
}
/*
@ -277,6 +335,19 @@ extern u32 at91_pm_suspend_in_sram_sz;
static int at91_suspend_finish(unsigned long val)
{
int i;
if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) {
/*
* The 1st 8 words of memory might get corrupted in the process
* of DDR PHY recalibration; it is saved here in securam and it
* will be restored later, after recalibration, by bootloader
*/
for (i = 1; i < BACKUP_DDR_PHY_CALIBRATION; i++)
soc_pm.bu->ddr_phy_calibration[i] =
*((unsigned int *)soc_pm.memcs + (i - 1));
}
flush_cache_all();
outer_disable();
@ -288,8 +359,6 @@ static int at91_suspend_finish(unsigned long val)
static void at91_pm_suspend(suspend_state_t state)
{
if (soc_pm.data.mode == AT91_PM_BACKUP) {
pm_bu->suspended = 1;
cpu_suspend(0, at91_suspend_finish);
/* The SRAM is lost between suspend cycles */
@ -511,10 +580,16 @@ static const struct of_device_id ramc_ids[] __initconst = {
{ .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
{ .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
{ .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
{ .compatible = "microchip,sama7g5-uddrc", },
{ /*sentinel*/ }
};
static __init void at91_dt_ramc(void)
static const struct of_device_id ramc_phy_ids[] __initconst = {
{ .compatible = "microchip,sama7g5-ddr3phy", },
{ /* Sentinel. */ },
};
static __init void at91_dt_ramc(bool phy_mandatory)
{
struct device_node *np;
const struct of_device_id *of_id;
@ -528,9 +603,11 @@ static __init void at91_dt_ramc(void)
panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
ramc = of_id->data;
if (!standby)
standby = ramc->idle;
soc_pm.data.memctrl = ramc->memctrl;
if (ramc) {
if (!standby)
standby = ramc->idle;
soc_pm.data.memctrl = ramc->memctrl;
}
idx++;
}
@ -538,6 +615,16 @@ static __init void at91_dt_ramc(void)
if (!idx)
panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
/* Lookup for DDR PHY node, if any. */
for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) {
soc_pm.data.ramc_phy = of_iomap(np, 0);
if (!soc_pm.data.ramc_phy)
panic(pr_fmt("unable to map ramc phy cpu registers\n"));
}
if (phy_mandatory && !soc_pm.data.ramc_phy)
panic(pr_fmt("DDR PHY is mandatory!\n"));
if (!standby) {
pr_warn("ramc no standby function available\n");
return;
@ -618,37 +705,57 @@ static bool __init at91_is_pm_mode_active(int pm_mode)
soc_pm.data.suspend_mode == pm_mode);
}
static int __init at91_pm_backup_scan_memcs(unsigned long node,
const char *uname, int depth,
void *data)
{
const char *type;
const __be32 *reg;
int *located = data;
int size;
/* Memory node already located. */
if (*located)
return 0;
type = of_get_flat_dt_prop(node, "device_type", NULL);
/* We are scanning "memory" nodes only. */
if (!type || strcmp(type, "memory"))
return 0;
reg = of_get_flat_dt_prop(node, "reg", &size);
if (reg) {
soc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg));
*located = 1;
}
return 0;
}
static int __init at91_pm_backup_init(void)
{
struct gen_pool *sram_pool;
struct device_node *np;
struct platform_device *pdev = NULL;
int ret = -ENODEV;
struct platform_device *pdev;
int ret = -ENODEV, located = 0;
if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) &&
!IS_ENABLED(CONFIG_SOC_SAMA7G5))
return -EPERM;
if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
return 0;
np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
if (!np) {
pr_warn("%s: failed to find sfrbu!\n", __func__);
return ret;
}
soc_pm.data.sfrbu = of_iomap(np, 0);
of_node_put(np);
np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
if (!np)
goto securam_fail_no_ref_dev;
return ret;
pdev = of_find_device_by_node(np);
of_node_put(np);
if (!pdev) {
pr_warn("%s: failed to find securam device!\n", __func__);
goto securam_fail_no_ref_dev;
return ret;
}
sram_pool = gen_pool_get(&pdev->dev, NULL);
@ -657,79 +764,117 @@ static int __init at91_pm_backup_init(void)
goto securam_fail;
}
pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
if (!pm_bu) {
soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
if (!soc_pm.bu) {
pr_warn("%s: unable to alloc securam!\n", __func__);
ret = -ENOMEM;
goto securam_fail;
}
pm_bu->suspended = 0;
pm_bu->canary = __pa_symbol(&canary);
pm_bu->resume = __pa_symbol(cpu_resume);
soc_pm.bu->suspended = 0;
soc_pm.bu->canary = __pa_symbol(&canary);
soc_pm.bu->resume = __pa_symbol(cpu_resume);
if (soc_pm.data.ramc_phy) {
of_scan_flat_dt(at91_pm_backup_scan_memcs, &located);
if (!located)
goto securam_fail;
/* DDR3PHY_ZQ0SR0 */
soc_pm.bu->ddr_phy_calibration[0] = readl(soc_pm.data.ramc_phy +
0x188);
}
return 0;
securam_fail:
put_device(&pdev->dev);
securam_fail_no_ref_dev:
iounmap(soc_pm.data.sfrbu);
soc_pm.data.sfrbu = NULL;
return ret;
}
static void __init at91_pm_use_default_mode(int pm_mode)
{
if (pm_mode != AT91_PM_ULP1 && pm_mode != AT91_PM_BACKUP)
return;
if (soc_pm.data.standby_mode == pm_mode)
soc_pm.data.standby_mode = AT91_PM_ULP0;
if (soc_pm.data.suspend_mode == pm_mode)
soc_pm.data.suspend_mode = AT91_PM_ULP0;
}
static const struct of_device_id atmel_shdwc_ids[] = {
{ .compatible = "atmel,sama5d2-shdwc" },
{ .compatible = "microchip,sam9x60-shdwc" },
{ .compatible = "microchip,sama7g5-shdwc" },
{ /* sentinel. */ }
};
static void __init at91_pm_modes_init(void)
static void __init at91_pm_modes_init(const u32 *maps, int len)
{
struct device_node *np;
int ret;
if (!at91_is_pm_mode_active(AT91_PM_BACKUP) &&
!at91_is_pm_mode_active(AT91_PM_ULP1))
return;
np = of_find_matching_node(NULL, atmel_shdwc_ids);
if (!np) {
pr_warn("%s: failed to find shdwc!\n", __func__);
goto ulp1_default;
}
soc_pm.data.shdwc = of_iomap(np, 0);
of_node_put(np);
int ret, mode;
ret = at91_pm_backup_init();
if (ret) {
if (!at91_is_pm_mode_active(AT91_PM_ULP1))
goto unmap;
else
goto backup_default;
if (soc_pm.data.standby_mode == AT91_PM_BACKUP)
soc_pm.data.standby_mode = AT91_PM_ULP0;
if (soc_pm.data.suspend_mode == AT91_PM_BACKUP)
soc_pm.data.suspend_mode = AT91_PM_ULP0;
}
if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) {
np = of_find_matching_node(NULL, atmel_shdwc_ids);
if (!np) {
pr_warn("%s: failed to find shdwc!\n", __func__);
/* Use ULP0 if it doesn't needs SHDWC.*/
if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)))
mode = AT91_PM_ULP0;
else
mode = AT91_PM_STANDBY;
if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC))
soc_pm.data.standby_mode = mode;
if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))
soc_pm.data.suspend_mode = mode;
} else {
soc_pm.data.shdwc = of_iomap(np, 0);
of_node_put(np);
}
}
if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) {
np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
if (!np) {
pr_warn("%s: failed to find sfrbu!\n", __func__);
/*
* Use ULP0 if it doesn't need SHDWC or if SHDWC
* was already located.
*/
if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)) ||
soc_pm.data.shdwc)
mode = AT91_PM_ULP0;
else
mode = AT91_PM_STANDBY;
if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU))
soc_pm.data.standby_mode = mode;
if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))
soc_pm.data.suspend_mode = mode;
} else {
soc_pm.data.sfrbu = of_iomap(np, 0);
of_node_put(np);
}
}
/* Unmap all unnecessary. */
if (soc_pm.data.shdwc &&
!(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) {
iounmap(soc_pm.data.shdwc);
soc_pm.data.shdwc = NULL;
}
if (soc_pm.data.sfrbu &&
!(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) {
iounmap(soc_pm.data.sfrbu);
soc_pm.data.sfrbu = NULL;
}
return;
unmap:
iounmap(soc_pm.data.shdwc);
soc_pm.data.shdwc = NULL;
ulp1_default:
at91_pm_use_default_mode(AT91_PM_ULP1);
backup_default:
at91_pm_use_default_mode(AT91_PM_BACKUP);
}
struct pmc_info {
@ -764,6 +909,11 @@ static const struct pmc_info pmc_infos[] __initconst = {
.mckr = 0x28,
.version = AT91_PMC_V2,
},
{
.mckr = 0x28,
.version = AT91_PMC_V2,
},
};
static const struct of_device_id atmel_pmc_ids[] __initconst = {
@ -779,6 +929,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
{ .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
{ .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
{ .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
{ .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
{ /* sentinel */ },
};
@ -877,7 +1028,7 @@ void __init at91rm9200_pm_init(void)
soc_pm.data.standby_mode = AT91_PM_STANDBY;
soc_pm.data.suspend_mode = AT91_PM_ULP0;
at91_dt_ramc();
at91_dt_ramc(false);
/*
* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
@ -892,13 +1043,16 @@ void __init sam9x60_pm_init(void)
static const int modes[] __initconst = {
AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
};
static const int iomaps[] __initconst = {
[AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC),
};
if (!IS_ENABLED(CONFIG_SOC_SAM9X60))
return;
at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
at91_pm_modes_init();
at91_dt_ramc();
at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
at91_dt_ramc(false);
at91_pm_init(NULL);
soc_pm.ws_ids = sam9x60_ws_ids;
@ -918,7 +1072,7 @@ void __init at91sam9_pm_init(void)
soc_pm.data.standby_mode = AT91_PM_STANDBY;
soc_pm.data.suspend_mode = AT91_PM_ULP0;
at91_dt_ramc();
at91_dt_ramc(false);
at91_pm_init(at91sam9_idle);
}
@ -932,7 +1086,7 @@ void __init sama5_pm_init(void)
return;
at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
at91_dt_ramc();
at91_dt_ramc(false);
at91_pm_init(NULL);
}
@ -942,13 +1096,18 @@ void __init sama5d2_pm_init(void)
AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
AT91_PM_BACKUP,
};
static const u32 iomaps[] __initconst = {
[AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC),
[AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) |
AT91_PM_IOMAP(SFRBU),
};
if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
return;
at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
at91_pm_modes_init();
at91_dt_ramc();
at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
at91_dt_ramc(false);
at91_pm_init(NULL);
soc_pm.ws_ids = sama5d2_ws_ids;
@ -956,6 +1115,32 @@ void __init sama5d2_pm_init(void)
soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
}
void __init sama7_pm_init(void)
{
static const int modes[] __initconst = {
AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP,
};
static const u32 iomaps[] __initconst = {
[AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU),
[AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) |
AT91_PM_IOMAP(SHDWC),
[AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) |
AT91_PM_IOMAP(SHDWC),
};
if (!IS_ENABLED(CONFIG_SOC_SAMA7))
return;
at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
at91_dt_ramc(true);
at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
at91_pm_init(NULL);
soc_pm.ws_ids = sama7g5_ws_ids;
soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
}
static int __init at91_pm_modes_select(char *str)
{
char *s;

3
arch/arm/mach-at91/pm.h
View File

@ -12,6 +12,8 @@
#include <linux/mfd/syscon/atmel-mc.h>
#include <soc/at91/at91sam9_ddrsdr.h>
#include <soc/at91/at91sam9_sdramc.h>
#include <soc/at91/sama7-ddr.h>
#include <soc/at91/sama7-sfrbu.h>
#define AT91_MEMCTRL_MC 0
#define AT91_MEMCTRL_SDRAMC 1
@ -27,6 +29,7 @@
struct at91_pm_data {
void __iomem *pmc;
void __iomem *ramc[2];
void __iomem *ramc_phy;
unsigned long uhp_udp_mask;
unsigned int memctrl;
unsigned int mode;

2
arch/arm/mach-at91/pm_data-offsets.c
View File

@ -8,6 +8,8 @@ int main(void)
DEFINE(PM_DATA_PMC, offsetof(struct at91_pm_data, pmc));
DEFINE(PM_DATA_RAMC0, offsetof(struct at91_pm_data, ramc[0]));
DEFINE(PM_DATA_RAMC1, offsetof(struct at91_pm_data, ramc[1]));
DEFINE(PM_DATA_RAMC_PHY, offsetof(struct at91_pm_data,
ramc_phy));
DEFINE(PM_DATA_MEMCTRL, offsetof(struct at91_pm_data, memctrl));
DEFINE(PM_DATA_MODE, offsetof(struct at91_pm_data, mode));
DEFINE(PM_DATA_SHDWC, offsetof(struct at91_pm_data, shdwc));

831
arch/arm/mach-at91/pm_suspend.S
View File

@ -22,39 +22,57 @@ tmp3 .req r6
/*
* Wait until master clock is ready (after switching master clock source)
*
* @r_mckid: register holding master clock identifier
*
* Side effects: overwrites r7, r8
*/
.macro wait_mckrdy
1: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_MCKRDY
beq 1b
.macro wait_mckrdy r_mckid
#ifdef CONFIG_SOC_SAMA7
cmp \r_mckid, #0
beq 1f
mov r7, #AT91_PMC_MCKXRDY
b 2f
#endif
1: mov r7, #AT91_PMC_MCKRDY
2: ldr r8, [pmc, #AT91_PMC_SR]
and r8, r7
cmp r8, r7
bne 2b
.endm
/*
* Wait until master oscillator has stabilized.
*
* Side effects: overwrites r7
*/
.macro wait_moscrdy
1: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_MOSCS
1: ldr r7, [pmc, #AT91_PMC_SR]
tst r7, #AT91_PMC_MOSCS
beq 1b
.endm
/*
* Wait for main oscillator selection is done
*
* Side effects: overwrites r7
*/
.macro wait_moscsels
1: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_MOSCSELS
1: ldr r7, [pmc, #AT91_PMC_SR]
tst r7, #AT91_PMC_MOSCSELS
beq 1b
.endm
/*
* Put the processor to enter the idle state
*
* Side effects: overwrites r7
*/
.macro at91_cpu_idle
#if defined(CONFIG_CPU_V7)
mov tmp1, #AT91_PMC_PCK
str tmp1, [pmc, #AT91_PMC_SCDR]
mov r7, #AT91_PMC_PCK
str r7, [pmc, #AT91_PMC_SCDR]
dsb
@ -65,102 +83,375 @@ tmp3 .req r6
.endm
/**
* Set state for 2.5V low power regulator
* @ena: 0 - disable regulator
* 1 - enable regulator
*
* Side effects: overwrites r7, r8, r9, r10
*/
.macro at91_2_5V_reg_set_low_power ena
#ifdef CONFIG_SOC_SAMA7
ldr r7, .sfrbu
mov r8, #\ena
ldr r9, [r7, #AT91_SFRBU_25LDOCR]
orr r9, r9, #AT91_SFRBU_25LDOCR_LP
cmp r8, #1
beq lp_done_\ena
bic r9, r9, #AT91_SFRBU_25LDOCR_LP
lp_done_\ena:
ldr r10, =AT91_SFRBU_25LDOCR_LDOANAKEY
orr r9, r9, r10
str r9, [r7, #AT91_SFRBU_25LDOCR]
#endif
.endm
.macro at91_backup_set_lpm reg
#ifdef CONFIG_SOC_SAMA7
orr \reg, \reg, #0x200000
#endif
.endm
.text
.arm
/*
* void at91_suspend_sram_fn(struct at91_pm_data*)
* @input param:
* @r0: base address of struct at91_pm_data
#ifdef CONFIG_SOC_SAMA7
/**
* Enable self-refresh
*
* Side effects: overwrites r2, r3, tmp1, tmp2, tmp3, r7
*/
/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */
.align 3
ENTRY(at91_pm_suspend_in_sram)
/* Save registers on stack */
stmfd sp!, {r4 - r12, lr}
.macro at91_sramc_self_refresh_ena
ldr r2, .sramc_base
ldr r3, .sramc_phy_base
ldr r7, .pm_mode
/* Drain write buffer */
dsb
/* Disable all AXI ports. */
ldr tmp1, [r2, #UDDRC_PCTRL_0]
bic tmp1, tmp1, #0x1
str tmp1, [r2, #UDDRC_PCTRL_0]
ldr tmp1, [r2, #UDDRC_PCTRL_1]
bic tmp1, tmp1, #0x1
str tmp1, [r2, #UDDRC_PCTRL_1]
ldr tmp1, [r2, #UDDRC_PCTRL_2]
bic tmp1, tmp1, #0x1
str tmp1, [r2, #UDDRC_PCTRL_2]
ldr tmp1, [r2, #UDDRC_PCTRL_3]
bic tmp1, tmp1, #0x1
str tmp1, [r2, #UDDRC_PCTRL_3]
ldr tmp1, [r2, #UDDRC_PCTRL_4]
bic tmp1, tmp1, #0x1
str tmp1, [r2, #UDDRC_PCTRL_4]
sr_ena_1:
/* Wait for all ports to disable. */
ldr tmp1, [r2, #UDDRC_PSTAT]
ldr tmp2, =UDDRC_PSTAT_ALL_PORTS
tst tmp1, tmp2
bne sr_ena_1
/* Switch to self-refresh. */
ldr tmp1, [r2, #UDDRC_PWRCTL]
orr tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW
str tmp1, [r2, #UDDRC_PWRCTL]
sr_ena_2:
/* Wait for self-refresh enter. */
ldr tmp1, [r2, #UDDRC_STAT]
bic tmp1, tmp1, #~UDDRC_STAT_SELFREF_TYPE_MSK
cmp tmp1, #UDDRC_STAT_SELFREF_TYPE_SW
bne sr_ena_2
/* Put DDR PHY's DLL in bypass mode for non-backup modes. */
cmp r7, #AT91_PM_BACKUP
beq sr_ena_3
ldr tmp1, [r3, #DDR3PHY_PIR]
orr tmp1, tmp1, #DDR3PHY_PIR_DLLBYP
str tmp1, [r3, #DDR3PHY_PIR]
sr_ena_3:
/* Power down DDR PHY data receivers. */
ldr tmp1, [r3, #DDR3PHY_DXCCR]
orr tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR
str tmp1, [r3, #DDR3PHY_DXCCR]
/* Power down ADDR/CMD IO. */
ldr tmp1, [r3, #DDR3PHY_ACIOCR]
orr tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD
orr tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0
orr tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0
str tmp1, [r3, #DDR3PHY_ACIOCR]
/* Power down ODT. */
ldr tmp1, [r3, #DDR3PHY_DSGCR]
orr tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0
str tmp1, [r3, #DDR3PHY_DSGCR]
.endm
/**
* Disable self-refresh
*
* Side effects: overwrites r2, r3, tmp1, tmp2, tmp3
*/
.macro at91_sramc_self_refresh_dis
ldr r2, .sramc_base
ldr r3, .sramc_phy_base
/* Power up DDR PHY data receivers. */
ldr tmp1, [r3, #DDR3PHY_DXCCR]
bic tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR
str tmp1, [r3, #DDR3PHY_DXCCR]
/* Power up the output of CK and CS pins. */
ldr tmp1, [r3, #DDR3PHY_ACIOCR]
bic tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD
bic tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0
bic tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0
str tmp1, [r3, #DDR3PHY_ACIOCR]
/* Power up ODT. */
ldr tmp1, [r3, #DDR3PHY_DSGCR]
bic tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0
str tmp1, [r3, #DDR3PHY_DSGCR]
/* Take DDR PHY's DLL out of bypass mode. */
ldr tmp1, [r3, #DDR3PHY_PIR]
bic tmp1, tmp1, #DDR3PHY_PIR_DLLBYP
str tmp1, [r3, #DDR3PHY_PIR]
/* Enable quasi-dynamic programming. */
mov tmp1, #0
mcr p15, 0, tmp1, c7, c10, 4
str tmp1, [r2, #UDDRC_SWCTRL]
ldr tmp1, [r0, #PM_DATA_PMC]
str tmp1, .pmc_base
ldr tmp1, [r0, #PM_DATA_RAMC0]
str tmp1, .sramc_base
ldr tmp1, [r0, #PM_DATA_RAMC1]
str tmp1, .sramc1_base
ldr tmp1, [r0, #PM_DATA_MEMCTRL]
str tmp1, .memtype
ldr tmp1, [r0, #PM_DATA_MODE]
str tmp1, .pm_mode
ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]
str tmp1, .mckr_offset
ldr tmp1, [r0, #PM_DATA_PMC_VERSION]
str tmp1, .pmc_version
/* Both ldrne below are here to preload their address in the TLB */
ldr tmp1, [r0, #PM_DATA_SHDWC]
str tmp1, .shdwc
cmp tmp1, #0
ldrne tmp2, [tmp1, #0]
ldr tmp1, [r0, #PM_DATA_SFRBU]
str tmp1, .sfrbu
cmp tmp1, #0
ldrne tmp2, [tmp1, #0x10]
/* De-assert SDRAM initialization. */
ldr tmp1, [r2, #UDDRC_DFIMISC]
bic tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN
str tmp1, [r2, #UDDRC_DFIMISC]
/* Active the self-refresh mode */
mov r0, #SRAMC_SELF_FRESH_ACTIVE
bl at91_sramc_self_refresh
/* Quasi-dynamic programming done. */
mov tmp1, #UDDRC_SWCTRL_SW_DONE
str tmp1, [r2, #UDDRC_SWCTRL]
ldr r0, .pm_mode
cmp r0, #AT91_PM_STANDBY
beq standby
cmp r0, #AT91_PM_BACKUP
beq backup_mode
sr_dis_1:
ldr tmp1, [r2, #UDDRC_SWSTAT]
tst tmp1, #UDDRC_SWSTAT_SW_DONE_ACK
beq sr_dis_1
bl at91_ulp_mode
b exit_suspend
/* DLL soft-reset + DLL lock wait + ITM reset */
mov tmp1, #(DDR3PHY_PIR_INIT | DDR3PHY_PIR_DLLSRST | \
DDR3PHY_PIR_DLLLOCK | DDR3PHY_PIR_ITMSRST)
str tmp1, [r3, #DDR3PHY_PIR]
standby:
/* Wait for interrupt */
ldr pmc, .pmc_base
at91_cpu_idle
b exit_suspend
sr_dis_4:
/* Wait for it. */
ldr tmp1, [r3, #DDR3PHY_PGSR]
tst tmp1, #DDR3PHY_PGSR_IDONE
beq sr_dis_4
backup_mode:
bl at91_backup_mode
b exit_suspend
/* Enable quasi-dynamic programming. */
mov tmp1, #0
str tmp1, [r2, #UDDRC_SWCTRL]
exit_suspend:
/* Exit the self-refresh mode */
mov r0, #SRAMC_SELF_FRESH_EXIT
bl at91_sramc_self_refresh
/* Assert PHY init complete enable signal. */
ldr tmp1, [r2, #UDDRC_DFIMISC]
orr tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN
str tmp1, [r2, #UDDRC_DFIMISC]
/* Restore registers, and return */
ldmfd sp!, {r4 - r12, pc}
ENDPROC(at91_pm_suspend_in_sram)
/* Programming is done. Set sw_done. */
mov tmp1, #UDDRC_SWCTRL_SW_DONE
str tmp1, [r2, #UDDRC_SWCTRL]
ENTRY(at91_backup_mode)
/* Switch the master clock source to slow clock. */
ldr pmc, .pmc_base
ldr tmp2, .mckr_offset
ldr tmp1, [pmc, tmp2]
bic tmp1, tmp1, #AT91_PMC_CSS
str tmp1, [pmc, tmp2]
sr_dis_5:
/* Wait for it. */
ldr tmp1, [r2, #UDDRC_SWSTAT]
tst tmp1, #UDDRC_SWSTAT_SW_DONE_ACK
beq sr_dis_5
wait_mckrdy
/* Trigger self-refresh exit. */
ldr tmp1, [r2, #UDDRC_PWRCTL]
bic tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW
str tmp1, [r2, #UDDRC_PWRCTL]
/*BUMEN*/
ldr r0, .sfrbu
mov tmp1, #0x1
str tmp1, [r0, #0x10]
sr_dis_6:
/* Wait for self-refresh exit done. */
ldr tmp1, [r2, #UDDRC_STAT]
bic tmp1, tmp1, #~UDDRC_STAT_OPMODE_MSK
cmp tmp1, #UDDRC_STAT_OPMODE_NORMAL
bne sr_dis_6
/* Shutdown */
ldr r0, .shdwc
mov tmp1, #0xA5000000
add tmp1, tmp1, #0x1
str tmp1, [r0, #0]
ENDPROC(at91_backup_mode)
/* Enable all AXI ports. */
ldr tmp1, [r2, #UDDRC_PCTRL_0]
orr tmp1, tmp1, #0x1
str tmp1, [r2, #UDDRC_PCTRL_0]
ldr tmp1, [r2, #UDDRC_PCTRL_1]
orr tmp1, tmp1, #0x1
str tmp1, [r2, #UDDRC_PCTRL_1]
ldr tmp1, [r2, #UDDRC_PCTRL_2]
orr tmp1, tmp1, #0x1
str tmp1, [r2, #UDDRC_PCTRL_2]
ldr tmp1, [r2, #UDDRC_PCTRL_3]
orr tmp1, tmp1, #0x1
str tmp1, [r2, #UDDRC_PCTRL_3]
ldr tmp1, [r2, #UDDRC_PCTRL_4]
orr tmp1, tmp1, #0x1
str tmp1, [r2, #UDDRC_PCTRL_4]
dsb
.endm
#else
/**
* Enable self-refresh
*
* register usage:
* @r1: memory type
* @r2: base address of the sram controller
* @r3: temporary
*/
.macro at91_sramc_self_refresh_ena
ldr r1, .memtype
ldr r2, .sramc_base
cmp r1, #AT91_MEMCTRL_MC
bne sr_ena_ddrc_sf
/* Active SDRAM self-refresh mode */
mov r3, #1
str r3, [r2, #AT91_MC_SDRAMC_SRR]
b sr_ena_exit
sr_ena_ddrc_sf:
cmp r1, #AT91_MEMCTRL_DDRSDR
bne sr_ena_sdramc_sf
/*
* DDR Memory controller
*/
/* LPDDR1 --> force DDR2 mode during self-refresh */
ldr r3, [r2, #AT91_DDRSDRC_MDR]
str r3, .saved_sam9_mdr
bic r3, r3, #~AT91_DDRSDRC_MD
cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
ldreq r3, [r2, #AT91_DDRSDRC_MDR]
biceq r3, r3, #AT91_DDRSDRC_MD
orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
streq r3, [r2, #AT91_DDRSDRC_MDR]
/* Active DDRC self-refresh mode */
ldr r3, [r2, #AT91_DDRSDRC_LPR]
str r3, .saved_sam9_lpr
bic r3, r3, #AT91_DDRSDRC_LPCB
orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
str r3, [r2, #AT91_DDRSDRC_LPR]
/* If using the 2nd ddr controller */
ldr r2, .sramc1_base
cmp r2, #0
beq sr_ena_no_2nd_ddrc
ldr r3, [r2, #AT91_DDRSDRC_MDR]
str r3, .saved_sam9_mdr1
bic r3, r3, #~AT91_DDRSDRC_MD
cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
ldreq r3, [r2, #AT91_DDRSDRC_MDR]
biceq r3, r3, #AT91_DDRSDRC_MD
orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
streq r3, [r2, #AT91_DDRSDRC_MDR]
/* Active DDRC self-refresh mode */
ldr r3, [r2, #AT91_DDRSDRC_LPR]
str r3, .saved_sam9_lpr1
bic r3, r3, #AT91_DDRSDRC_LPCB
orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
str r3, [r2, #AT91_DDRSDRC_LPR]
sr_ena_no_2nd_ddrc:
b sr_ena_exit
/*
* SDRAMC Memory controller
*/
sr_ena_sdramc_sf:
/* Active SDRAMC self-refresh mode */
ldr r3, [r2, #AT91_SDRAMC_LPR]
str r3, .saved_sam9_lpr
bic r3, r3, #AT91_SDRAMC_LPCB
orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
str r3, [r2, #AT91_SDRAMC_LPR]
ldr r3, .saved_sam9_lpr
str r3, [r2, #AT91_SDRAMC_LPR]
sr_ena_exit:
.endm
/**
* Disable self-refresh
*
* register usage:
* @r1: memory type
* @r2: base address of the sram controller
* @r3: temporary
*/
.macro at91_sramc_self_refresh_dis
ldr r1, .memtype
ldr r2, .sramc_base
cmp r1, #AT91_MEMCTRL_MC
bne sr_dis_ddrc_exit_sf
/*
* at91rm9200 Memory controller
*/
/*
* For exiting the self-refresh mode, do nothing,
* automatically exit the self-refresh mode.
*/
b sr_dis_exit
sr_dis_ddrc_exit_sf:
cmp r1, #AT91_MEMCTRL_DDRSDR
bne sdramc_exit_sf
/* DDR Memory controller */
/* Restore MDR in case of LPDDR1 */
ldr r3, .saved_sam9_mdr
str r3, [r2, #AT91_DDRSDRC_MDR]
/* Restore LPR on AT91 with DDRAM */
ldr r3, .saved_sam9_lpr
str r3, [r2, #AT91_DDRSDRC_LPR]
/* If using the 2nd ddr controller */
ldr r2, .sramc1_base
cmp r2, #0
ldrne r3, .saved_sam9_mdr1
strne r3, [r2, #AT91_DDRSDRC_MDR]
ldrne r3, .saved_sam9_lpr1
strne r3, [r2, #AT91_DDRSDRC_LPR]
b sr_dis_exit
sdramc_exit_sf:
/* SDRAMC Memory controller */
ldr r3, .saved_sam9_lpr
str r3, [r2, #AT91_SDRAMC_LPR]
sr_dis_exit:
.endm
#endif
.macro at91_pm_ulp0_mode
ldr pmc, .pmc_base
@ -176,7 +467,9 @@ ENDPROC(at91_backup_mode)
bic tmp1, tmp1, #AT91_PMC_PRES
orr tmp1, tmp1, #AT91_PMC_PRES_64
str tmp1, [pmc, tmp3]
wait_mckrdy
mov tmp3, #0
wait_mckrdy tmp3
b 1f
0:
@ -212,10 +505,13 @@ ENDPROC(at91_backup_mode)
bne 5f
/* Set lowest prescaler for fast resume. */
ldr tmp3, .mckr_offset
ldr tmp1, [pmc, tmp3]
bic tmp1, tmp1, #AT91_PMC_PRES
str tmp1, [pmc, tmp3]
wait_mckrdy
mov tmp3, #0
wait_mckrdy tmp3
b 6f
5: /* Restore RC oscillator state */
@ -252,6 +548,7 @@ ENDPROC(at91_backup_mode)
.macro at91_pm_ulp1_mode
ldr pmc, .pmc_base
ldr tmp2, .mckr_offset
mov tmp3, #0
/* Save RC oscillator state and check if it is enabled. */
ldr tmp1, [pmc, #AT91_PMC_SR]
@ -293,7 +590,7 @@ ENDPROC(at91_backup_mode)
orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
str tmp1, [pmc, tmp2]
wait_mckrdy
wait_mckrdy tmp3
/* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */
ldr tmp1, [pmc, #AT91_CKGR_MOR]
@ -306,7 +603,7 @@ ENDPROC(at91_backup_mode)
nop
nop
wait_mckrdy
wait_mckrdy tmp3
/* Enable the crystal oscillator */
ldr tmp1, [pmc, #AT91_CKGR_MOR]
@ -322,7 +619,7 @@ ENDPROC(at91_backup_mode)
bic tmp1, tmp1, #AT91_PMC_CSS
str tmp1, [pmc, tmp2]
wait_mckrdy
wait_mckrdy tmp3
/* Switch main clock source to crystal oscillator */
ldr tmp1, [pmc, #AT91_CKGR_MOR]
@ -339,7 +636,7 @@ ENDPROC(at91_backup_mode)
orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
str tmp1, [pmc, tmp2]
wait_mckrdy
wait_mckrdy tmp3
/* Restore RC oscillator state */
ldr tmp1, .saved_osc_status
@ -367,7 +664,7 @@ ENDPROC(at91_backup_mode)
cmp tmp1, #AT91_PMC_V1
beq 1f
#ifdef CONFIG_SOC_SAM9X60
#ifdef CONFIG_HAVE_AT91_SAM9X60_PLL
/* Save PLLA settings. */
ldr tmp2, [pmc, #AT91_PMC_PLL_UPDT]
bic tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID
@ -434,7 +731,7 @@ ENDPROC(at91_backup_mode)
cmp tmp3, #AT91_PMC_V1
beq 4f
#ifdef CONFIG_SOC_SAM9X60
#ifdef CONFIG_HAVE_AT91_SAM9X60_PLL
/* step 1. */
ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
@ -497,7 +794,122 @@ ENDPROC(at91_backup_mode)
2:
.endm
ENTRY(at91_ulp_mode)
/**
* at91_mckx_ps_enable: save MCK1..4 settings and switch it to main clock
*
* Side effects: overwrites tmp1, tmp2
*/
.macro at91_mckx_ps_enable
#ifdef CONFIG_SOC_SAMA7
ldr pmc, .pmc_base
/* There are 4 MCKs we need to handle: MCK1..4 */
mov tmp1, #1
e_loop: cmp tmp1, #5
beq e_done
/* Write MCK ID to retrieve the settings. */
str tmp1, [pmc, #AT91_PMC_MCR_V2]
ldr tmp2, [pmc, #AT91_PMC_MCR_V2]
e_save_mck1:
cmp tmp1, #1
bne e_save_mck2
str tmp2, .saved_mck1
b e_ps
e_save_mck2:
cmp tmp1, #2
bne e_save_mck3
str tmp2, .saved_mck2
b e_ps
e_save_mck3:
cmp tmp1, #3
bne e_save_mck4
str tmp2, .saved_mck3
b e_ps
e_save_mck4:
str tmp2, .saved_mck4
e_ps:
/* Use CSS=MAINCK and DIV=1. */
bic tmp2, tmp2, #AT91_PMC_MCR_V2_CSS
bic tmp2, tmp2, #AT91_PMC_MCR_V2_DIV
orr tmp2, tmp2, #AT91_PMC_MCR_V2_CSS_MAINCK
orr tmp2, tmp2, #AT91_PMC_MCR_V2_DIV1
str tmp2, [pmc, #AT91_PMC_MCR_V2]
wait_mckrdy tmp1
add tmp1, tmp1, #1
b e_loop
e_done:
#endif
.endm
/**
* at91_mckx_ps_restore: restore MCK1..4 settings
*
* Side effects: overwrites tmp1, tmp2
*/
.macro at91_mckx_ps_restore
#ifdef CONFIG_SOC_SAMA7
ldr pmc, .pmc_base
/* There are 4 MCKs we need to handle: MCK1..4 */
mov tmp1, #1
r_loop: cmp tmp1, #5
beq r_done
r_save_mck1:
cmp tmp1, #1
bne r_save_mck2
ldr tmp2, .saved_mck1
b r_ps
r_save_mck2:
cmp tmp1, #2
bne r_save_mck3
ldr tmp2, .saved_mck2
b r_ps
r_save_mck3:
cmp tmp1, #3
bne r_save_mck4
ldr tmp2, .saved_mck3
b r_ps
r_save_mck4:
ldr tmp2, .saved_mck4
r_ps:
/* Write MCK ID to retrieve the settings. */
str tmp1, [pmc, #AT91_PMC_MCR_V2]
ldr tmp3, [pmc, #AT91_PMC_MCR_V2]
/* We need to restore CSS and DIV. */
bic tmp3, tmp3, #AT91_PMC_MCR_V2_CSS
bic tmp3, tmp3, #AT91_PMC_MCR_V2_DIV
orr tmp3, tmp3, tmp2
bic tmp3, tmp3, #AT91_PMC_MCR_V2_ID_MSK
orr tmp3, tmp3, tmp1
orr tmp3, tmp3, #AT91_PMC_MCR_V2_CMD
str tmp2, [pmc, #AT91_PMC_MCR_V2]
wait_mckrdy tmp1
add tmp1, tmp1, #1
b r_loop
r_done:
#endif
.endm
.macro at91_ulp_mode
at91_mckx_ps_enable
ldr pmc, .pmc_base
ldr tmp2, .mckr_offset
ldr tmp3, .pm_mode
@ -518,10 +930,15 @@ ENTRY(at91_ulp_mode)
save_mck:
str tmp1, [pmc, tmp2]
wait_mckrdy
mov tmp3, #0
wait_mckrdy tmp3
at91_plla_disable
/* Enable low power mode for 2.5V regulator. */
at91_2_5V_reg_set_low_power 1
ldr tmp3, .pm_mode
cmp tmp3, #AT91_PM_ULP1
beq ulp1_mode
@ -533,6 +950,9 @@ ulp1_mode:
b ulp_exit
ulp_exit:
/* Disable low power mode for 2.5V regulator. */
at91_2_5V_reg_set_low_power 0
ldr pmc, .pmc_base
at91_plla_enable
@ -544,135 +964,110 @@ ulp_exit:
ldr tmp2, .saved_mckr
str tmp2, [pmc, tmp1]
wait_mckrdy
mov tmp3, #0
wait_mckrdy tmp3
mov pc, lr
ENDPROC(at91_ulp_mode)
at91_mckx_ps_restore
.endm
.macro at91_backup_mode
/* Switch the master clock source to slow clock. */
ldr pmc, .pmc_base
ldr tmp2, .mckr_offset
ldr tmp1, [pmc, tmp2]
bic tmp1, tmp1, #AT91_PMC_CSS
str tmp1, [pmc, tmp2]
mov tmp3, #0
wait_mckrdy tmp3
/*BUMEN*/
ldr r0, .sfrbu
mov tmp1, #0x1
str tmp1, [r0, #0x10]
/* Wait for it. */
1: ldr tmp1, [r0, #0x10]
tst tmp1, #0x1
beq 1b
/* Shutdown */
ldr r0, .shdwc
mov tmp1, #0xA5000000
add tmp1, tmp1, #0x1
at91_backup_set_lpm tmp1
str tmp1, [r0, #0]
.endm
/*
* void at91_sramc_self_refresh(unsigned int is_active)
*
* void at91_suspend_sram_fn(struct at91_pm_data*)
* @input param:
* @r0: 1 - active self-refresh mode
* 0 - exit self-refresh mode
* register usage:
* @r1: memory type
* @r2: base address of the sram controller
* @r0: base address of struct at91_pm_data
*/
/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */
.align 3
ENTRY(at91_pm_suspend_in_sram)
/* Save registers on stack */
stmfd sp!, {r4 - r12, lr}
ENTRY(at91_sramc_self_refresh)
ldr r1, .memtype
ldr r2, .sramc_base
/* Drain write buffer */
mov tmp1, #0
mcr p15, 0, tmp1, c7, c10, 4
cmp r1, #AT91_MEMCTRL_MC
bne ddrc_sf
ldr tmp1, [r0, #PM_DATA_PMC]
str tmp1, .pmc_base
ldr tmp1, [r0, #PM_DATA_RAMC0]
str tmp1, .sramc_base
ldr tmp1, [r0, #PM_DATA_RAMC1]
str tmp1, .sramc1_base
ldr tmp1, [r0, #PM_DATA_RAMC_PHY]
str tmp1, .sramc_phy_base
ldr tmp1, [r0, #PM_DATA_MEMCTRL]
str tmp1, .memtype
ldr tmp1, [r0, #PM_DATA_MODE]
str tmp1, .pm_mode
ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]
str tmp1, .mckr_offset
ldr tmp1, [r0, #PM_DATA_PMC_VERSION]
str tmp1, .pmc_version
/* Both ldrne below are here to preload their address in the TLB */
ldr tmp1, [r0, #PM_DATA_SHDWC]
str tmp1, .shdwc
cmp tmp1, #0
ldrne tmp2, [tmp1, #0]
ldr tmp1, [r0, #PM_DATA_SFRBU]
str tmp1, .sfrbu
cmp tmp1, #0
ldrne tmp2, [tmp1, #0x10]
/*
* at91rm9200 Memory controller
*/
/* Active the self-refresh mode */
at91_sramc_self_refresh_ena
/*
* For exiting the self-refresh mode, do nothing,
* automatically exit the self-refresh mode.
*/
tst r0, #SRAMC_SELF_FRESH_ACTIVE
beq exit_sramc_sf
ldr r0, .pm_mode
cmp r0, #AT91_PM_STANDBY
beq standby
cmp r0, #AT91_PM_BACKUP
beq backup_mode
/* Active SDRAM self-refresh mode */
mov r3, #1
str r3, [r2, #AT91_MC_SDRAMC_SRR]
b exit_sramc_sf
at91_ulp_mode
b exit_suspend
ddrc_sf:
cmp r1, #AT91_MEMCTRL_DDRSDR
bne sdramc_sf
standby:
/* Wait for interrupt */
ldr pmc, .pmc_base
at91_cpu_idle
b exit_suspend
/*
* DDR Memory controller
*/
tst r0, #SRAMC_SELF_FRESH_ACTIVE
beq ddrc_exit_sf
backup_mode:
at91_backup_mode
/* LPDDR1 --> force DDR2 mode during self-refresh */
ldr r3, [r2, #AT91_DDRSDRC_MDR]
str r3, .saved_sam9_mdr
bic r3, r3, #~AT91_DDRSDRC_MD
cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
ldreq r3, [r2, #AT91_DDRSDRC_MDR]
biceq r3, r3, #AT91_DDRSDRC_MD
orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
streq r3, [r2, #AT91_DDRSDRC_MDR]
exit_suspend:
/* Exit the self-refresh mode */
at91_sramc_self_refresh_dis
/* Active DDRC self-refresh mode */
ldr r3, [r2, #AT91_DDRSDRC_LPR]
str r3, .saved_sam9_lpr
bic r3, r3, #AT91_DDRSDRC_LPCB
orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
str r3, [r2, #AT91_DDRSDRC_LPR]
/* If using the 2nd ddr controller */
ldr r2, .sramc1_base
cmp r2, #0
beq no_2nd_ddrc
ldr r3, [r2, #AT91_DDRSDRC_MDR]
str r3, .saved_sam9_mdr1
bic r3, r3, #~AT91_DDRSDRC_MD
cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
ldreq r3, [r2, #AT91_DDRSDRC_MDR]
biceq r3, r3, #AT91_DDRSDRC_MD
orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
streq r3, [r2, #AT91_DDRSDRC_MDR]
/* Active DDRC self-refresh mode */
ldr r3, [r2, #AT91_DDRSDRC_LPR]
str r3, .saved_sam9_lpr1
bic r3, r3, #AT91_DDRSDRC_LPCB
orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
str r3, [r2, #AT91_DDRSDRC_LPR]
no_2nd_ddrc:
b exit_sramc_sf
ddrc_exit_sf:
/* Restore MDR in case of LPDDR1 */
ldr r3, .saved_sam9_mdr
str r3, [r2, #AT91_DDRSDRC_MDR]
/* Restore LPR on AT91 with DDRAM */
ldr r3, .saved_sam9_lpr
str r3, [r2, #AT91_DDRSDRC_LPR]
/* If using the 2nd ddr controller */
ldr r2, .sramc1_base
cmp r2, #0
ldrne r3, .saved_sam9_mdr1
strne r3, [r2, #AT91_DDRSDRC_MDR]
ldrne r3, .saved_sam9_lpr1
strne r3, [r2, #AT91_DDRSDRC_LPR]
b exit_sramc_sf
/*
* SDRAMC Memory controller
*/
sdramc_sf:
tst r0, #SRAMC_SELF_FRESH_ACTIVE
beq sdramc_exit_sf
/* Active SDRAMC self-refresh mode */
ldr r3, [r2, #AT91_SDRAMC_LPR]
str r3, .saved_sam9_lpr
bic r3, r3, #AT91_SDRAMC_LPCB
orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
str r3, [r2, #AT91_SDRAMC_LPR]
sdramc_exit_sf:
ldr r3, .saved_sam9_lpr
str r3, [r2, #AT91_SDRAMC_LPR]
exit_sramc_sf:
mov pc, lr
ENDPROC(at91_sramc_self_refresh)
/* Restore registers, and return */
ldmfd sp!, {r4 - r12, pc}
ENDPROC(at91_pm_suspend_in_sram)
.pmc_base:
.word 0
@ -680,6 +1075,8 @@ ENDPROC(at91_sramc_self_refresh)
.word 0
.sramc1_base:
.word 0
.sramc_phy_base:
.word 0
.shdwc:
.word 0
.sfrbu:
@ -706,6 +1103,16 @@ ENDPROC(at91_sramc_self_refresh)
.word 0
.saved_osc_status:
.word 0
#ifdef CONFIG_SOC_SAMA7
.saved_mck1:
.word 0
.saved_mck2:
.word 0
.saved_mck3:
.word 0
.saved_mck4:
.word 0
#endif
ENTRY(at91_pm_suspend_in_sram_sz)
.word .-at91_pm_suspend_in_sram

33
arch/arm/mach-at91/sama7.c Normal file
View File

@ -0,0 +1,33 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Setup code for SAMA7
*
* Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
*
*/
#include <linux/of.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/system_misc.h>
#include "generic.h"
static void __init sama7_dt_device_init(void)
{
of_platform_default_populate(NULL, NULL, NULL);
sama7_pm_init();
}
static const char *const sama7_dt_board_compat[] __initconst = {
"microchip,sama7",
NULL
};
DT_MACHINE_START(sama7_dt, "Microchip SAMA7")
/* Maintainer: Microchip */
.init_machine = sama7_dt_device_init,
.dt_compat = sama7_dt_board_compat,
MACHINE_END

5
arch/arm/mach-ep93xx/Kconfig
View File

@ -9,11 +9,6 @@ config EP93XX_SOC_COMMON
select SOC_BUS
select LEDS_GPIO_REGISTER
config CRUNCH
bool "Support for MaverickCrunch"
help
Enable kernel support for MaverickCrunch.
comment "EP93xx Platforms"
config MACH_ADSSPHERE

3
arch/arm/mach-ep93xx/Makefile
View File

@ -6,9 +6,6 @@ obj-y := core.o clock.o timer-ep93xx.o
obj-$(CONFIG_EP93XX_DMA) += dma.o
obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o
AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312
obj-$(CONFIG_MACH_ADSSPHERE) += adssphere.o
obj-$(CONFIG_MACH_EDB93XX) += edb93xx.o
obj-$(CONFIG_MACH_GESBC9312) += gesbc9312.o

1
arch/arm/mach-ep93xx/adssphere.c
View File

@ -36,6 +36,5 @@ MACHINE_START(ADSSPHERE, "ADS Sphere board")
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
.init_machine = adssphere_init_machine,
.init_late = ep93xx_init_late,
.restart = ep93xx_restart,
MACHINE_END

5
arch/arm/mach-ep93xx/core.c
View File

@ -1004,8 +1004,3 @@ void ep93xx_restart(enum reboot_mode mode, const char *cmd)
while (1)
;
}
void __init ep93xx_init_late(void)
{
crunch_init();
}

310
arch/arm/mach-ep93xx/crunch-bits.S
View File

@ -1,310 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/kernel/crunch-bits.S
* Cirrus MaverickCrunch context switching and handling
*
* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
*
* Shamelessly stolen from the iWMMXt code by Nicolas Pitre, which is
* Copyright (c) 2003-2004, MontaVista Software, Inc.
*/
#include <linux/linkage.h>
#include <asm/ptrace.h>
#include <asm/thread_info.h>
#include <asm/asm-offsets.h>
#include <asm/assembler.h>
#include <mach/ep93xx-regs.h>
/*
* We can't use hex constants here due to a bug in gas.
*/
#define CRUNCH_MVDX0 0
#define CRUNCH_MVDX1 8
#define CRUNCH_MVDX2 16
#define CRUNCH_MVDX3 24
#define CRUNCH_MVDX4 32
#define CRUNCH_MVDX5 40
#define CRUNCH_MVDX6 48
#define CRUNCH_MVDX7 56
#define CRUNCH_MVDX8 64
#define CRUNCH_MVDX9 72
#define CRUNCH_MVDX10 80
#define CRUNCH_MVDX11 88
#define CRUNCH_MVDX12 96
#define CRUNCH_MVDX13 104
#define CRUNCH_MVDX14 112
#define CRUNCH_MVDX15 120
#define CRUNCH_MVAX0L 128
#define CRUNCH_MVAX0M 132
#define CRUNCH_MVAX0H 136
#define CRUNCH_MVAX1L 140
#define CRUNCH_MVAX1M 144
#define CRUNCH_MVAX1H 148
#define CRUNCH_MVAX2L 152
#define CRUNCH_MVAX2M 156
#define CRUNCH_MVAX2H 160
#define CRUNCH_MVAX3L 164
#define CRUNCH_MVAX3M 168
#define CRUNCH_MVAX3H 172
#define CRUNCH_DSPSC 176
#define CRUNCH_SIZE 184
.text
/*
* Lazy switching of crunch coprocessor context
*
* r10 = struct thread_info pointer
* r9 = ret_from_exception
* lr = undefined instr exit
*
* called from prefetch exception handler with interrupts enabled
*/
ENTRY(crunch_task_enable)
inc_preempt_count r10, r3
ldr r8, =(EP93XX_APB_VIRT_BASE + 0x00130000) @ syscon addr
ldr r1, [r8, #0x80]
tst r1, #0x00800000 @ access to crunch enabled?
bne 2f @ if so no business here
mov r3, #0xaa @ unlock syscon swlock
str r3, [r8, #0xc0]
orr r1, r1, #0x00800000 @ enable access to crunch
str r1, [r8, #0x80]
ldr r3, =crunch_owner
add r0, r10, #TI_CRUNCH_STATE @ get task crunch save area
ldr r2, [sp, #60] @ current task pc value
ldr r1, [r3] @ get current crunch owner
str r0, [r3] @ this task now owns crunch
sub r2, r2, #4 @ adjust pc back
str r2, [sp, #60]
ldr r2, [r8, #0x80]
mov r2, r2 @ flush out enable (@@@)
teq r1, #0 @ test for last ownership
mov lr, r9 @ normal exit from exception
beq crunch_load @ no owner, skip save
crunch_save:
cfstr64 mvdx0, [r1, #CRUNCH_MVDX0] @ save 64b registers
cfstr64 mvdx1, [r1, #CRUNCH_MVDX1]
cfstr64 mvdx2, [r1, #CRUNCH_MVDX2]
cfstr64 mvdx3, [r1, #CRUNCH_MVDX3]
cfstr64 mvdx4, [r1, #CRUNCH_MVDX4]
cfstr64 mvdx5, [r1, #CRUNCH_MVDX5]
cfstr64 mvdx6, [r1, #CRUNCH_MVDX6]
cfstr64 mvdx7, [r1, #CRUNCH_MVDX7]
cfstr64 mvdx8, [r1, #CRUNCH_MVDX8]
cfstr64 mvdx9, [r1, #CRUNCH_MVDX9]
cfstr64 mvdx10, [r1, #CRUNCH_MVDX10]
cfstr64 mvdx11, [r1, #CRUNCH_MVDX11]
cfstr64 mvdx12, [r1, #CRUNCH_MVDX12]
cfstr64 mvdx13, [r1, #CRUNCH_MVDX13]
cfstr64 mvdx14, [r1, #CRUNCH_MVDX14]
cfstr64 mvdx15, [r1, #CRUNCH_MVDX15]
#ifdef __ARMEB__
#error fix me for ARMEB
#endif
cfmv32al mvfx0, mvax0 @ save 72b accumulators
cfstr32 mvfx0, [r1, #CRUNCH_MVAX0L]
cfmv32am mvfx0, mvax0
cfstr32 mvfx0, [r1, #CRUNCH_MVAX0M]
cfmv32ah mvfx0, mvax0
cfstr32 mvfx0, [r1, #CRUNCH_MVAX0H]
cfmv32al mvfx0, mvax1
cfstr32 mvfx0, [r1, #CRUNCH_MVAX1L]
cfmv32am mvfx0, mvax1
cfstr32 mvfx0, [r1, #CRUNCH_MVAX1M]
cfmv32ah mvfx0, mvax1
cfstr32 mvfx0, [r1, #CRUNCH_MVAX1H]
cfmv32al mvfx0, mvax2
cfstr32 mvfx0, [r1, #CRUNCH_MVAX2L]
cfmv32am mvfx0, mvax2
cfstr32 mvfx0, [r1, #CRUNCH_MVAX2M]
cfmv32ah mvfx0, mvax2
cfstr32 mvfx0, [r1, #CRUNCH_MVAX2H]
cfmv32al mvfx0, mvax3
cfstr32 mvfx0, [r1, #CRUNCH_MVAX3L]
cfmv32am mvfx0, mvax3
cfstr32 mvfx0, [r1, #CRUNCH_MVAX3M]
cfmv32ah mvfx0, mvax3
cfstr32 mvfx0, [r1, #CRUNCH_MVAX3H]
cfmv32sc mvdx0, dspsc @ save status word
cfstr64 mvdx0, [r1, #CRUNCH_DSPSC]
teq r0, #0 @ anything to load?
cfldr64eq mvdx0, [r1, #CRUNCH_MVDX0] @ mvdx0 was clobbered
beq 1f
crunch_load:
cfldr64 mvdx0, [r0, #CRUNCH_DSPSC] @ load status word
cfmvsc32 dspsc, mvdx0
cfldr32 mvfx0, [r0, #CRUNCH_MVAX0L] @ load 72b accumulators
cfmval32 mvax0, mvfx0
cfldr32 mvfx0, [r0, #CRUNCH_MVAX0M]
cfmvam32 mvax0, mvfx0
cfldr32 mvfx0, [r0, #CRUNCH_MVAX0H]
cfmvah32 mvax0, mvfx0
cfldr32 mvfx0, [r0, #CRUNCH_MVAX1L]
cfmval32 mvax1, mvfx0
cfldr32 mvfx0, [r0, #CRUNCH_MVAX1M]
cfmvam32 mvax1, mvfx0
cfldr32 mvfx0, [r0, #CRUNCH_MVAX1H]
cfmvah32 mvax1, mvfx0
cfldr32 mvfx0, [r0, #CRUNCH_MVAX2L]
cfmval32 mvax2, mvfx0
cfldr32 mvfx0, [r0, #CRUNCH_MVAX2M]
cfmvam32 mvax2, mvfx0
cfldr32 mvfx0, [r0, #CRUNCH_MVAX2H]
cfmvah32 mvax2, mvfx0
cfldr32 mvfx0, [r0, #CRUNCH_MVAX3L]
cfmval32 mvax3, mvfx0
cfldr32 mvfx0, [r0, #CRUNCH_MVAX3M]
cfmvam32 mvax3, mvfx0
cfldr32 mvfx0, [r0, #CRUNCH_MVAX3H]
cfmvah32 mvax3, mvfx0
cfldr64 mvdx0, [r0, #CRUNCH_MVDX0] @ load 64b registers
cfldr64 mvdx1, [r0, #CRUNCH_MVDX1]
cfldr64 mvdx2, [r0, #CRUNCH_MVDX2]
cfldr64 mvdx3, [r0, #CRUNCH_MVDX3]
cfldr64 mvdx4, [r0, #CRUNCH_MVDX4]
cfldr64 mvdx5, [r0, #CRUNCH_MVDX5]
cfldr64 mvdx6, [r0, #CRUNCH_MVDX6]
cfldr64 mvdx7, [r0, #CRUNCH_MVDX7]
cfldr64 mvdx8, [r0, #CRUNCH_MVDX8]
cfldr64 mvdx9, [r0, #CRUNCH_MVDX9]
cfldr64 mvdx10, [r0, #CRUNCH_MVDX10]
cfldr64 mvdx11, [r0, #CRUNCH_MVDX11]
cfldr64 mvdx12, [r0, #CRUNCH_MVDX12]
cfldr64 mvdx13, [r0, #CRUNCH_MVDX13]
cfldr64 mvdx14, [r0, #CRUNCH_MVDX14]
cfldr64 mvdx15, [r0, #CRUNCH_MVDX15]
1:
#ifdef CONFIG_PREEMPT_COUNT
get_thread_info r10
#endif
2: dec_preempt_count r10, r3
ret lr
/*
* Back up crunch regs to save area and disable access to them
* (mainly for gdb or sleep mode usage)
*
* r0 = struct thread_info pointer of target task or NULL for any
*/
ENTRY(crunch_task_disable)
stmfd sp!, {r4, r5, lr}
mrs ip, cpsr
orr r2, ip, #PSR_I_BIT @ disable interrupts
msr cpsr_c, r2
ldr r4, =(EP93XX_APB_VIRT_BASE + 0x00130000) @ syscon addr
ldr r3, =crunch_owner
add r2, r0, #TI_CRUNCH_STATE @ get task crunch save area
ldr r1, [r3] @ get current crunch owner
teq r1, #0 @ any current owner?
beq 1f @ no: quit
teq r0, #0 @ any owner?
teqne r1, r2 @ or specified one?
bne 1f @ no: quit
ldr r5, [r4, #0x80] @ enable access to crunch
mov r2, #0xaa
str r2, [r4, #0xc0]
orr r5, r5, #0x00800000
str r5, [r4, #0x80]
mov r0, #0 @ nothing to load
str r0, [r3] @ no more current owner
ldr r2, [r4, #0x80] @ flush out enable (@@@)
mov r2, r2
bl crunch_save
mov r2, #0xaa @ disable access to crunch
str r2, [r4, #0xc0]
bic r5, r5, #0x00800000
str r5, [r4, #0x80]
ldr r5, [r4, #0x80] @ flush out enable (@@@)
mov r5, r5
1: msr cpsr_c, ip @ restore interrupt mode
ldmfd sp!, {r4, r5, pc}
/*
* Copy crunch state to given memory address
*
* r0 = struct thread_info pointer of target task
* r1 = memory address where to store crunch state
*
* this is called mainly in the creation of signal stack frames
*/
ENTRY(crunch_task_copy)
mrs ip, cpsr
orr r2, ip, #PSR_I_BIT @ disable interrupts
msr cpsr_c, r2
ldr r3, =crunch_owner
add r2, r0, #TI_CRUNCH_STATE @ get task crunch save area
ldr r3, [r3] @ get current crunch owner
teq r2, r3 @ does this task own it...
beq 1f
@ current crunch values are in the task save area
msr cpsr_c, ip @ restore interrupt mode
mov r0, r1
mov r1, r2
mov r2, #CRUNCH_SIZE
b memcpy
1: @ this task owns crunch regs -- grab a copy from there
mov r0, #0 @ nothing to load
mov r3, lr @ preserve return address
bl crunch_save
msr cpsr_c, ip @ restore interrupt mode
ret r3
/*
* Restore crunch state from given memory address
*
* r0 = struct thread_info pointer of target task
* r1 = memory address where to get crunch state from
*
* this is used to restore crunch state when unwinding a signal stack frame
*/
ENTRY(crunch_task_restore)
mrs ip, cpsr
orr r2, ip, #PSR_I_BIT @ disable interrupts
msr cpsr_c, r2
ldr r3, =crunch_owner
add r2, r0, #TI_CRUNCH_STATE @ get task crunch save area
ldr r3, [r3] @ get current crunch owner
teq r2, r3 @ does this task own it...
beq 1f
@ this task doesn't own crunch regs -- use its save area
msr cpsr_c, ip @ restore interrupt mode
mov r0, r2
mov r2, #CRUNCH_SIZE
b memcpy
1: @ this task owns crunch regs -- load them directly
mov r0, r1
mov r1, #0 @ nothing to save
mov r3, lr @ preserve return address
bl crunch_load
msr cpsr_c, ip @ restore interrupt mode
ret r3

86
arch/arm/mach-ep93xx/crunch.c
View File

@ -1,86 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/kernel/crunch.c
* Cirrus MaverickCrunch context switching and handling
*
* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/thread_notify.h>
#include "soc.h"
struct crunch_state *crunch_owner;
void crunch_task_release(struct thread_info *thread)
{
local_irq_disable();
if (crunch_owner == &thread->crunchstate)
crunch_owner = NULL;
local_irq_enable();
}
static int crunch_enabled(u32 devcfg)
{
return !!(devcfg & EP93XX_SYSCON_DEVCFG_CPENA);
}
static int crunch_do(struct notifier_block *self, unsigned long cmd, void *t)
{
struct thread_info *thread = (struct thread_info *)t;
struct crunch_state *crunch_state;
u32 devcfg;
crunch_state = &thread->crunchstate;
switch (cmd) {
case THREAD_NOTIFY_FLUSH:
memset(crunch_state, 0, sizeof(*crunch_state));
/*
* FALLTHROUGH: Ensure we don't try to overwrite our newly
* initialised state information on the first fault.
*/
fallthrough;
case THREAD_NOTIFY_EXIT:
crunch_task_release(thread);
break;
case THREAD_NOTIFY_SWITCH:
devcfg = __raw_readl(EP93XX_SYSCON_DEVCFG);
if (crunch_enabled(devcfg) || crunch_owner == crunch_state) {
/*
* We don't use ep93xx_syscon_swlocked_write() here
* because we are on the context switch path and
* preemption is already disabled.
*/
devcfg ^= EP93XX_SYSCON_DEVCFG_CPENA;
__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
__raw_writel(devcfg, EP93XX_SYSCON_DEVCFG);
}
break;
}
return NOTIFY_DONE;
}
static struct notifier_block crunch_notifier_block = {
.notifier_call = crunch_do,
};
int __init crunch_init(void)
{
thread_register_notifier(&crunch_notifier_block);
elf_hwcap |= HWCAP_CRUNCH;
return 0;
}

8
arch/arm/mach-ep93xx/edb93xx.c
View File

@ -247,7 +247,6 @@ MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board")
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
.init_machine = edb93xx_init_machine,
.init_late = ep93xx_init_late,
.restart = ep93xx_restart,
MACHINE_END
#endif
@ -260,7 +259,6 @@ MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board")
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
.init_machine = edb93xx_init_machine,
.init_late = ep93xx_init_late,
.restart = ep93xx_restart,
MACHINE_END
#endif
@ -273,7 +271,6 @@ MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
.init_machine = edb93xx_init_machine,
.init_late = ep93xx_init_late,
.restart = ep93xx_restart,
MACHINE_END
#endif
@ -286,7 +283,6 @@ MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board")
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
.init_machine = edb93xx_init_machine,
.init_late = ep93xx_init_late,
.restart = ep93xx_restart,
MACHINE_END
#endif
@ -299,7 +295,6 @@ MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board")
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
.init_machine = edb93xx_init_machine,
.init_late = ep93xx_init_late,
.restart = ep93xx_restart,
MACHINE_END
#endif
@ -312,7 +307,6 @@ MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board")
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
.init_machine = edb93xx_init_machine,
.init_late = ep93xx_init_late,
.restart = ep93xx_restart,
MACHINE_END
#endif
@ -325,7 +319,6 @@ MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board")
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
.init_machine = edb93xx_init_machine,
.init_late = ep93xx_init_late,
.restart = ep93xx_restart,
MACHINE_END
#endif
@ -338,7 +331,6 @@ MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board")
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
.init_machine = edb93xx_init_machine,
.init_late = ep93xx_init_late,
.restart = ep93xx_restart,
MACHINE_END
#endif

1
arch/arm/mach-ep93xx/gesbc9312.c
View File

@ -36,6 +36,5 @@ MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx")
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
.init_machine = gesbc9312_init_machine,
.init_late = ep93xx_init_late,
.restart = ep93xx_restart,
MACHINE_END

4
arch/arm/mach-ep93xx/micro9.c
View File

@ -80,7 +80,6 @@ MACHINE_START(MICRO9, "Contec Micro9-High")
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
.init_machine = micro9_init_machine,
.init_late = ep93xx_init_late,
.restart = ep93xx_restart,
MACHINE_END
#endif
@ -93,7 +92,6 @@ MACHINE_START(MICRO9M, "Contec Micro9-Mid")
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
.init_machine = micro9_init_machine,
.init_late = ep93xx_init_late,
.restart = ep93xx_restart,
MACHINE_END
#endif
@ -106,7 +104,6 @@ MACHINE_START(MICRO9L, "Contec Micro9-Lite")
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
.init_machine = micro9_init_machine,
.init_late = ep93xx_init_late,
.restart = ep93xx_restart,
MACHINE_END
#endif
@ -119,7 +116,6 @@ MACHINE_START(MICRO9S, "Contec Micro9-Slim")
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
.init_machine = micro9_init_machine,
.init_late = ep93xx_init_late,
.restart = ep93xx_restart,
MACHINE_END
#endif

7
arch/arm/mach-ep93xx/platform.h
View File

@ -38,12 +38,5 @@ struct device *ep93xx_init_devices(void);
extern void ep93xx_timer_init(void);
void ep93xx_restart(enum reboot_mode, const char *);
void ep93xx_init_late(void);
#ifdef CONFIG_CRUNCH
int crunch_init(void);
#else
static inline int crunch_init(void) { return 0; }
#endif
#endif

1
arch/arm/mach-ep93xx/simone.c
View File

@ -123,6 +123,5 @@ MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board")
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
.init_machine = simone_init_machine,
.init_late = ep93xx_init_late,
.restart = ep93xx_restart,
MACHINE_END

1
arch/arm/mach-ep93xx/snappercl15.c
View File

@ -157,6 +157,5 @@ MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15")
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
.init_machine = snappercl15_init_machine,
.init_late = ep93xx_init_late,
.restart = ep93xx_restart,
MACHINE_END

2
arch/arm/mach-ep93xx/ts72xx.c
View File

@ -354,7 +354,6 @@ MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
.init_machine = ts72xx_init_machine,
.init_late = ep93xx_init_late,
.restart = ep93xx_restart,
MACHINE_END
@ -418,6 +417,5 @@ MACHINE_START(BK3, "Liebherr controller BK3.1")
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
.init_machine = bk3_init_machine,
.init_late = ep93xx_init_late,
.restart = ep93xx_restart,
MACHINE_END

1
arch/arm/mach-ep93xx/vision_ep9307.c
View File

@ -306,6 +306,5 @@ MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307")
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
.init_machine = vision_init_machine,
.init_late = ep93xx_init_late,
.restart = ep93xx_restart,
MACHINE_END

158
arch/arm/mach-ixp4xx/Kconfig
View File

@ -17,39 +17,6 @@ config MACH_IXP4XX_OF
help
Say 'Y' here to support Device Tree-based IXP4xx platforms.
config MACH_NSLU2
bool
prompt "Linksys NSLU2"
depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support Linksys's
NSLU2 NAS device. For more information on this platform,
see http://www.nslu2-linux.org
config MACH_AVILA
bool "Avila"
depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support the Gateworks
Avila Network Platform. For more information on this platform,
see <file:Documentation/arm/ixp4xx.rst>.
config MACH_LOFT
bool "Loft"
depends on MACH_AVILA
help
Say 'Y' here if you want your kernel to support the Giant
Shoulder Inc Loft board (a minor variation on the standard
Gateworks Avila Network Platform).
config ARCH_ADI_COYOTE
bool "Coyote"
depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support the ADI
Engineering Coyote Gateway Reference Platform. For more
information on this platform, see <file:Documentation/arm/ixp4xx.rst>.
config MACH_GATEWAY7001
bool "Gateway 7001"
depends on IXP4XX_PCI_LEGACY
@ -58,37 +25,6 @@ config MACH_GATEWAY7001
7001 Access Point. For more information on this platform,
see http://openwrt.org
config MACH_WG302V2
bool "Netgear WG302 v2 / WAG302 v2"
depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support Netgear's
WG302 v2 or WAG302 v2 Access Points. For more information
on this platform, see http://openwrt.org
config ARCH_IXDP425
bool "IXDP425"
depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support Intel's
IXDP425 Development Platform (Also known as Richfield).
For more information on this platform, see <file:Documentation/arm/ixp4xx.rst>.
config MACH_IXDPG425
bool "IXDPG425"
depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support Intel's
IXDPG425 Development Platform (Also known as Montajade).
For more information on this platform, see <file:Documentation/arm/ixp4xx.rst>.
config MACH_IXDP465
bool "IXDP465"
help
Say 'Y' here if you want your kernel to support Intel's
IXDP465 Development Platform (Also known as BMP).
For more information on this platform, see <file:Documentation/arm/ixp4xx.rst>.
config MACH_GORAMO_MLR
bool "GORAMO Multi Link Router"
depends on IXP4XX_PCI_LEGACY
@ -96,23 +32,6 @@ config MACH_GORAMO_MLR
Say 'Y' here if you want your kernel to support GORAMO
MultiLink router.
config MACH_KIXRP435
bool "KIXRP435"
help
Say 'Y' here if you want your kernel to support Intel's
KIXRP435 Reference Platform.
For more information on this platform, see <file:Documentation/arm/ixp4xx.rst>.
#
# IXCDP1100 is the exact same HW as IXDP425, but with a different machine
# number from the bootloader due to marketing monkeys, so we just enable it
# by default if IXDP425 is enabled.
#
config ARCH_IXCDP1100
bool
depends on ARCH_IXDP425
default y
config ARCH_PRPMC1100
bool "PrPMC1100"
help
@ -120,46 +39,6 @@ config ARCH_PRPMC1100
PrPCM1100 Processor Mezanine Module. For more information on
this platform, see <file:Documentation/arm/ixp4xx.rst>.
config MACH_NAS100D
bool
prompt "NAS100D"
depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support Iomega's
NAS 100d device. For more information on this platform,
see http://www.nslu2-linux.org/wiki/NAS100d/HomePage
config MACH_DSMG600
bool
prompt "D-Link DSM-G600 RevA"
depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support D-Link's
DSM-G600 RevA device. For more information on this platform,
see http://www.nslu2-linux.org/wiki/DSMG600/HomePage
config ARCH_IXDP4XX
bool
depends on ARCH_IXDP425 || MACH_IXDP465 || MACH_KIXRP435
default y
config MACH_FSG
bool
prompt "Freecom FSG-3"
depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support Freecom's
FSG-3 device. For more information on this platform,
see http://www.nslu2-linux.org/wiki/FSG3/HomePage
config MACH_ARCOM_VULCAN
bool
prompt "Arcom/Eurotech Vulcan"
depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support Arcom's
Vulcan board.
#
# Certain registers and IRQs are only enabled if supporting IXP465 CPUs
#
@ -173,43 +52,6 @@ config CPU_IXP43X
depends on MACH_KIXRP435
default y
config MACH_GTWX5715
bool "Gemtek WX5715 (Linksys WRV54G)"
depends on ARCH_IXP4XX
depends on IXP4XX_PCI_LEGACY
help
This board is currently inside the Linksys WRV54G Gateways.
IXP425 - 266mhz
32mb SDRAM
8mb Flash
miniPCI slot 0 does not have a card connector soldered to the board
miniPCI slot 1 has an ISL3880 802.11g card (Prism54)
npe0 is connected to a Kendin KS8995M Switch (4 ports)
npe1 is the "wan" port
"Console" UART is available on J11 as console
"High Speed" UART is n/c (as far as I can tell)
20 Pin ARM/Xscale JTAG interface on J2
config MACH_DEVIXP
bool "Omicron DEVIXP"
help
Say 'Y' here if you want your kernel to support the DEVIXP
board from OMICRON electronics GmbH.
config MACH_MICCPT
bool "Omicron MICCPT"
depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support the MICCPT
board from OMICRON electronics GmbH.
config MACH_MIC256
bool "Omicron MIC256"
help
Say 'Y' here if you want your kernel to support the MIC256
board from OMICRON electronics GmbH.
comment "IXP4xx Options"
config IXP4XX_PCI_LEGACY

26
arch/arm/mach-ixp4xx/Makefile
View File

@ -9,37 +9,11 @@ obj-pci-n :=
# Device tree platform
obj-pci-$(CONFIG_MACH_IXP4XX_OF) += ixp4xx-of.o
obj-pci-$(CONFIG_ARCH_IXDP4XX) += ixdp425-pci.o
obj-pci-$(CONFIG_MACH_AVILA) += avila-pci.o
obj-pci-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o
obj-pci-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o
obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o
obj-pci-$(CONFIG_MACH_MICCPT) += miccpt-pci.o
obj-pci-$(CONFIG_MACH_NSLU2) += nslu2-pci.o
obj-pci-$(CONFIG_MACH_NAS100D) += nas100d-pci.o
obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o
obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o
obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o
obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
obj-pci-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-pci.o
obj-y += common.o
obj-$(CONFIG_ARCH_IXDP4XX) += ixdp425-setup.o
obj-$(CONFIG_MACH_AVILA) += avila-setup.o
obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o
obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o
obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o
obj-$(CONFIG_MACH_DEVIXP) += omixp-setup.o
obj-$(CONFIG_MACH_MICCPT) += omixp-setup.o
obj-$(CONFIG_MACH_MIC256) += omixp-setup.o
obj-$(CONFIG_MACH_NSLU2) += nslu2-setup.o
obj-$(CONFIG_MACH_NAS100D) += nas100d-setup.o
obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o
obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o
obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
obj-$(CONFIG_MACH_FSG) += fsg-setup.o
obj-$(CONFIG_MACH_GORAMO_MLR) += goramo_mlr.o
obj-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-setup.o
obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o

79
arch/arm/mach-ixp4xx/avila-pci.c
View File

@ -1,79 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-ixp4xx/avila-pci.c
*
* Gateworks Avila board-level PCI initialization
*
* Author: Michael-Luke Jones <mlj28@cam.ac.uk>
*
* Based on ixdp-pci.c
* Copyright (C) 2002 Intel Corporation.
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*
* Maintainer: Deepak Saxena <dsaxena@plexity.net>
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <asm/mach/pci.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include "irqs.h"
#define AVILA_MAX_DEV 4
#define LOFT_MAX_DEV 6
#define IRQ_LINES 4
/* PCI controller GPIO to IRQ pin mappings */
#define INTA 11
#define INTB 10
#define INTC 9
#define INTD 8
void __init avila_pci_preinit(void)
{
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init avila_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[IRQ_LINES] = {
IXP4XX_GPIO_IRQ(INTA),
IXP4XX_GPIO_IRQ(INTB),
IXP4XX_GPIO_IRQ(INTC),
IXP4XX_GPIO_IRQ(INTD)
};
if (slot >= 1 &&
slot <= (machine_is_loft() ? LOFT_MAX_DEV : AVILA_MAX_DEV) &&
pin >= 1 && pin <= IRQ_LINES)
return pci_irq_table[(slot + pin - 2) % 4];
return -1;
}
struct hw_pci avila_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = avila_pci_preinit,
.setup = ixp4xx_setup,
.map_irq = avila_map_irq,
};
int __init avila_pci_init(void)
{
if (machine_is_avila() || machine_is_loft())
pci_common_init(&avila_pci);
return 0;
}
subsys_initcall(avila_pci_init);

210
arch/arm/mach-ixp4xx/avila-setup.c
View File

@ -1,210 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* arch/arm/mach-ixp4xx/avila-setup.c
*
* Gateworks Avila board-setup
*
* Author: Michael-Luke Jones <mlj28@cam.ac.uk>
*
* Based on ixdp-setup.c
* Copyright (C) 2003-2005 MontaVista Software, Inc.
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_8250.h>
#include <linux/gpio/machine.h>
#include <linux/platform_data/pata_ixp4xx_cf.h>
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include "irqs.h"
#define AVILA_SDA_PIN 7
#define AVILA_SCL_PIN 6
static struct flash_platform_data avila_flash_data = {
.map_name = "cfi_probe",
.width = 2,
};
static struct resource avila_flash_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device avila_flash = {
.name = "IXP4XX-Flash",
.id = 0,
.dev = {
.platform_data = &avila_flash_data,
},
.num_resources = 1,
.resource = &avila_flash_resource,
};
static struct gpiod_lookup_table avila_i2c_gpiod_table = {
.dev_id = "i2c-gpio.0",
.table = {
GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", AVILA_SDA_PIN,
NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", AVILA_SCL_PIN,
NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
},
};
static struct platform_device avila_i2c_gpio = {
.name = "i2c-gpio",
.id = 0,
.dev = {
.platform_data = NULL,
},
};
static struct resource avila_uart_resources[] = {
{
.start = IXP4XX_UART1_BASE_PHYS,
.end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM
},
{
.start = IXP4XX_UART2_BASE_PHYS,
.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM
}
};
static struct plat_serial8250_port avila_uart_data[] = {
{
.mapbase = IXP4XX_UART1_BASE_PHYS,
.membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART1,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
{
.mapbase = IXP4XX_UART2_BASE_PHYS,
.membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART2,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
{ },
};
static struct platform_device avila_uart = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev.platform_data = avila_uart_data,
.num_resources = 2,
.resource = avila_uart_resources
};
static struct resource avila_pata_resources[] = {
{
.flags = IORESOURCE_MEM
},
{
.flags = IORESOURCE_MEM,
},
{
.name = "intrq",
.start = IRQ_IXP4XX_GPIO12,
.end = IRQ_IXP4XX_GPIO12,
.flags = IORESOURCE_IRQ,
},
};
static struct ixp4xx_pata_data avila_pata_data = {
.cs0_bits = 0xbfff0043,
.cs1_bits = 0xbfff0043,
};
static struct platform_device avila_pata = {
.name = "pata_ixp4xx_cf",
.id = 0,
.dev.platform_data = &avila_pata_data,
.num_resources = ARRAY_SIZE(avila_pata_resources),
.resource = avila_pata_resources,
};
static struct platform_device *avila_devices[] __initdata = {
&avila_i2c_gpio,
&avila_flash,
&avila_uart
};
static void __init avila_init(void)
{
ixp4xx_sys_init();
avila_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
avila_flash_resource.end =
IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
gpiod_add_lookup_table(&avila_i2c_gpiod_table);
platform_add_devices(avila_devices, ARRAY_SIZE(avila_devices));
avila_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(1);
avila_pata_resources[0].end = IXP4XX_EXP_BUS_END(1);
avila_pata_resources[1].start = IXP4XX_EXP_BUS_BASE(2);
avila_pata_resources[1].end = IXP4XX_EXP_BUS_END(2);
avila_pata_data.cs0_cfg = IXP4XX_EXP_CS1;
avila_pata_data.cs1_cfg = IXP4XX_EXP_CS2;
platform_device_register(&avila_pata);
}
MACHINE_START(AVILA, "Gateworks Avila Network Platform")
/* Maintainer: Deepak Saxena <dsaxena@plexity.net> */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.init_time = ixp4xx_timer_init,
.atag_offset = 0x100,
.init_machine = avila_init,
#if defined(CONFIG_PCI)
.dma_zone_size = SZ_64M,
#endif
.restart = ixp4xx_restart,
MACHINE_END
/*
* Loft is functionally equivalent to Avila except that it has a
* different number for the maximum PCI devices. The MACHINE
* structure below is identical to Avila except for the comment.
*/
#ifdef CONFIG_MACH_LOFT
MACHINE_START(LOFT, "Giant Shoulder Inc Loft board")
/* Maintainer: Tom Billman <kernel@giantshoulderinc.com> */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.init_time = ixp4xx_timer_init,
.atag_offset = 0x100,
.init_machine = avila_init,
#if defined(CONFIG_PCI)
.dma_zone_size = SZ_64M,
#endif
.restart = ixp4xx_restart,
MACHINE_END
#endif

62
arch/arm/mach-ixp4xx/coyote-pci.c
View File

@ -1,62 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-ixp4xx/coyote-pci.c
*
* PCI setup routines for ADI Engineering Coyote platform
*
* Copyright (C) 2002 Jungo Software Technologies.
* Copyright (C) 2003 MontaVista Softwrae, Inc.
*
* Maintainer: Deepak Saxena <dsaxena@mvista.com>
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include "irqs.h"
#define SLOT0_DEVID 14
#define SLOT1_DEVID 15
/* PCI controller GPIO to IRQ pin mappings */
#define SLOT0_INTA 6
#define SLOT1_INTA 11
void __init coyote_pci_preinit(void)
{
irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init coyote_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
if (slot == SLOT0_DEVID)
return IXP4XX_GPIO_IRQ(SLOT0_INTA);
else if (slot == SLOT1_DEVID)
return IXP4XX_GPIO_IRQ(SLOT1_INTA);
else return -1;
}
struct hw_pci coyote_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = coyote_pci_preinit,
.setup = ixp4xx_setup,
.map_irq = coyote_map_irq,
};
int __init coyote_pci_init(void)
{
if (machine_is_adi_coyote())
pci_common_init(&coyote_pci);
return 0;
}
subsys_initcall(coyote_pci_init);

144
arch/arm/mach-ixp4xx/coyote-setup.c
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@ -1,144 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* arch/arm/mach-ixp4xx/coyote-setup.c
*
* Board setup for ADI Engineering and IXDGP425 boards
*
* Copyright (C) 2003-2005 MontaVista Software, Inc.
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_8250.h>
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include "irqs.h"
#define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_BASE(3)
#define COYOTE_IDE_BASE_VIRT 0xFFFE1000
#define COYOTE_IDE_REGION_SIZE 0x1000
#define COYOTE_IDE_DATA_PORT 0xFFFE10E0
#define COYOTE_IDE_CTRL_PORT 0xFFFE10FC
#define COYOTE_IDE_ERROR_PORT 0xFFFE10E2
#define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5
static struct flash_platform_data coyote_flash_data = {
.map_name = "cfi_probe",
.width = 2,
};
static struct resource coyote_flash_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device coyote_flash = {
.name = "IXP4XX-Flash",
.id = 0,
.dev = {
.platform_data = &coyote_flash_data,
},
.num_resources = 1,
.resource = &coyote_flash_resource,
};
static struct resource coyote_uart_resource = {
.start = IXP4XX_UART2_BASE_PHYS,
.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
};
static struct plat_serial8250_port coyote_uart_data[] = {
{
.mapbase = IXP4XX_UART2_BASE_PHYS,
.membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART2,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
{ },
};
static struct platform_device coyote_uart = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = coyote_uart_data,
},
.num_resources = 1,
.resource = &coyote_uart_resource,
};
static struct platform_device *coyote_devices[] __initdata = {
&coyote_flash,
&coyote_uart
};
static void __init coyote_init(void)
{
ixp4xx_sys_init();
coyote_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
coyote_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
*IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
*IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
if (machine_is_ixdpg425()) {
coyote_uart_data[0].membase =
(char*)(IXP4XX_UART1_BASE_VIRT + REG_OFFSET);
coyote_uart_data[0].mapbase = IXP4XX_UART1_BASE_PHYS;
coyote_uart_data[0].irq = IRQ_IXP4XX_UART1;
}
platform_add_devices(coyote_devices, ARRAY_SIZE(coyote_devices));
}
#ifdef CONFIG_ARCH_ADI_COYOTE
MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote")
/* Maintainer: MontaVista Software, Inc. */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.init_time = ixp4xx_timer_init,
.atag_offset = 0x100,
.init_machine = coyote_init,
#if defined(CONFIG_PCI)
.dma_zone_size = SZ_64M,
#endif
.restart = ixp4xx_restart,
MACHINE_END
#endif
/*
* IXDPG425 is identical to Coyote except for which serial port
* is connected.
*/
#ifdef CONFIG_MACH_IXDPG425
MACHINE_START(IXDPG425, "Intel IXDPG425")
/* Maintainer: MontaVista Software, Inc. */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.init_time = ixp4xx_timer_init,
.atag_offset = 0x100,
.init_machine = coyote_init,
.restart = ixp4xx_restart,
MACHINE_END
#endif

77
arch/arm/mach-ixp4xx/dsmg600-pci.c
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@ -1,77 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* DSM-G600 board-level PCI initialization
*
* Copyright (C) 2006 Tower Technologies
* Author: Alessandro Zummo <a.zummo@towertech.it>
*
* based on ixdp425-pci.c:
* Copyright (C) 2002 Intel Corporation.
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*
* Maintainer: http://www.nslu2-linux.org/
*/
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
#include "irqs.h"
#define MAX_DEV 4
#define IRQ_LINES 3
/* PCI controller GPIO to IRQ pin mappings */
#define INTA 11
#define INTB 10
#define INTC 9
#define INTD 8
#define INTE 7
#define INTF 6
void __init dsmg600_pci_preinit(void)
{
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init dsmg600_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[MAX_DEV][IRQ_LINES] = {
{ IXP4XX_GPIO_IRQ(INTE), -1, -1 },
{ IXP4XX_GPIO_IRQ(INTA), -1, -1 },
{ IXP4XX_GPIO_IRQ(INTB), IXP4XX_GPIO_IRQ(INTC),
IXP4XX_GPIO_IRQ(INTD) },
{ IXP4XX_GPIO_IRQ(INTF), -1, -1 },
};
if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
return pci_irq_table[slot - 1][pin - 1];
return -1;
}
struct hw_pci __initdata dsmg600_pci = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = dsmg600_pci_preinit,
.setup = ixp4xx_setup,
.map_irq = dsmg600_map_irq,
};
int __init dsmg600_pci_init(void)
{
if (machine_is_dsmg600())
pci_common_init(&dsmg600_pci);
return 0;
}
subsys_initcall(dsmg600_pci_init);

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arch/arm/mach-ixp4xx/dsmg600-setup.c
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@ -1,304 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* DSM-G600 board-setup
*
* Copyright (C) 2008 Rod Whitby <rod@whitby.id.au>
* Copyright (C) 2006 Tower Technologies
*
* based on ixdp425-setup.c:
* Copyright (C) 2003-2004 MontaVista Software, Inc.
* based on nslu2-power.c:
* Copyright (C) 2005 Tower Technologies
* based on nslu2-io.c:
* Copyright (C) 2004 Karen Spearel
*
* Author: Alessandro Zummo <a.zummo@towertech.it>
* Author: Michael Westerhof <mwester@dls.net>
* Author: Rod Whitby <rod@whitby.id.au>
* Maintainers: http://www.nslu2-linux.org/
*/
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/jiffies.h>
#include <linux/timer.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
#include <linux/leds.h>
#include <linux/reboot.h>
#include <linux/i2c.h>
#include <linux/gpio/machine.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/time.h>
#include "irqs.h"
#define DSMG600_SDA_PIN 5
#define DSMG600_SCL_PIN 4
/* DSM-G600 Timer Setting */
#define DSMG600_FREQ 66000000
/* Buttons */
#define DSMG600_PB_GPIO 15 /* power button */
#define DSMG600_RB_GPIO 3 /* reset button */
/* Power control */
#define DSMG600_PO_GPIO 2 /* power off */
/* LEDs */
#define DSMG600_LED_PWR_GPIO 0
#define DSMG600_LED_WLAN_GPIO 14
static struct flash_platform_data dsmg600_flash_data = {
.map_name = "cfi_probe",
.width = 2,
};
static struct resource dsmg600_flash_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device dsmg600_flash = {
.name = "IXP4XX-Flash",
.id = 0,
.dev.platform_data = &dsmg600_flash_data,
.num_resources = 1,
.resource = &dsmg600_flash_resource,
};
static struct gpiod_lookup_table dsmg600_i2c_gpiod_table = {
.dev_id = "i2c-gpio.0",
.table = {
GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", DSMG600_SDA_PIN,
NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", DSMG600_SCL_PIN,
NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
},
};
static struct platform_device dsmg600_i2c_gpio = {
.name = "i2c-gpio",
.id = 0,
.dev = {
.platform_data = NULL,
},
};
static struct i2c_board_info __initdata dsmg600_i2c_board_info [] = {
{
I2C_BOARD_INFO("pcf8563", 0x51),
},
};
static struct gpio_led dsmg600_led_pins[] = {
{
.name = "dsmg600:green:power",
.gpio = DSMG600_LED_PWR_GPIO,
},
{
.name = "dsmg600:green:wlan",
.gpio = DSMG600_LED_WLAN_GPIO,
.active_low = true,
},
};
static struct gpio_led_platform_data dsmg600_led_data = {
.num_leds = ARRAY_SIZE(dsmg600_led_pins),
.leds = dsmg600_led_pins,
};
static struct platform_device dsmg600_leds = {
.name = "leds-gpio",
.id = -1,
.dev.platform_data = &dsmg600_led_data,
};
static struct resource dsmg600_uart_resources[] = {
{
.start = IXP4XX_UART1_BASE_PHYS,
.end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
{
.start = IXP4XX_UART2_BASE_PHYS,
.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
}
};
static struct plat_serial8250_port dsmg600_uart_data[] = {
{
.mapbase = IXP4XX_UART1_BASE_PHYS,
.membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART1,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
{
.mapbase = IXP4XX_UART2_BASE_PHYS,
.membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART2,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
{ }
};
static struct platform_device dsmg600_uart = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev.platform_data = dsmg600_uart_data,
.num_resources = ARRAY_SIZE(dsmg600_uart_resources),
.resource = dsmg600_uart_resources,
};
static struct platform_device *dsmg600_devices[] __initdata = {
&dsmg600_i2c_gpio,
&dsmg600_flash,
&dsmg600_leds,
};
static void dsmg600_power_off(void)
{
/* enable the pwr cntl and drive it high */
gpio_direction_output(DSMG600_PO_GPIO, 1);
}
/* This is used to make sure the power-button pusher is serious. The button
* must be held until the value of this counter reaches zero.
*/
static int power_button_countdown;
/* Must hold the button down for at least this many counts to be processed */
#define PBUTTON_HOLDDOWN_COUNT 4 /* 2 secs */
static void dsmg600_power_handler(struct timer_list *unused);
static DEFINE_TIMER(dsmg600_power_timer, dsmg600_power_handler);
static void dsmg600_power_handler(struct timer_list *unused)
{
/* This routine is called twice per second to check the
* state of the power button.
*/
if (gpio_get_value(DSMG600_PB_GPIO)) {
/* IO Pin is 1 (button pushed) */
if (power_button_countdown > 0)
power_button_countdown--;
} else {
/* Done on button release, to allow for auto-power-on mods. */
if (power_button_countdown == 0) {
/* Signal init to do the ctrlaltdel action,
* this will bypass init if it hasn't started
* and do a kernel_restart.
*/
ctrl_alt_del();
/* Change the state of the power LED to "blink" */
gpio_set_value(DSMG600_LED_PWR_GPIO, 0);
} else {
power_button_countdown = PBUTTON_HOLDDOWN_COUNT;
}
}
mod_timer(&dsmg600_power_timer, jiffies + msecs_to_jiffies(500));
}
static irqreturn_t dsmg600_reset_handler(int irq, void *dev_id)
{
/* This is the paper-clip reset, it shuts the machine down directly. */
machine_power_off();
return IRQ_HANDLED;
}
static void __init dsmg600_timer_init(void)
{
/* The xtal on this machine is non-standard. */
ixp4xx_timer_freq = DSMG600_FREQ;
/* Call standard timer_init function. */
ixp4xx_timer_init();
}
static int __init dsmg600_gpio_init(void)
{
if (!machine_is_dsmg600())
return 0;
gpio_request(DSMG600_RB_GPIO, "reset button");
if (request_irq(gpio_to_irq(DSMG600_RB_GPIO), &dsmg600_reset_handler,
IRQF_TRIGGER_LOW, "DSM-G600 reset button", NULL) < 0) {
printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
gpio_to_irq(DSMG600_RB_GPIO));
}
/*
* The power button on the D-Link DSM-G600 is on GPIO 15, but
* it cannot handle interrupts on that GPIO line. So we'll
* have to poll it with a kernel timer.
*/
/* Make sure that the power button GPIO is set up as an input */
gpio_request(DSMG600_PB_GPIO, "power button");
gpio_direction_input(DSMG600_PB_GPIO);
/* Request poweroff GPIO line */
gpio_request(DSMG600_PO_GPIO, "power off button");
/* Set the initial value for the power button IRQ handler */
power_button_countdown = PBUTTON_HOLDDOWN_COUNT;
mod_timer(&dsmg600_power_timer, jiffies + msecs_to_jiffies(500));
return 0;
}
device_initcall(dsmg600_gpio_init);
static void __init dsmg600_init(void)
{
ixp4xx_sys_init();
dsmg600_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
dsmg600_flash_resource.end =
IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
gpiod_add_lookup_table(&dsmg600_i2c_gpiod_table);
i2c_register_board_info(0, dsmg600_i2c_board_info,
ARRAY_SIZE(dsmg600_i2c_board_info));
/* The UART is required on the DSM-G600 (Redboot cannot use the
* NIC) -- do it here so that it does *not* get removed if
* platform_add_devices fails!
*/
(void)platform_device_register(&dsmg600_uart);
platform_add_devices(dsmg600_devices, ARRAY_SIZE(dsmg600_devices));
pm_power_off = dsmg600_power_off;
}
MACHINE_START(DSMG600, "D-Link DSM-G600 RevA")
/* Maintainer: www.nslu2-linux.org */
.atag_offset = 0x100,
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.init_time = dsmg600_timer_init,
.init_machine = dsmg600_init,
#if defined(CONFIG_PCI)
.dma_zone_size = SZ_64M,
#endif
.restart = ixp4xx_restart,
MACHINE_END

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arch/arm/mach-ixp4xx/fsg-pci.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arch/mach-ixp4xx/fsg-pci.c
*
* FSG board-level PCI initialization
*
* Author: Rod Whitby <rod@whitby.id.au>
* Maintainer: http://www.nslu2-linux.org/
*
* based on ixdp425-pci.c:
* Copyright (C) 2002 Intel Corporation.
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*/
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
#include "irqs.h"
#define MAX_DEV 3
#define IRQ_LINES 3
/* PCI controller GPIO to IRQ pin mappings */
#define INTA 6
#define INTB 7
#define INTC 5
void __init fsg_pci_preinit(void)
{
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init fsg_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[IRQ_LINES] = {
IXP4XX_GPIO_IRQ(INTC),
IXP4XX_GPIO_IRQ(INTB),
IXP4XX_GPIO_IRQ(INTA),
};
int irq = -1;
slot -= 11;
if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
irq = pci_irq_table[slot - 1];
printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n",
__func__, slot, pin, irq);
return irq;
}
struct hw_pci fsg_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = fsg_pci_preinit,
.setup = ixp4xx_setup,
.map_irq = fsg_map_irq,
};
int __init fsg_pci_init(void)
{
if (machine_is_fsg())
pci_common_init(&fsg_pci);
return 0;
}
subsys_initcall(fsg_pci_init);

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arch/arm/mach-ixp4xx/fsg-setup.c
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// SPDX-License-Identifier: GPL-2.0
/*
* arch/arm/mach-ixp4xx/fsg-setup.c
*
* FSG board-setup
*
* Copyright (C) 2008 Rod Whitby <rod@whitby.id.au>
*
* based on ixdp425-setup.c:
* Copyright (C) 2003-2004 MontaVista Software, Inc.
* based on nslu2-power.c
* Copyright (C) 2005 Tower Technologies
*
* Author: Rod Whitby <rod@whitby.id.au>
* Maintainers: http://www.nslu2-linux.org/
*
*/
#include <linux/gpio.h>
#include <linux/if_ether.h>
#include <linux/irq.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
#include <linux/leds.h>
#include <linux/reboot.h>
#include <linux/i2c.h>
#include <linux/gpio/machine.h>
#include <linux/io.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <mach/hardware.h>
#include "irqs.h"
#define FSG_SDA_PIN 12
#define FSG_SCL_PIN 13
#define FSG_SB_GPIO 4 /* sync button */
#define FSG_RB_GPIO 9 /* reset button */
#define FSG_UB_GPIO 10 /* usb button */
static struct flash_platform_data fsg_flash_data = {
.map_name = "cfi_probe",
.width = 2,
};
static struct resource fsg_flash_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device fsg_flash = {
.name = "IXP4XX-Flash",
.id = 0,
.dev = {
.platform_data = &fsg_flash_data,
},
.num_resources = 1,
.resource = &fsg_flash_resource,
};
static struct gpiod_lookup_table fsg_i2c_gpiod_table = {
.dev_id = "i2c-gpio.0",
.table = {
GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", FSG_SDA_PIN,
NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", FSG_SCL_PIN,
NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
},
};
static struct platform_device fsg_i2c_gpio = {
.name = "i2c-gpio",
.id = 0,
.dev = {
.platform_data = NULL,
},
};
static struct i2c_board_info __initdata fsg_i2c_board_info [] = {
{
I2C_BOARD_INFO("isl1208", 0x6f),
},
};
static struct resource fsg_uart_resources[] = {
{
.start = IXP4XX_UART1_BASE_PHYS,
.end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
{
.start = IXP4XX_UART2_BASE_PHYS,
.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
}
};
static struct plat_serial8250_port fsg_uart_data[] = {
{
.mapbase = IXP4XX_UART1_BASE_PHYS,
.membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART1,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
{
.mapbase = IXP4XX_UART2_BASE_PHYS,
.membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART2,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
{ }
};
static struct platform_device fsg_uart = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = fsg_uart_data,
},
.num_resources = ARRAY_SIZE(fsg_uart_resources),
.resource = fsg_uart_resources,
};
static struct platform_device fsg_leds = {
.name = "fsg-led",
.id = -1,
};
/* Built-in 10/100 Ethernet MAC interfaces */
static struct resource fsg_eth_npeb_resources[] = {
{
.start = IXP4XX_EthB_BASE_PHYS,
.end = IXP4XX_EthB_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
};
static struct resource fsg_eth_npec_resources[] = {
{
.start = IXP4XX_EthC_BASE_PHYS,
.end = IXP4XX_EthC_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
};
static struct eth_plat_info fsg_plat_eth[] = {
{
.phy = 5,
.rxq = 3,
.txreadyq = 20,
}, {
.phy = 4,
.rxq = 4,
.txreadyq = 21,
}
};
static struct platform_device fsg_eth[] = {
{
.name = "ixp4xx_eth",
.id = IXP4XX_ETH_NPEB,
.dev = {
.platform_data = fsg_plat_eth,
},
.num_resources = ARRAY_SIZE(fsg_eth_npeb_resources),
.resource = fsg_eth_npeb_resources,
}, {
.name = "ixp4xx_eth",
.id = IXP4XX_ETH_NPEC,
.dev = {
.platform_data = fsg_plat_eth + 1,
},
.num_resources = ARRAY_SIZE(fsg_eth_npec_resources),
.resource = fsg_eth_npec_resources,
}
};
static struct platform_device *fsg_devices[] __initdata = {
&fsg_i2c_gpio,
&fsg_flash,
&fsg_leds,
&fsg_eth[0],
&fsg_eth[1],
};
static irqreturn_t fsg_power_handler(int irq, void *dev_id)
{
/* Signal init to do the ctrlaltdel action, this will bypass init if
* it hasn't started and do a kernel_restart.
*/
ctrl_alt_del();
return IRQ_HANDLED;
}
static irqreturn_t fsg_reset_handler(int irq, void *dev_id)
{
/* This is the paper-clip reset which does an emergency reboot. */
printk(KERN_INFO "Restarting system.\n");
machine_restart(NULL);
/* This should never be reached. */
return IRQ_HANDLED;
}
static void __init fsg_init(void)
{
uint8_t __iomem *f;
ixp4xx_sys_init();
fsg_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
fsg_flash_resource.end =
IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
*IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
*IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
/* Configure CS2 for operation, 8bit and writable */
*IXP4XX_EXP_CS2 = 0xbfff0002;
gpiod_add_lookup_table(&fsg_i2c_gpiod_table);
i2c_register_board_info(0, fsg_i2c_board_info,
ARRAY_SIZE(fsg_i2c_board_info));
/* This is only useful on a modified machine, but it is valuable
* to have it first in order to see debug messages, and so that
* it does *not* get removed if platform_add_devices fails!
*/
(void)platform_device_register(&fsg_uart);
platform_add_devices(fsg_devices, ARRAY_SIZE(fsg_devices));
if (request_irq(gpio_to_irq(FSG_RB_GPIO), &fsg_reset_handler,
IRQF_TRIGGER_LOW, "FSG reset button", NULL) < 0) {
printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
gpio_to_irq(FSG_RB_GPIO));
}
if (request_irq(gpio_to_irq(FSG_SB_GPIO), &fsg_power_handler,
IRQF_TRIGGER_LOW, "FSG power button", NULL) < 0) {
printk(KERN_DEBUG "Power Button IRQ %d not available\n",
gpio_to_irq(FSG_SB_GPIO));
}
/*
* Map in a portion of the flash and read the MAC addresses.
* Since it is stored in BE in the flash itself, we need to
* byteswap it if we're in LE mode.
*/
f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x400000);
if (f) {
#ifdef __ARMEB__
int i;
for (i = 0; i < 6; i++) {
fsg_plat_eth[0].hwaddr[i] = readb(f + 0x3C0422 + i);
fsg_plat_eth[1].hwaddr[i] = readb(f + 0x3C043B + i);
}
#else
/*
Endian-swapped reads from unaligned addresses are
required to extract the two MACs from the big-endian
Redboot config area in flash.
*/
fsg_plat_eth[0].hwaddr[0] = readb(f + 0x3C0421);
fsg_plat_eth[0].hwaddr[1] = readb(f + 0x3C0420);
fsg_plat_eth[0].hwaddr[2] = readb(f + 0x3C0427);
fsg_plat_eth[0].hwaddr[3] = readb(f + 0x3C0426);
fsg_plat_eth[0].hwaddr[4] = readb(f + 0x3C0425);
fsg_plat_eth[0].hwaddr[5] = readb(f + 0x3C0424);
fsg_plat_eth[1].hwaddr[0] = readb(f + 0x3C0439);
fsg_plat_eth[1].hwaddr[1] = readb(f + 0x3C043F);
fsg_plat_eth[1].hwaddr[2] = readb(f + 0x3C043E);
fsg_plat_eth[1].hwaddr[3] = readb(f + 0x3C043D);
fsg_plat_eth[1].hwaddr[4] = readb(f + 0x3C043C);
fsg_plat_eth[1].hwaddr[5] = readb(f + 0x3C0443);
#endif
iounmap(f);
}
printk(KERN_INFO "FSG: Using MAC address %pM for port 0\n",
fsg_plat_eth[0].hwaddr);
printk(KERN_INFO "FSG: Using MAC address %pM for port 1\n",
fsg_plat_eth[1].hwaddr);
}
MACHINE_START(FSG, "Freecom FSG-3")
/* Maintainer: www.nslu2-linux.org */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.init_time = ixp4xx_timer_init,
.atag_offset = 0x100,
.init_machine = fsg_init,
#if defined(CONFIG_PCI)
.dma_zone_size = SZ_64M,
#endif
.restart = ixp4xx_restart,
MACHINE_END

72
arch/arm/mach-ixp4xx/gtwx5715-pci.c
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@ -1,72 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* arch/arm/mach-ixp4xx/gtwx5715-pci.c
*
* Gemtek GTWX5715 (Linksys WRV54G) board setup
*
* Copyright (C) 2004 George T. Joseph
* Derived from Coyote
*/
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <asm/mach/pci.h>
#include "irqs.h"
#define SLOT0_DEVID 0
#define SLOT1_DEVID 1
#define INTA 10 /* slot 1 has INTA and INTB crossed */
#define INTB 11
/*
* Slot 0 isn't actually populated with a card connector but
* we initialize it anyway in case a future version has the
* slot populated or someone with good soldering skills has
* some free time.
*/
void __init gtwx5715_pci_preinit(void)
{
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init gtwx5715_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int rc = -1;
if ((slot == SLOT0_DEVID && pin == 1) ||
(slot == SLOT1_DEVID && pin == 2))
rc = IXP4XX_GPIO_IRQ(INTA);
else if ((slot == SLOT0_DEVID && pin == 2) ||
(slot == SLOT1_DEVID && pin == 1))
rc = IXP4XX_GPIO_IRQ(INTB);
printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n",
__func__, slot, pin, rc);
return rc;
}
struct hw_pci gtwx5715_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = gtwx5715_pci_preinit,
.setup = ixp4xx_setup,
.map_irq = gtwx5715_map_irq,
};
int __init gtwx5715_pci_init(void)
{
if (machine_is_gtwx5715())
pci_common_init(&gtwx5715_pci);
return 0;
}
subsys_initcall(gtwx5715_pci_init);

167
arch/arm/mach-ixp4xx/gtwx5715-setup.c
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@ -1,167 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* arch/arm/mach-ixp4xx/gtwx5715-setup.c
*
* Gemtek GTWX5715 (Linksys WRV54G) board setup
*
* Copyright (C) 2004 George T. Joseph
* Derived from Coyote
*/
#include <linux/init.h>
#include <linux/device.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_8250.h>
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include "irqs.h"
/* GPIO 5,6,7 and 12 are hard wired to the Kendin KS8995M Switch
and operate as an SPI type interface. The details of the interface
are available on Kendin/Micrel's web site. */
#define GTWX5715_KSSPI_SELECT 5
#define GTWX5715_KSSPI_TXD 6
#define GTWX5715_KSSPI_CLOCK 7
#define GTWX5715_KSSPI_RXD 12
/* The "reset" button is wired to GPIO 3.
The GPIO is brought "low" when the button is pushed. */
#define GTWX5715_BUTTON_GPIO 3
/* Board Label Front Label
LED1 Power
LED2 Wireless-G
LED3 not populated but could be
LED4 Internet
LED5 - LED8 Controlled by KS8995M Switch
LED9 DMZ */
#define GTWX5715_LED1_GPIO 2
#define GTWX5715_LED2_GPIO 9
#define GTWX5715_LED3_GPIO 8
#define GTWX5715_LED4_GPIO 1
#define GTWX5715_LED9_GPIO 4
/*
* Xscale UART registers are 32 bits wide with only the least
* significant 8 bits having any meaning. From a configuration
* perspective, this means 2 things...
*
* Setting .regshift = 2 so that the standard 16550 registers
* line up on every 4th byte.
*
* Shifting the register start virtual address +3 bytes when
* compiled big-endian. Since register writes are done on a
* single byte basis, if the shift isn't done the driver will
* write the value into the most significant byte of the register,
* which is ignored, instead of the least significant.
*/
#ifdef __ARMEB__
#define REG_OFFSET 3
#else
#define REG_OFFSET 0
#endif
/*
* Only the second or "console" uart is connected on the gtwx5715.
*/
static struct resource gtwx5715_uart_resources[] = {
{
.start = IXP4XX_UART2_BASE_PHYS,
.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_IXP4XX_UART2,
.end = IRQ_IXP4XX_UART2,
.flags = IORESOURCE_IRQ,
},
{ },
};
static struct plat_serial8250_port gtwx5715_uart_platform_data[] = {
{
.mapbase = IXP4XX_UART2_BASE_PHYS,
.membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART2,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
{ },
};
static struct platform_device gtwx5715_uart_device = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = gtwx5715_uart_platform_data,
},
.num_resources = 2,
.resource = gtwx5715_uart_resources,
};
static struct flash_platform_data gtwx5715_flash_data = {
.map_name = "cfi_probe",
.width = 2,
};
static struct resource gtwx5715_flash_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device gtwx5715_flash = {
.name = "IXP4XX-Flash",
.id = 0,
.dev = {
.platform_data = &gtwx5715_flash_data,
},
.num_resources = 1,
.resource = &gtwx5715_flash_resource,
};
static struct platform_device *gtwx5715_devices[] __initdata = {
&gtwx5715_uart_device,
&gtwx5715_flash,
};
static void __init gtwx5715_init(void)
{
ixp4xx_sys_init();
gtwx5715_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
gtwx5715_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_8M - 1;
platform_add_devices(gtwx5715_devices, ARRAY_SIZE(gtwx5715_devices));
}
MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)")
/* Maintainer: George Joseph */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.init_time = ixp4xx_timer_init,
.atag_offset = 0x100,
.init_machine = gtwx5715_init,
#if defined(CONFIG_PCI)
.dma_zone_size = SZ_64M,
#endif
.restart = ixp4xx_restart,
MACHINE_END

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arch/arm/mach-ixp4xx/ixdp425-pci.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-ixp4xx/ixdp425-pci.c
*
* IXDP425 board-level PCI initialization
*
* Copyright (C) 2002 Intel Corporation.
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*
* Maintainer: Deepak Saxena <dsaxena@plexity.net>
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <asm/mach/pci.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include "irqs.h"
#define MAX_DEV 4
#define IRQ_LINES 4
/* PCI controller GPIO to IRQ pin mappings */
#define INTA 11
#define INTB 10
#define INTC 9
#define INTD 8
void __init ixdp425_pci_preinit(void)
{
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init ixdp425_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[IRQ_LINES] = {
IXP4XX_GPIO_IRQ(INTA),
IXP4XX_GPIO_IRQ(INTB),
IXP4XX_GPIO_IRQ(INTC),
IXP4XX_GPIO_IRQ(INTD)
};
if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
return pci_irq_table[(slot + pin - 2) % 4];
return -1;
}
struct hw_pci ixdp425_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = ixdp425_pci_preinit,
.setup = ixp4xx_setup,
.map_irq = ixdp425_map_irq,
};
int __init ixdp425_pci_init(void)
{
if (machine_is_ixdp425() || machine_is_ixcdp1100() ||
machine_is_ixdp465() || machine_is_kixrp435())
pci_common_init(&ixdp425_pci);
return 0;
}
subsys_initcall(ixdp425_pci_init);

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arch/arm/mach-ixp4xx/ixdp425-setup.c
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// SPDX-License-Identifier: GPL-2.0
/*
* arch/arm/mach-ixp4xx/ixdp425-setup.c
*
* IXDP425/IXCDP1100 board-setup
*
* Copyright (C) 2003-2005 MontaVista Software, Inc.
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_8250.h>
#include <linux/gpio/machine.h>
#include <linux/io.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/platnand.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include "irqs.h"
#define IXDP425_SDA_PIN 7
#define IXDP425_SCL_PIN 6
/* NAND Flash pins */
#define IXDP425_NAND_NCE_PIN 12
#define IXDP425_NAND_CMD_BYTE 0x01
#define IXDP425_NAND_ADDR_BYTE 0x02
static struct flash_platform_data ixdp425_flash_data = {
.map_name = "cfi_probe",
.width = 2,
};
static struct resource ixdp425_flash_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device ixdp425_flash = {
.name = "IXP4XX-Flash",
.id = 0,
.dev = {
.platform_data = &ixdp425_flash_data,
},
.num_resources = 1,
.resource = &ixdp425_flash_resource,
};
#if defined(CONFIG_MTD_NAND_PLATFORM) || \
defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
static struct mtd_partition ixdp425_partitions[] = {
{
.name = "ixp400 NAND FS 0",
.offset = 0,
.size = SZ_8M
}, {
.name = "ixp400 NAND FS 1",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL
},
};
static void
ixdp425_flash_nand_cmd_ctrl(struct nand_chip *this, int cmd, unsigned int ctrl)
{
int offset = (int)nand_get_controller_data(this);
if (ctrl & NAND_CTRL_CHANGE) {
if (ctrl & NAND_NCE) {
gpio_set_value(IXDP425_NAND_NCE_PIN, 0);
udelay(5);
} else
gpio_set_value(IXDP425_NAND_NCE_PIN, 1);
offset = (ctrl & NAND_CLE) ? IXDP425_NAND_CMD_BYTE : 0;
offset |= (ctrl & NAND_ALE) ? IXDP425_NAND_ADDR_BYTE : 0;
nand_set_controller_data(this, (void *)offset);
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->legacy.IO_ADDR_W + offset);
}
static struct platform_nand_data ixdp425_flash_nand_data = {
.chip = {
.nr_chips = 1,
.chip_delay = 30,
.partitions = ixdp425_partitions,
.nr_partitions = ARRAY_SIZE(ixdp425_partitions),
},
.ctrl = {
.cmd_ctrl = ixdp425_flash_nand_cmd_ctrl
}
};
static struct resource ixdp425_flash_nand_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device ixdp425_flash_nand = {
.name = "gen_nand",
.id = -1,
.dev = {
.platform_data = &ixdp425_flash_nand_data,
},
.num_resources = 1,
.resource = &ixdp425_flash_nand_resource,
};
#endif /* CONFIG_MTD_NAND_PLATFORM */
static struct gpiod_lookup_table ixdp425_i2c_gpiod_table = {
.dev_id = "i2c-gpio.0",
.table = {
GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", IXDP425_SDA_PIN,
NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", IXDP425_SCL_PIN,
NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
},
};
static struct platform_device ixdp425_i2c_gpio = {
.name = "i2c-gpio",
.id = 0,
.dev = {
.platform_data = NULL,
},
};
static struct resource ixdp425_uart_resources[] = {
{
.start = IXP4XX_UART1_BASE_PHYS,
.end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM
},
{
.start = IXP4XX_UART2_BASE_PHYS,
.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM
}
};
static struct plat_serial8250_port ixdp425_uart_data[] = {
{
.mapbase = IXP4XX_UART1_BASE_PHYS,
.membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART1,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
{
.mapbase = IXP4XX_UART2_BASE_PHYS,
.membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART2,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
{ },
};
static struct platform_device ixdp425_uart = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev.platform_data = ixdp425_uart_data,
.num_resources = 2,
.resource = ixdp425_uart_resources
};
/* Built-in 10/100 Ethernet MAC interfaces */
static struct resource ixp425_npeb_resources[] = {
{
.start = IXP4XX_EthB_BASE_PHYS,
.end = IXP4XX_EthB_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
};
static struct resource ixp425_npec_resources[] = {
{
.start = IXP4XX_EthC_BASE_PHYS,
.end = IXP4XX_EthC_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
};
static struct eth_plat_info ixdp425_plat_eth[] = {
{
.phy = 0,
.rxq = 3,
.txreadyq = 20,
}, {
.phy = 1,
.rxq = 4,
.txreadyq = 21,
}
};
static struct platform_device ixdp425_eth[] = {
{
.name = "ixp4xx_eth",
.id = IXP4XX_ETH_NPEB,
.dev.platform_data = ixdp425_plat_eth,
.num_resources = ARRAY_SIZE(ixp425_npeb_resources),
.resource = ixp425_npeb_resources,
}, {
.name = "ixp4xx_eth",
.id = IXP4XX_ETH_NPEC,
.dev.platform_data = ixdp425_plat_eth + 1,
.num_resources = ARRAY_SIZE(ixp425_npec_resources),
.resource = ixp425_npec_resources,
}
};
static struct platform_device *ixdp425_devices[] __initdata = {
&ixdp425_i2c_gpio,
&ixdp425_flash,
#if defined(CONFIG_MTD_NAND_PLATFORM) || \
defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
&ixdp425_flash_nand,
#endif
&ixdp425_uart,
&ixdp425_eth[0],
&ixdp425_eth[1],
};
static void __init ixdp425_init(void)
{
ixp4xx_sys_init();
ixdp425_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
ixdp425_flash_resource.end =
IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
#if defined(CONFIG_MTD_NAND_PLATFORM) || \
defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
ixdp425_flash_nand_resource.start = IXP4XX_EXP_BUS_BASE(3),
ixdp425_flash_nand_resource.end = IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1;
gpio_request(IXDP425_NAND_NCE_PIN, "NAND NCE pin");
gpio_direction_output(IXDP425_NAND_NCE_PIN, 0);
/* Configure expansion bus for NAND Flash */
*IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN |
IXP4XX_EXP_BUS_STROBE_T(1) | /* extend by 1 clock */
IXP4XX_EXP_BUS_CYCLES(0) | /* Intel cycles */
IXP4XX_EXP_BUS_SIZE(0) | /* 512bytes addr space*/
IXP4XX_EXP_BUS_WR_EN |
IXP4XX_EXP_BUS_BYTE_EN; /* 8 bit data bus */
#endif
if (cpu_is_ixp43x()) {
ixdp425_uart.num_resources = 1;
ixdp425_uart_data[1].flags = 0;
}
gpiod_add_lookup_table(&ixdp425_i2c_gpiod_table);
platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices));
}
#ifdef CONFIG_ARCH_IXDP425
MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
/* Maintainer: MontaVista Software, Inc. */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.init_time = ixp4xx_timer_init,
.atag_offset = 0x100,
.init_machine = ixdp425_init,
#if defined(CONFIG_PCI)
.dma_zone_size = SZ_64M,
#endif
.restart = ixp4xx_restart,
MACHINE_END
#endif
#ifdef CONFIG_MACH_IXDP465
MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
/* Maintainer: MontaVista Software, Inc. */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.init_time = ixp4xx_timer_init,
.atag_offset = 0x100,
.init_machine = ixdp425_init,
#if defined(CONFIG_PCI)
.dma_zone_size = SZ_64M,
#endif
MACHINE_END
#endif
#ifdef CONFIG_ARCH_PRPMC1100
MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
/* Maintainer: MontaVista Software, Inc. */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.init_time = ixp4xx_timer_init,
.atag_offset = 0x100,
.init_machine = ixdp425_init,
#if defined(CONFIG_PCI)
.dma_zone_size = SZ_64M,
#endif
MACHINE_END
#endif
#ifdef CONFIG_MACH_KIXRP435
MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
/* Maintainer: MontaVista Software, Inc. */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.init_time = ixp4xx_timer_init,
.atag_offset = 0x100,
.init_machine = ixdp425_init,
#if defined(CONFIG_PCI)
.dma_zone_size = SZ_64M,
#endif
MACHINE_END
#endif

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arch/arm/mach-ixp4xx/ixdpg425-pci.c
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@ -1,56 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-ixp4xx/ixdpg425-pci.c
*
* PCI setup routines for Intel IXDPG425 Platform
*
* Copyright (C) 2004 MontaVista Softwrae, Inc.
*
* Maintainer: Deepak Saxena <dsaxena@plexity.net>
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <asm/mach/pci.h>
#include "irqs.h"
void __init ixdpg425_pci_preinit(void)
{
irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init ixdpg425_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
if (slot == 12 || slot == 13)
return IRQ_IXP4XX_GPIO7;
else if (slot == 14)
return IRQ_IXP4XX_GPIO6;
else return -1;
}
struct hw_pci ixdpg425_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = ixdpg425_pci_preinit,
.setup = ixp4xx_setup,
.map_irq = ixdpg425_map_irq,
};
int __init ixdpg425_pci_init(void)
{
if (machine_is_ixdpg425())
pci_common_init(&ixdpg425_pci);
return 0;
}
subsys_initcall(ixdpg425_pci_init);

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arch/arm/mach-ixp4xx/miccpt-pci.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-ixp4xx/miccpt-pci.c
*
* MICCPT board-level PCI initialization
*
* Copyright (C) 2002 Intel Corporation.
* Copyright (C) 2003-2004 MontaVista Software, Inc.
* Copyright (C) 2006 OMICRON electronics GmbH
*
* Author: Michael Jochum <michael.jochum@omicron.at>
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <asm/mach/pci.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include "irqs.h"
#define MAX_DEV 4
#define IRQ_LINES 4
/* PCI controller GPIO to IRQ pin mappings */
#define INTA 1
#define INTB 2
#define INTC 3
#define INTD 4
void __init miccpt_pci_preinit(void)
{
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init miccpt_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[IRQ_LINES] = {
IXP4XX_GPIO_IRQ(INTA),
IXP4XX_GPIO_IRQ(INTB),
IXP4XX_GPIO_IRQ(INTC),
IXP4XX_GPIO_IRQ(INTD)
};
if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
return pci_irq_table[(slot + pin - 2) % 4];
return -1;
}
struct hw_pci miccpt_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = miccpt_pci_preinit,
.setup = ixp4xx_setup,
.map_irq = miccpt_map_irq,
};
int __init miccpt_pci_init(void)
{
if (machine_is_miccpt())
pci_common_init(&miccpt_pci);
return 0;
}
subsys_initcall(miccpt_pci_init);

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// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-ixp4xx/nas100d-pci.c
*
* NAS 100d board-level PCI initialization
*
* based on ixdp425-pci.c:
* Copyright (C) 2002 Intel Corporation.
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*
* Maintainer: http://www.nslu2-linux.org/
*/
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
#include "irqs.h"
#define MAX_DEV 3
#define IRQ_LINES 3
/* PCI controller GPIO to IRQ pin mappings */
#define INTA 11
#define INTB 10
#define INTC 9
#define INTD 8
#define INTE 7
void __init nas100d_pci_preinit(void)
{
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init nas100d_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[MAX_DEV][IRQ_LINES] = {
{ IXP4XX_GPIO_IRQ(INTA), -1, -1 },
{ IXP4XX_GPIO_IRQ(INTB), -1, -1 },
{ IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD),
IXP4XX_GPIO_IRQ(INTE) },
};
if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
return pci_irq_table[slot - 1][pin - 1];
return -1;
}
struct hw_pci __initdata nas100d_pci = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = nas100d_pci_preinit,
.setup = ixp4xx_setup,
.map_irq = nas100d_map_irq,
};
int __init nas100d_pci_init(void)
{
if (machine_is_nas100d())
pci_common_init(&nas100d_pci);
return 0;
}
subsys_initcall(nas100d_pci_init);

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arch/arm/mach-ixp4xx/nas100d-setup.c
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// SPDX-License-Identifier: GPL-2.0
/*
* arch/arm/mach-ixp4xx/nas100d-setup.c
*
* NAS 100d board-setup
*
* Copyright (C) 2008 Rod Whitby <rod@whitby.id.au>
*
* based on ixdp425-setup.c:
* Copyright (C) 2003-2004 MontaVista Software, Inc.
* based on nas100d-power.c:
* Copyright (C) 2005 Tower Technologies
* based on nas100d-io.c
* Copyright (C) 2004 Karen Spearel
*
* Author: Alessandro Zummo <a.zummo@towertech.it>
* Author: Rod Whitby <rod@whitby.id.au>
* Maintainers: http://www.nslu2-linux.org/
*
*/
#include <linux/gpio.h>
#include <linux/if_ether.h>
#include <linux/irq.h>
#include <linux/jiffies.h>
#include <linux/timer.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
#include <linux/leds.h>
#include <linux/reboot.h>
#include <linux/i2c.h>
#include <linux/gpio/machine.h>
#include <linux/io.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <mach/hardware.h>
#include "irqs.h"
#define NAS100D_SDA_PIN 5
#define NAS100D_SCL_PIN 6
/* Buttons */
#define NAS100D_PB_GPIO 14 /* power button */
#define NAS100D_RB_GPIO 4 /* reset button */
/* Power control */
#define NAS100D_PO_GPIO 12 /* power off */
/* LEDs */
#define NAS100D_LED_WLAN_GPIO 0
#define NAS100D_LED_DISK_GPIO 3
#define NAS100D_LED_PWR_GPIO 15
static struct flash_platform_data nas100d_flash_data = {
.map_name = "cfi_probe",
.width = 2,
};
static struct resource nas100d_flash_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device nas100d_flash = {
.name = "IXP4XX-Flash",
.id = 0,
.dev.platform_data = &nas100d_flash_data,
.num_resources = 1,
.resource = &nas100d_flash_resource,
};
static struct i2c_board_info __initdata nas100d_i2c_board_info [] = {
{
I2C_BOARD_INFO("pcf8563", 0x51),
},
};
static struct gpio_led nas100d_led_pins[] = {
{
.name = "nas100d:green:wlan",
.gpio = NAS100D_LED_WLAN_GPIO,
.active_low = true,
},
{
.name = "nas100d:blue:power", /* (off=flashing) */
.gpio = NAS100D_LED_PWR_GPIO,
.active_low = true,
},
{
.name = "nas100d:yellow:disk",
.gpio = NAS100D_LED_DISK_GPIO,
.active_low = true,
},
};
static struct gpio_led_platform_data nas100d_led_data = {
.num_leds = ARRAY_SIZE(nas100d_led_pins),
.leds = nas100d_led_pins,
};
static struct platform_device nas100d_leds = {
.name = "leds-gpio",
.id = -1,
.dev.platform_data = &nas100d_led_data,
};
static struct gpiod_lookup_table nas100d_i2c_gpiod_table = {
.dev_id = "i2c-gpio.0",
.table = {
GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", NAS100D_SDA_PIN,
NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", NAS100D_SCL_PIN,
NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
},
};
static struct platform_device nas100d_i2c_gpio = {
.name = "i2c-gpio",
.id = 0,
.dev = {
.platform_data = NULL,
},
};
static struct resource nas100d_uart_resources[] = {
{
.start = IXP4XX_UART1_BASE_PHYS,
.end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
{
.start = IXP4XX_UART2_BASE_PHYS,
.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
}
};
static struct plat_serial8250_port nas100d_uart_data[] = {
{
.mapbase = IXP4XX_UART1_BASE_PHYS,
.membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART1,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
{
.mapbase = IXP4XX_UART2_BASE_PHYS,
.membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART2,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
{ }
};
static struct platform_device nas100d_uart = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev.platform_data = nas100d_uart_data,
.num_resources = 2,
.resource = nas100d_uart_resources,
};
/* Built-in 10/100 Ethernet MAC interfaces */
static struct resource nas100d_eth_resources[] = {
{
.start = IXP4XX_EthB_BASE_PHYS,
.end = IXP4XX_EthB_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
};
static struct eth_plat_info nas100d_plat_eth[] = {
{
.phy = 0,
.rxq = 3,
.txreadyq = 20,
}
};
static struct platform_device nas100d_eth[] = {
{
.name = "ixp4xx_eth",
.id = IXP4XX_ETH_NPEB,
.dev.platform_data = nas100d_plat_eth,
.num_resources = ARRAY_SIZE(nas100d_eth_resources),
.resource = nas100d_eth_resources,
}
};
static struct platform_device *nas100d_devices[] __initdata = {
&nas100d_i2c_gpio,
&nas100d_flash,
&nas100d_leds,
&nas100d_eth[0],
};
static void nas100d_power_off(void)
{
/* This causes the box to drop the power and go dead. */
/* enable the pwr cntl gpio and assert power off */
gpio_direction_output(NAS100D_PO_GPIO, 1);
}
/* This is used to make sure the power-button pusher is serious. The button
* must be held until the value of this counter reaches zero.
*/
static int power_button_countdown;
/* Must hold the button down for at least this many counts to be processed */
#define PBUTTON_HOLDDOWN_COUNT 4 /* 2 secs */
static void nas100d_power_handler(struct timer_list *unused);
static DEFINE_TIMER(nas100d_power_timer, nas100d_power_handler);
static void nas100d_power_handler(struct timer_list *unused)
{
/* This routine is called twice per second to check the
* state of the power button.
*/
if (gpio_get_value(NAS100D_PB_GPIO)) {
/* IO Pin is 1 (button pushed) */
if (power_button_countdown > 0)
power_button_countdown--;
} else {
/* Done on button release, to allow for auto-power-on mods. */
if (power_button_countdown == 0) {
/* Signal init to do the ctrlaltdel action,
* this will bypass init if it hasn't started
* and do a kernel_restart.
*/
ctrl_alt_del();
/* Change the state of the power LED to "blink" */
gpio_set_value(NAS100D_LED_PWR_GPIO, 0);
} else {
power_button_countdown = PBUTTON_HOLDDOWN_COUNT;
}
}
mod_timer(&nas100d_power_timer, jiffies + msecs_to_jiffies(500));
}
static irqreturn_t nas100d_reset_handler(int irq, void *dev_id)
{
/* This is the paper-clip reset, it shuts the machine down directly. */
machine_power_off();
return IRQ_HANDLED;
}
static int __init nas100d_gpio_init(void)
{
if (!machine_is_nas100d())
return 0;
/*
* The power button on the Iomega NAS100d is on GPIO 14, but
* it cannot handle interrupts on that GPIO line. So we'll
* have to poll it with a kernel timer.
*/
/* Request the power off GPIO */
gpio_request(NAS100D_PO_GPIO, "power off");
/* Make sure that the power button GPIO is set up as an input */
gpio_request(NAS100D_PB_GPIO, "power button");
gpio_direction_input(NAS100D_PB_GPIO);
/* Set the initial value for the power button IRQ handler */
power_button_countdown = PBUTTON_HOLDDOWN_COUNT;
mod_timer(&nas100d_power_timer, jiffies + msecs_to_jiffies(500));
return 0;
}
device_initcall(nas100d_gpio_init);
static void __init nas100d_init(void)
{
uint8_t __iomem *f;
int i;
ixp4xx_sys_init();
nas100d_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
nas100d_flash_resource.end =
IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
gpiod_add_lookup_table(&nas100d_i2c_gpiod_table);
i2c_register_board_info(0, nas100d_i2c_board_info,
ARRAY_SIZE(nas100d_i2c_board_info));
/*
* This is only useful on a modified machine, but it is valuable
* to have it first in order to see debug messages, and so that
* it does *not* get removed if platform_add_devices fails!
*/
(void)platform_device_register(&nas100d_uart);
platform_add_devices(nas100d_devices, ARRAY_SIZE(nas100d_devices));
pm_power_off = nas100d_power_off;
if (request_irq(gpio_to_irq(NAS100D_RB_GPIO), &nas100d_reset_handler,
IRQF_TRIGGER_LOW, "NAS100D reset button", NULL) < 0) {
printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
gpio_to_irq(NAS100D_RB_GPIO));
}
/*
* Map in a portion of the flash and read the MAC address.
* Since it is stored in BE in the flash itself, we need to
* byteswap it if we're in LE mode.
*/
f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x1000000);
if (f) {
for (i = 0; i < 6; i++)
#ifdef __ARMEB__
nas100d_plat_eth[0].hwaddr[i] = readb(f + 0xFC0FD8 + i);
#else
nas100d_plat_eth[0].hwaddr[i] = readb(f + 0xFC0FD8 + (i^3));
#endif
iounmap(f);
}
printk(KERN_INFO "NAS100D: Using MAC address %pM for port 0\n",
nas100d_plat_eth[0].hwaddr);
}
MACHINE_START(NAS100D, "Iomega NAS 100d")
/* Maintainer: www.nslu2-linux.org */
.atag_offset = 0x100,
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.init_time = ixp4xx_timer_init,
.init_machine = nas100d_init,
#if defined(CONFIG_PCI)
.dma_zone_size = SZ_64M,
#endif
.restart = ixp4xx_restart,
MACHINE_END

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// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-ixp4xx/nslu2-pci.c
*
* NSLU2 board-level PCI initialization
*
* based on ixdp425-pci.c:
* Copyright (C) 2002 Intel Corporation.
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*
* Maintainer: http://www.nslu2-linux.org/
*/
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
#include "irqs.h"
#define MAX_DEV 3
#define IRQ_LINES 3
/* PCI controller GPIO to IRQ pin mappings */
#define INTA 11
#define INTB 10
#define INTC 9
#define INTD 8
void __init nslu2_pci_preinit(void)
{
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init nslu2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[IRQ_LINES] = {
IXP4XX_GPIO_IRQ(INTA),
IXP4XX_GPIO_IRQ(INTB),
IXP4XX_GPIO_IRQ(INTC),
};
if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
return pci_irq_table[(slot + pin - 2) % IRQ_LINES];
return -1;
}
struct hw_pci __initdata nslu2_pci = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = nslu2_pci_preinit,
.setup = ixp4xx_setup,
.map_irq = nslu2_map_irq,
};
int __init nslu2_pci_init(void) /* monkey see, monkey do */
{
if (machine_is_nslu2())
pci_common_init(&nslu2_pci);
return 0;
}
subsys_initcall(nslu2_pci_init);

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// SPDX-License-Identifier: GPL-2.0
/*
* arch/arm/mach-ixp4xx/nslu2-setup.c
*
* NSLU2 board-setup
*
* Copyright (C) 2008 Rod Whitby <rod@whitby.id.au>
*
* based on ixdp425-setup.c:
* Copyright (C) 2003-2004 MontaVista Software, Inc.
* based on nslu2-power.c:
* Copyright (C) 2005 Tower Technologies
*
* Author: Mark Rakes <mrakes at mac.com>
* Author: Rod Whitby <rod@whitby.id.au>
* Author: Alessandro Zummo <a.zummo@towertech.it>
* Maintainers: http://www.nslu2-linux.org/
*
*/
#include <linux/gpio.h>
#include <linux/if_ether.h>
#include <linux/irq.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
#include <linux/leds.h>
#include <linux/reboot.h>
#include <linux/i2c.h>
#include <linux/gpio/machine.h>
#include <linux/io.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/time.h>
#include <mach/hardware.h>
#include "irqs.h"
#define NSLU2_SDA_PIN 7
#define NSLU2_SCL_PIN 6
/* NSLU2 Timer */
#define NSLU2_FREQ 66000000
/* Buttons */
#define NSLU2_PB_GPIO 5 /* power button */
#define NSLU2_PO_GPIO 8 /* power off */
#define NSLU2_RB_GPIO 12 /* reset button */
/* Buzzer */
#define NSLU2_GPIO_BUZZ 4
/* LEDs */
#define NSLU2_LED_RED_GPIO 0
#define NSLU2_LED_GRN_GPIO 1
#define NSLU2_LED_DISK1_GPIO 3
#define NSLU2_LED_DISK2_GPIO 2
static struct flash_platform_data nslu2_flash_data = {
.map_name = "cfi_probe",
.width = 2,
};
static struct resource nslu2_flash_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device nslu2_flash = {
.name = "IXP4XX-Flash",
.id = 0,
.dev.platform_data = &nslu2_flash_data,
.num_resources = 1,
.resource = &nslu2_flash_resource,
};
static struct gpiod_lookup_table nslu2_i2c_gpiod_table = {
.dev_id = "i2c-gpio.0",
.table = {
GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", NSLU2_SDA_PIN,
NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", NSLU2_SCL_PIN,
NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
},
};
static struct i2c_board_info __initdata nslu2_i2c_board_info [] = {
{
I2C_BOARD_INFO("x1205", 0x6f),
},
};
static struct gpio_led nslu2_led_pins[] = {
{
.name = "nslu2:green:ready",
.gpio = NSLU2_LED_GRN_GPIO,
},
{
.name = "nslu2:red:status",
.gpio = NSLU2_LED_RED_GPIO,
},
{
.name = "nslu2:green:disk-1",
.gpio = NSLU2_LED_DISK1_GPIO,
.active_low = true,
},
{
.name = "nslu2:green:disk-2",
.gpio = NSLU2_LED_DISK2_GPIO,
.active_low = true,
},
};
static struct gpio_led_platform_data nslu2_led_data = {
.num_leds = ARRAY_SIZE(nslu2_led_pins),
.leds = nslu2_led_pins,
};
static struct platform_device nslu2_leds = {
.name = "leds-gpio",
.id = -1,
.dev.platform_data = &nslu2_led_data,
};
static struct platform_device nslu2_i2c_gpio = {
.name = "i2c-gpio",
.id = 0,
.dev = {
.platform_data = NULL,
},
};
static struct resource nslu2_beeper_resources[] = {
{
.start = IRQ_IXP4XX_TIMER2,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device nslu2_beeper = {
.name = "ixp4xx-beeper",
.id = NSLU2_GPIO_BUZZ,
.resource = nslu2_beeper_resources,
.num_resources = ARRAY_SIZE(nslu2_beeper_resources),
};
static struct resource nslu2_uart_resources[] = {
{
.start = IXP4XX_UART1_BASE_PHYS,
.end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
{
.start = IXP4XX_UART2_BASE_PHYS,
.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
}
};
static struct plat_serial8250_port nslu2_uart_data[] = {
{
.mapbase = IXP4XX_UART1_BASE_PHYS,
.membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART1,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
{
.mapbase = IXP4XX_UART2_BASE_PHYS,
.membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART2,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
{ }
};
static struct platform_device nslu2_uart = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev.platform_data = nslu2_uart_data,
.num_resources = 2,
.resource = nslu2_uart_resources,
};
/* Built-in 10/100 Ethernet MAC interfaces */
static struct resource nslu2_eth_resources[] = {
{
.start = IXP4XX_EthB_BASE_PHYS,
.end = IXP4XX_EthB_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
};
static struct eth_plat_info nslu2_plat_eth[] = {
{
.phy = 1,
.rxq = 3,
.txreadyq = 20,
}
};
static struct platform_device nslu2_eth[] = {
{
.name = "ixp4xx_eth",
.id = IXP4XX_ETH_NPEB,
.dev.platform_data = nslu2_plat_eth,
.num_resources = ARRAY_SIZE(nslu2_eth_resources),
.resource = nslu2_eth_resources,
}
};
static struct platform_device *nslu2_devices[] __initdata = {
&nslu2_i2c_gpio,
&nslu2_flash,
&nslu2_beeper,
&nslu2_leds,
&nslu2_eth[0],
};
static void nslu2_power_off(void)
{
/* This causes the box to drop the power and go dead. */
/* enable the pwr cntl gpio and assert power off */
gpio_direction_output(NSLU2_PO_GPIO, 1);
}
static irqreturn_t nslu2_power_handler(int irq, void *dev_id)
{
/* Signal init to do the ctrlaltdel action, this will bypass init if
* it hasn't started and do a kernel_restart.
*/
ctrl_alt_del();
return IRQ_HANDLED;
}
static irqreturn_t nslu2_reset_handler(int irq, void *dev_id)
{
/* This is the paper-clip reset, it shuts the machine down directly.
*/
machine_power_off();
return IRQ_HANDLED;
}
static int __init nslu2_gpio_init(void)
{
if (!machine_is_nslu2())
return 0;
/* Request the power off GPIO */
return gpio_request(NSLU2_PO_GPIO, "power off");
}
device_initcall(nslu2_gpio_init);
static void __init nslu2_timer_init(void)
{
/* The xtal on this machine is non-standard. */
ixp4xx_timer_freq = NSLU2_FREQ;
/* Call standard timer_init function. */
ixp4xx_timer_init();
}
static void __init nslu2_init(void)
{
uint8_t __iomem *f;
int i;
ixp4xx_sys_init();
nslu2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
nslu2_flash_resource.end =
IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
gpiod_add_lookup_table(&nslu2_i2c_gpiod_table);
i2c_register_board_info(0, nslu2_i2c_board_info,
ARRAY_SIZE(nslu2_i2c_board_info));
/*
* This is only useful on a modified machine, but it is valuable
* to have it first in order to see debug messages, and so that
* it does *not* get removed if platform_add_devices fails!
*/
(void)platform_device_register(&nslu2_uart);
platform_add_devices(nslu2_devices, ARRAY_SIZE(nslu2_devices));
pm_power_off = nslu2_power_off;
if (request_irq(gpio_to_irq(NSLU2_RB_GPIO), &nslu2_reset_handler,
IRQF_TRIGGER_LOW, "NSLU2 reset button", NULL) < 0) {
printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
gpio_to_irq(NSLU2_RB_GPIO));
}
if (request_irq(gpio_to_irq(NSLU2_PB_GPIO), &nslu2_power_handler,
IRQF_TRIGGER_HIGH, "NSLU2 power button", NULL) < 0) {
printk(KERN_DEBUG "Power Button IRQ %d not available\n",
gpio_to_irq(NSLU2_PB_GPIO));
}
/*
* Map in a portion of the flash and read the MAC address.
* Since it is stored in BE in the flash itself, we need to
* byteswap it if we're in LE mode.
*/
f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x40000);
if (f) {
for (i = 0; i < 6; i++)
#ifdef __ARMEB__
nslu2_plat_eth[0].hwaddr[i] = readb(f + 0x3FFB0 + i);
#else
nslu2_plat_eth[0].hwaddr[i] = readb(f + 0x3FFB0 + (i^3));
#endif
iounmap(f);
}
printk(KERN_INFO "NSLU2: Using MAC address %pM for port 0\n",
nslu2_plat_eth[0].hwaddr);
}
MACHINE_START(NSLU2, "Linksys NSLU2")
/* Maintainer: www.nslu2-linux.org */
.atag_offset = 0x100,
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.init_time = nslu2_timer_init,
.init_machine = nslu2_init,
#if defined(CONFIG_PCI)
.dma_zone_size = SZ_64M,
#endif
.restart = ixp4xx_restart,
MACHINE_END

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arch/arm/mach-ixp4xx/omixp-setup.c
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@ -1,298 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-ixp4xx/omixp-setup.c
*
* omicron ixp4xx board setup
* Copyright (C) 2009 OMICRON electronics GmbH
*
* based nslu2-setup.c, ixdp425-setup.c:
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*/
#include <linux/kernel.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/leds.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <mach/hardware.h>
#include "irqs.h"
static struct resource omixp_flash_resources[] = {
{
.flags = IORESOURCE_MEM,
}, {
.flags = IORESOURCE_MEM,
},
};
static struct mtd_partition omixp_partitions[] = {
{
.name = "Recovery Bootloader",
.size = 0x00020000,
.offset = 0,
}, {
.name = "Calibration Data",
.size = 0x00020000,
.offset = 0x00020000,
}, {
.name = "Recovery FPGA",
.size = 0x00020000,
.offset = 0x00040000,
}, {
.name = "Release Bootloader",
.size = 0x00020000,
.offset = 0x00060000,
}, {
.name = "Release FPGA",
.size = 0x00020000,
.offset = 0x00080000,
}, {
.name = "Kernel",
.size = 0x00160000,
.offset = 0x000a0000,
}, {
.name = "Filesystem",
.size = 0x00C00000,
.offset = 0x00200000,
}, {
.name = "Persistent Storage",
.size = 0x00200000,
.offset = 0x00E00000,
},
};
static struct flash_platform_data omixp_flash_data[] = {
{
.map_name = "cfi_probe",
.parts = omixp_partitions,
.nr_parts = ARRAY_SIZE(omixp_partitions),
}, {
.map_name = "cfi_probe",
.parts = NULL,
.nr_parts = 0,
},
};
static struct platform_device omixp_flash_device[] = {
{
.name = "IXP4XX-Flash",
.id = 0,
.dev = {
.platform_data = &omixp_flash_data[0],
},
.resource = &omixp_flash_resources[0],
.num_resources = 1,
}, {
.name = "IXP4XX-Flash",
.id = 1,
.dev = {
.platform_data = &omixp_flash_data[1],
},
.resource = &omixp_flash_resources[1],
.num_resources = 1,
},
};
/* Swap UART's - These boards have the console on UART2. The following
* configuration is used:
* ttyS0 .. UART2
* ttyS1 .. UART1
* This way standard images can be used with the kernel that expect
* the console on ttyS0.
*/
static struct resource omixp_uart_resources[] = {
{
.start = IXP4XX_UART2_BASE_PHYS,
.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
}, {
.start = IXP4XX_UART1_BASE_PHYS,
.end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
};
static struct plat_serial8250_port omixp_uart_data[] = {
{
.mapbase = IXP4XX_UART2_BASE_PHYS,
.membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART2,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
}, {
.mapbase = IXP4XX_UART1_BASE_PHYS,
.membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART1,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
}, {
/* list termination */
}
};
static struct platform_device omixp_uart = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev.platform_data = omixp_uart_data,
.num_resources = 2,
.resource = omixp_uart_resources,
};
static struct gpio_led mic256_led_pins[] = {
{
.name = "LED-A",
.gpio = 7,
},
};
static struct gpio_led_platform_data mic256_led_data = {
.num_leds = ARRAY_SIZE(mic256_led_pins),
.leds = mic256_led_pins,
};
static struct platform_device mic256_leds = {
.name = "leds-gpio",
.id = -1,
.dev.platform_data = &mic256_led_data,
};
/* Built-in 10/100 Ethernet MAC interfaces */
static struct resource ixp425_npeb_resources[] = {
{
.start = IXP4XX_EthB_BASE_PHYS,
.end = IXP4XX_EthB_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
};
static struct resource ixp425_npec_resources[] = {
{
.start = IXP4XX_EthC_BASE_PHYS,
.end = IXP4XX_EthC_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
};
static struct eth_plat_info ixdp425_plat_eth[] = {
{
.phy = 0,
.rxq = 3,
.txreadyq = 20,
}, {
.phy = 1,
.rxq = 4,
.txreadyq = 21,
},
};
static struct platform_device ixdp425_eth[] = {
{
.name = "ixp4xx_eth",
.id = IXP4XX_ETH_NPEB,
.dev.platform_data = ixdp425_plat_eth,
.num_resources = ARRAY_SIZE(ixp425_npeb_resources),
.resource = ixp425_npeb_resources,
}, {
.name = "ixp4xx_eth",
.id = IXP4XX_ETH_NPEC,
.dev.platform_data = ixdp425_plat_eth + 1,
.num_resources = ARRAY_SIZE(ixp425_npec_resources),
.resource = ixp425_npec_resources,
},
};
static struct platform_device *devixp_pldev[] __initdata = {
&omixp_uart,
&omixp_flash_device[0],
&ixdp425_eth[0],
&ixdp425_eth[1],
};
static struct platform_device *mic256_pldev[] __initdata = {
&omixp_uart,
&omixp_flash_device[0],
&mic256_leds,
&ixdp425_eth[0],
&ixdp425_eth[1],
};
static struct platform_device *miccpt_pldev[] __initdata = {
&omixp_uart,
&omixp_flash_device[0],
&omixp_flash_device[1],
&ixdp425_eth[0],
&ixdp425_eth[1],
};
static void __init omixp_init(void)
{
ixp4xx_sys_init();
/* 16MiB Boot Flash */
omixp_flash_resources[0].start = IXP4XX_EXP_BUS_BASE(0);
omixp_flash_resources[0].end = IXP4XX_EXP_BUS_END(0);
/* 32 MiB Data Flash */
omixp_flash_resources[1].start = IXP4XX_EXP_BUS_BASE(2);
omixp_flash_resources[1].end = IXP4XX_EXP_BUS_END(2);
if (machine_is_devixp())
platform_add_devices(devixp_pldev, ARRAY_SIZE(devixp_pldev));
else if (machine_is_miccpt())
platform_add_devices(miccpt_pldev, ARRAY_SIZE(miccpt_pldev));
else if (machine_is_mic256())
platform_add_devices(mic256_pldev, ARRAY_SIZE(mic256_pldev));
}
#ifdef CONFIG_MACH_DEVIXP
MACHINE_START(DEVIXP, "Omicron DEVIXP")
.atag_offset = 0x100,
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.init_time = ixp4xx_timer_init,
.init_machine = omixp_init,
.restart = ixp4xx_restart,
MACHINE_END
#endif
#ifdef CONFIG_MACH_MICCPT
MACHINE_START(MICCPT, "Omicron MICCPT")
.atag_offset = 0x100,
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.init_time = ixp4xx_timer_init,
.init_machine = omixp_init,
#if defined(CONFIG_PCI)
.dma_zone_size = SZ_64M,
#endif
.restart = ixp4xx_restart,
MACHINE_END
#endif
#ifdef CONFIG_MACH_MIC256
MACHINE_START(MIC256, "Omicron MIC256")
.atag_offset = 0x100,
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.init_time = ixp4xx_timer_init,
.init_machine = omixp_init,
.restart = ixp4xx_restart,
MACHINE_END
#endif

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arch/arm/mach-ixp4xx/vulcan-pci.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arch/mach-ixp4xx/vulcan-pci.c
*
* Vulcan board-level PCI initialization
*
* Copyright (C) 2010 Marc Zyngier <maz@misterjones.org>
*
* based on ixdp425-pci.c:
* Copyright (C) 2002 Intel Corporation.
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*/
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
#include "irqs.h"
/* PCI controller GPIO to IRQ pin mappings */
#define INTA 2
#define INTB 3
void __init vulcan_pci_preinit(void)
{
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
/*
* Cardbus bridge wants way more than the SoC can actually offer,
* and leaves the whole PCI bus in a mess. Artificially limit it
* to 8MB per region. Of course indirect mode doesn't have this
* limitation...
*/
pci_cardbus_mem_size = SZ_8M;
pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n",
(int)(pci_cardbus_mem_size >> 20));
#endif
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init vulcan_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
if (slot == 1)
return IXP4XX_GPIO_IRQ(INTA);
if (slot == 2)
return IXP4XX_GPIO_IRQ(INTB);
return -1;
}
struct hw_pci vulcan_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = vulcan_pci_preinit,
.setup = ixp4xx_setup,
.map_irq = vulcan_map_irq,
};
int __init vulcan_pci_init(void)
{
if (machine_is_arcom_vulcan())
pci_common_init(&vulcan_pci);
return 0;
}
subsys_initcall(vulcan_pci_init);

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arch/arm/mach-ixp4xx/vulcan-setup.c
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// SPDX-License-Identifier: GPL-2.0
/*
* arch/arm/mach-ixp4xx/vulcan-setup.c
*
* Arcom/Eurotech Vulcan board-setup
*
* Copyright (C) 2010 Marc Zyngier <maz@misterjones.org>
*
* based on fsg-setup.c:
* Copyright (C) 2008 Rod Whitby <rod@whitby.id.au>
*/
#include <linux/if_ether.h>
#include <linux/irq.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
#include <linux/io.h>
#include <linux/w1-gpio.h>
#include <linux/gpio/machine.h>
#include <linux/mtd/plat-ram.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include "irqs.h"
static struct flash_platform_data vulcan_flash_data = {
.map_name = "cfi_probe",
.width = 2,
};
static struct resource vulcan_flash_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device vulcan_flash = {
.name = "IXP4XX-Flash",
.id = 0,
.dev = {
.platform_data = &vulcan_flash_data,
},
.resource = &vulcan_flash_resource,
.num_resources = 1,
};
static struct platdata_mtd_ram vulcan_sram_data = {
.mapname = "Vulcan SRAM",
.bankwidth = 1,
};
static struct resource vulcan_sram_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device vulcan_sram = {
.name = "mtd-ram",
.id = 0,
.dev = {
.platform_data = &vulcan_sram_data,
},
.resource = &vulcan_sram_resource,
.num_resources = 1,
};
static struct resource vulcan_uart_resources[] = {
[0] = {
.start = IXP4XX_UART1_BASE_PHYS,
.end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IXP4XX_UART2_BASE_PHYS,
.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
[2] = {
.flags = IORESOURCE_MEM,
},
};
static struct plat_serial8250_port vulcan_uart_data[] = {
[0] = {
.mapbase = IXP4XX_UART1_BASE_PHYS,
.membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART1,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
[1] = {
.mapbase = IXP4XX_UART2_BASE_PHYS,
.membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART2,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
[2] = {
.irq = IXP4XX_GPIO_IRQ(4),
.irqflags = IRQF_TRIGGER_LOW,
.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.uartclk = 1843200,
},
[3] = {
.irq = IXP4XX_GPIO_IRQ(4),
.irqflags = IRQF_TRIGGER_LOW,
.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.uartclk = 1843200,
},
{ }
};
static struct platform_device vulcan_uart = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = vulcan_uart_data,
},
.resource = vulcan_uart_resources,
.num_resources = ARRAY_SIZE(vulcan_uart_resources),
};
static struct resource vulcan_npeb_resources[] = {
{
.start = IXP4XX_EthB_BASE_PHYS,
.end = IXP4XX_EthB_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
};
static struct resource vulcan_npec_resources[] = {
{
.start = IXP4XX_EthC_BASE_PHYS,
.end = IXP4XX_EthC_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
};
static struct eth_plat_info vulcan_plat_eth[] = {
[0] = {
.phy = 0,
.rxq = 3,
.txreadyq = 20,
},
[1] = {
.phy = 1,
.rxq = 4,
.txreadyq = 21,
},
};
static struct platform_device vulcan_eth[] = {
[0] = {
.name = "ixp4xx_eth",
.id = IXP4XX_ETH_NPEB,
.dev = {
.platform_data = &vulcan_plat_eth[0],
},
.num_resources = ARRAY_SIZE(vulcan_npeb_resources),
.resource = vulcan_npeb_resources,
},
[1] = {
.name = "ixp4xx_eth",
.id = IXP4XX_ETH_NPEC,
.dev = {
.platform_data = &vulcan_plat_eth[1],
},
.num_resources = ARRAY_SIZE(vulcan_npec_resources),
.resource = vulcan_npec_resources,
},
};
static struct resource vulcan_max6369_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device vulcan_max6369 = {
.name = "max6369_wdt",
.id = -1,
.resource = &vulcan_max6369_resource,
.num_resources = 1,
};
static struct gpiod_lookup_table vulcan_w1_gpiod_table = {
.dev_id = "w1-gpio",
.table = {
GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", 14, NULL, 0,
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
},
};
static struct w1_gpio_platform_data vulcan_w1_gpio_pdata = {
/* Intentionally left blank */
};
static struct platform_device vulcan_w1_gpio = {
.name = "w1-gpio",
.id = 0,
.dev = {
.platform_data = &vulcan_w1_gpio_pdata,
},
};
static struct platform_device *vulcan_devices[] __initdata = {
&vulcan_uart,
&vulcan_flash,
&vulcan_sram,
&vulcan_max6369,
&vulcan_eth[0],
&vulcan_eth[1],
&vulcan_w1_gpio,
};
static void __init vulcan_init(void)
{
ixp4xx_sys_init();
/* Flash is spread over both CS0 and CS1 */
vulcan_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
vulcan_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
*IXP4XX_EXP_CS0 = IXP4XX_EXP_BUS_CS_EN |
IXP4XX_EXP_BUS_STROBE_T(3) |
IXP4XX_EXP_BUS_SIZE(0xF) |
IXP4XX_EXP_BUS_BYTE_RD16 |
IXP4XX_EXP_BUS_WR_EN;
*IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
/* SRAM on CS2, (256kB, 8bit, writable) */
vulcan_sram_resource.start = IXP4XX_EXP_BUS_BASE(2);
vulcan_sram_resource.end = IXP4XX_EXP_BUS_BASE(2) + SZ_256K - 1;
*IXP4XX_EXP_CS2 = IXP4XX_EXP_BUS_CS_EN |
IXP4XX_EXP_BUS_STROBE_T(1) |
IXP4XX_EXP_BUS_HOLD_T(2) |
IXP4XX_EXP_BUS_SIZE(9) |
IXP4XX_EXP_BUS_SPLT_EN |
IXP4XX_EXP_BUS_WR_EN |
IXP4XX_EXP_BUS_BYTE_EN;
/* XR16L2551 on CS3 (Moto style, 512 bytes, 8bits, writable) */
vulcan_uart_resources[2].start = IXP4XX_EXP_BUS_BASE(3);
vulcan_uart_resources[2].end = IXP4XX_EXP_BUS_BASE(3) + 16 - 1;
vulcan_uart_data[2].mapbase = vulcan_uart_resources[2].start;
vulcan_uart_data[3].mapbase = vulcan_uart_data[2].mapbase + 8;
*IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN |
IXP4XX_EXP_BUS_STROBE_T(3) |
IXP4XX_EXP_BUS_CYCLES(IXP4XX_EXP_BUS_CYCLES_MOTOROLA)|
IXP4XX_EXP_BUS_WR_EN |
IXP4XX_EXP_BUS_BYTE_EN;
/* GPIOS on CS4 (512 bytes, 8bits, writable) */
*IXP4XX_EXP_CS4 = IXP4XX_EXP_BUS_CS_EN |
IXP4XX_EXP_BUS_WR_EN |
IXP4XX_EXP_BUS_BYTE_EN;
/* max6369 on CS5 (512 bytes, 8bits, writable) */
vulcan_max6369_resource.start = IXP4XX_EXP_BUS_BASE(5);
vulcan_max6369_resource.end = IXP4XX_EXP_BUS_BASE(5);
*IXP4XX_EXP_CS5 = IXP4XX_EXP_BUS_CS_EN |
IXP4XX_EXP_BUS_WR_EN |
IXP4XX_EXP_BUS_BYTE_EN;
gpiod_add_lookup_table(&vulcan_w1_gpiod_table);
platform_add_devices(vulcan_devices, ARRAY_SIZE(vulcan_devices));
}
MACHINE_START(ARCOM_VULCAN, "Arcom/Eurotech Vulcan")
/* Maintainer: Marc Zyngier <maz@misterjones.org> */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.init_time = ixp4xx_timer_init,
.atag_offset = 0x100,
.init_machine = vulcan_init,
#if defined(CONFIG_PCI)
.dma_zone_size = SZ_64M,
#endif
.restart = ixp4xx_restart,
MACHINE_END

60
arch/arm/mach-ixp4xx/wg302v2-pci.c
View File

@ -1,60 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arch/mach-ixp4xx/wg302v2-pci.c
*
* PCI setup routines for the Netgear WG302 v2 and WAG302 v2
*
* Copyright (C) 2007 Imre Kaloz <kaloz@openwrt.org>
*
* based on coyote-pci.c:
* Copyright (C) 2002 Jungo Software Technologies.
* Copyright (C) 2003 MontaVista Software, Inc.
*
* Maintainer: Imre Kaloz <kaloz@openwrt.org>
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <asm/mach/pci.h>
#include "irqs.h"
void __init wg302v2_pci_preinit(void)
{
irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init wg302v2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
if (slot == 1)
return IRQ_IXP4XX_GPIO8;
else if (slot == 2)
return IRQ_IXP4XX_GPIO9;
else return -1;
}
struct hw_pci wg302v2_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = wg302v2_pci_preinit,
.setup = ixp4xx_setup,
.map_irq = wg302v2_map_irq,
};
int __init wg302v2_pci_init(void)
{
if (machine_is_wg302v2())
pci_common_init(&wg302v2_pci);
return 0;
}
subsys_initcall(wg302v2_pci_init);

114
arch/arm/mach-ixp4xx/wg302v2-setup.c
View File

@ -1,114 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* arch/arm/mach-ixp4xx/wg302-setup.c
*
* Board setup for the Netgear WG302 v2 and WAG302 v2
*
* Copyright (C) 2007 Imre Kaloz <Kaloz@openwrt.org>
*
* based on coyote-setup.c:
* Copyright (C) 2003-2005 MontaVista Software, Inc.
*
* Author: Imre Kaloz <kaloz@openwrt.org>
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_8250.h>
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include "irqs.h"
static struct flash_platform_data wg302v2_flash_data = {
.map_name = "cfi_probe",
.width = 2,
};
static struct resource wg302v2_flash_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device wg302v2_flash = {
.name = "IXP4XX-Flash",
.id = 0,
.dev = {
.platform_data = &wg302v2_flash_data,
},
.num_resources = 1,
.resource = &wg302v2_flash_resource,
};
static struct resource wg302v2_uart_resource = {
.start = IXP4XX_UART2_BASE_PHYS,
.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
};
static struct plat_serial8250_port wg302v2_uart_data[] = {
{
.mapbase = IXP4XX_UART2_BASE_PHYS,
.membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART2,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
{ },
};
static struct platform_device wg302v2_uart = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = wg302v2_uart_data,
},
.num_resources = 1,
.resource = &wg302v2_uart_resource,
};
static struct platform_device *wg302v2_devices[] __initdata = {
&wg302v2_flash,
&wg302v2_uart,
};
static void __init wg302v2_init(void)
{
ixp4xx_sys_init();
wg302v2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
wg302v2_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
*IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
*IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
platform_add_devices(wg302v2_devices, ARRAY_SIZE(wg302v2_devices));
}
#ifdef CONFIG_MACH_WG302V2
MACHINE_START(WG302V2, "Netgear WG302 v2 / WAG302 v2")
/* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.init_time = ixp4xx_timer_init,
.atag_offset = 0x100,
.init_machine = wg302v2_init,
#if defined(CONFIG_PCI)
.dma_zone_size = SZ_64M,
#endif
.restart = ixp4xx_restart,
MACHINE_END
#endif

23
arch/arm/mach-omap2/Kconfig
View File

@ -181,18 +181,6 @@ config SOC_TI81XX
depends on ARCH_OMAP3
default y
config OMAP_PACKAGE_CBC
bool
config OMAP_PACKAGE_CBB
bool
config OMAP_PACKAGE_CUS
bool
config OMAP_PACKAGE_CBP
bool
comment "OMAP Legacy Platform Data Board Type"
depends on ARCH_OMAP2PLUS
@ -204,17 +192,6 @@ config MACH_OMAP2_TUSB6010
depends on ARCH_OMAP2 && SOC_OMAP2420
default y if MACH_NOKIA_N8X0
config MACH_OMAP3517EVM
bool "OMAP3517/ AM3517 EVM board"
depends on ARCH_OMAP3
default y
config MACH_OMAP3_PANDORA
bool "OMAP3 Pandora"
depends on ARCH_OMAP3
default y
select OMAP_PACKAGE_CBB
config MACH_NOKIA_N810
bool

3
arch/arm/mach-s3c/mach-gta02.c
View File

@ -79,13 +79,12 @@ static struct pcf50633 *gta02_pcf;
static long gta02_panic_blink(int state)
{
long delay = 0;
char led;
led = (state) ? 1 : 0;
gpio_direction_output(GTA02_GPIO_AUX_LED, led);
return delay;
return 0;
}

2
arch/arm64/include/asm/hwcap.h
View File

@ -18,7 +18,7 @@
#define COMPAT_HWCAP_EDSP (1 << 7)
#define COMPAT_HWCAP_JAVA (1 << 8)
#define COMPAT_HWCAP_IWMMXT (1 << 9)
#define COMPAT_HWCAP_CRUNCH (1 << 10)
#define COMPAT_HWCAP_CRUNCH (1 << 10) /* Obsolete */
#define COMPAT_HWCAP_THUMBEE (1 << 11)
#define COMPAT_HWCAP_NEON (1 << 12)
#define COMPAT_HWCAP_VFPv3 (1 << 13)

35
drivers/soc/aspeed/aspeed-lpc-ctrl.c
View File

@ -37,6 +37,7 @@ struct aspeed_lpc_ctrl {
u32 pnor_size;
u32 pnor_base;
bool fwh2ahb;
struct regmap *scu;
};
static struct aspeed_lpc_ctrl *file_aspeed_lpc_ctrl(struct file *file)
@ -51,7 +52,7 @@ static int aspeed_lpc_ctrl_mmap(struct file *file, struct vm_area_struct *vma)
unsigned long vsize = vma->vm_end - vma->vm_start;
pgprot_t prot = vma->vm_page_prot;
if (vma->vm_pgoff + vsize > lpc_ctrl->mem_base + lpc_ctrl->mem_size)
if (vma->vm_pgoff + vma_pages(vma) > lpc_ctrl->mem_size >> PAGE_SHIFT)
return -EINVAL;
/* ast2400/2500 AHB accesses are not cache coherent */
@ -183,13 +184,22 @@ static long aspeed_lpc_ctrl_ioctl(struct file *file, unsigned int cmd,
/*
* Switch to FWH2AHB mode, AST2600 only.
*
* The other bits in this register are interrupt status bits
* that are cleared by writing 1. As we don't want to clear
* them, set only the bit of interest.
*/
if (lpc_ctrl->fwh2ahb)
if (lpc_ctrl->fwh2ahb) {
/*
* Enable FWH2AHB in SCU debug control register 2. This
* does not turn it on, but makes it available for it
* to be configured in HICR6.
*/
regmap_update_bits(lpc_ctrl->scu, 0x0D8, BIT(2), 0);
/*
* The other bits in this register are interrupt status bits
* that are cleared by writing 1. As we don't want to clear
* them, set only the bit of interest.
*/
regmap_write(lpc_ctrl->regmap, HICR6, SW_FWH2AHB);
}
/*
* Enable LPC FHW cycles. This is required for the host to
@ -285,6 +295,16 @@ static int aspeed_lpc_ctrl_probe(struct platform_device *pdev)
return -ENODEV;
}
if (of_device_is_compatible(dev->of_node, "aspeed,ast2600-lpc-ctrl")) {
lpc_ctrl->fwh2ahb = true;
lpc_ctrl->scu = syscon_regmap_lookup_by_compatible("aspeed,ast2600-scu");
if (IS_ERR(lpc_ctrl->scu)) {
dev_err(dev, "couldn't find scu\n");
return PTR_ERR(lpc_ctrl->scu);
}
}
lpc_ctrl->clk = devm_clk_get(dev, NULL);
if (IS_ERR(lpc_ctrl->clk)) {
dev_err(dev, "couldn't get clock\n");
@ -296,9 +316,6 @@ static int aspeed_lpc_ctrl_probe(struct platform_device *pdev)
return rc;
}
if (of_device_is_compatible(dev->of_node, "aspeed,ast2600-lpc-ctrl"))
lpc_ctrl->fwh2ahb = true;
lpc_ctrl->miscdev.minor = MISC_DYNAMIC_MINOR;
lpc_ctrl->miscdev.name = DEVICE_NAME;
lpc_ctrl->miscdev.fops = &aspeed_lpc_ctrl_fops;

2
drivers/soc/aspeed/aspeed-p2a-ctrl.c
View File

@ -110,7 +110,7 @@ static int aspeed_p2a_mmap(struct file *file, struct vm_area_struct *vma)
vsize = vma->vm_end - vma->vm_start;
prot = vma->vm_page_prot;
if (vma->vm_pgoff + vsize > ctrl->mem_base + ctrl->mem_size)
if (vma->vm_pgoff + vma_pages(vma) > ctrl->mem_size >> PAGE_SHIFT)
return -EINVAL;
/* ast2400/2500 AHB accesses are not cache coherent */

1
drivers/soc/aspeed/aspeed-socinfo.c
View File

@ -26,6 +26,7 @@ static struct {
{ "AST2600", 0x05000303 },
{ "AST2620", 0x05010203 },
{ "AST2605", 0x05030103 },
{ "AST2625", 0x05030403 },
};
static const char *siliconid_to_name(u32 siliconid)

26
include/linux/clk/at91_pmc.h
View File

@ -137,6 +137,32 @@
#define AT91_PMC_PLLADIV2_ON (1 << 12)
#define AT91_PMC_H32MXDIV BIT(24)
#define AT91_PMC_MCR_V2 0x30 /* Master Clock Register [SAMA7G5 only] */
#define AT91_PMC_MCR_V2_ID_MSK (0xF)
#define AT91_PMC_MCR_V2_ID(_id) ((_id) & AT91_PMC_MCR_V2_ID_MSK)
#define AT91_PMC_MCR_V2_CMD (1 << 7)
#define AT91_PMC_MCR_V2_DIV (7 << 8)
#define AT91_PMC_MCR_V2_DIV1 (0 << 8)
#define AT91_PMC_MCR_V2_DIV2 (1 << 8)
#define AT91_PMC_MCR_V2_DIV4 (2 << 8)
#define AT91_PMC_MCR_V2_DIV8 (3 << 8)
#define AT91_PMC_MCR_V2_DIV16 (4 << 8)
#define AT91_PMC_MCR_V2_DIV32 (5 << 8)
#define AT91_PMC_MCR_V2_DIV64 (6 << 8)
#define AT91_PMC_MCR_V2_DIV3 (7 << 8)
#define AT91_PMC_MCR_V2_CSS (0x1F << 16)
#define AT91_PMC_MCR_V2_CSS_MD_SLCK (0 << 16)
#define AT91_PMC_MCR_V2_CSS_TD_SLCK (1 << 16)
#define AT91_PMC_MCR_V2_CSS_MAINCK (2 << 16)
#define AT91_PMC_MCR_V2_CSS_MCK0 (3 << 16)
#define AT91_PMC_MCR_V2_CSS_SYSPLL (5 << 16)
#define AT91_PMC_MCR_V2_CSS_DDRPLL (6 << 16)
#define AT91_PMC_MCR_V2_CSS_IMGPLL (7 << 16)
#define AT91_PMC_MCR_V2_CSS_BAUDPLL (8 << 16)
#define AT91_PMC_MCR_V2_CSS_AUDIOPLL (9 << 16)
#define AT91_PMC_MCR_V2_CSS_ETHPLL (10 << 16)
#define AT91_PMC_MCR_V2_EN (1 << 28)
#define AT91_PMC_XTALF 0x34 /* Main XTAL Frequency Register [SAMA7G5 only] */
#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */

80
include/soc/at91/sama7-ddr.h Normal file
View File

@ -0,0 +1,80 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Microchip SAMA7 UDDR Controller and DDR3 PHY Controller registers offsets
* and bit definitions.
*
* Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries
*
* Author: Claudu Beznea <claudiu.beznea@microchip.com>
*/
#ifndef __SAMA7_DDR_H__
#define __SAMA7_DDR_H__
#ifdef CONFIG_SOC_SAMA7
/* DDR3PHY */
#define DDR3PHY_PIR (0x04) /* DDR3PHY PHY Initialization Register */
#define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */
#define DDR3PHY_PIR_ITMSRST (1 << 4) /* Interface Timing Module Soft Reset */
#define DDR3PHY_PIR_DLLLOCK (1 << 2) /* DLL Lock */
#define DDR3PHY_PIR_DLLSRST (1 << 1) /* DLL Soft Rest */
#define DDR3PHY_PIR_INIT (1 << 0) /* Initialization Trigger */
#define DDR3PHY_PGCR (0x08) /* DDR3PHY PHY General Configuration Register */
#define DDR3PHY_PGCR_CKDV1 (1 << 13) /* CK# Disable Value */
#define DDR3PHY_PGCR_CKDV0 (1 << 12) /* CK Disable Value */
#define DDR3PHY_PGSR (0x0C) /* DDR3PHY PHY General Status Register */
#define DDR3PHY_PGSR_IDONE (1 << 0) /* Initialization Done */
#define DDR3PHY_ACIOCR (0x24) /* DDR3PHY AC I/O Configuration Register */
#define DDR3PHY_ACIOCR_CSPDD_CS0 (1 << 18) /* CS#[0] Power Down Driver */
#define DDR3PHY_ACIOCR_CKPDD_CK0 (1 << 8) /* CK[0] Power Down Driver */
#define DDR3PHY_ACIORC_ACPDD (1 << 3) /* AC Power Down Driver */
#define DDR3PHY_DXCCR (0x28) /* DDR3PHY DATX8 Common Configuration Register */
#define DDR3PHY_DXCCR_DXPDR (1 << 3) /* Data Power Down Receiver */
#define DDR3PHY_DSGCR (0x2C) /* DDR3PHY DDR System General Configuration Register */
#define DDR3PHY_DSGCR_ODTPDD_ODT0 (1 << 20) /* ODT[0] Power Down Driver */
#define DDR3PHY_ZQ0SR0 (0x188) /* ZQ status register 0 */
/* UDDRC */
#define UDDRC_STAT (0x04) /* UDDRC Operating Mode Status Register */
#define UDDRC_STAT_SELFREF_TYPE_DIS (0x0 << 4) /* SDRAM is not in Self-refresh */
#define UDDRC_STAT_SELFREF_TYPE_PHY (0x1 << 4) /* SDRAM is in Self-refresh, which was caused by PHY Master Request */
#define UDDRC_STAT_SELFREF_TYPE_SW (0x2 << 4) /* SDRAM is in Self-refresh, which was not caused solely under Automatic Self-refresh control */
#define UDDRC_STAT_SELFREF_TYPE_AUTO (0x3 << 4) /* SDRAM is in Self-refresh, which was caused by Automatic Self-refresh only */
#define UDDRC_STAT_SELFREF_TYPE_MSK (0x3 << 4) /* Self-refresh type mask */
#define UDDRC_STAT_OPMODE_INIT (0x0 << 0) /* Init */
#define UDDRC_STAT_OPMODE_NORMAL (0x1 << 0) /* Normal */
#define UDDRC_STAT_OPMODE_PWRDOWN (0x2 << 0) /* Power-down */
#define UDDRC_STAT_OPMODE_SELF_REFRESH (0x3 << 0) /* Self-refresh */
#define UDDRC_STAT_OPMODE_MSK (0x7 << 0) /* Operating mode mask */
#define UDDRC_PWRCTL (0x30) /* UDDRC Low Power Control Register */
#define UDDRC_PWRCTRL_SELFREF_SW (1 << 5) /* Software self-refresh */
#define UDDRC_DFIMISC (0x1B0) /* UDDRC DFI Miscellaneous Control Register */
#define UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0) /* PHY initialization complete enable signal */
#define UDDRC_SWCTRL (0x320) /* UDDRC Software Register Programming Control Enable */
#define UDDRC_SWCTRL_SW_DONE (1 << 0) /* Enable quasi-dynamic register programming outside reset */
#define UDDRC_SWSTAT (0x324) /* UDDRC Software Register Programming Control Status */
#define UDDRC_SWSTAT_SW_DONE_ACK (1 << 0) /* Register programming done */
#define UDDRC_PSTAT (0x3FC) /* UDDRC Port Status Register */
#define UDDRC_PSTAT_ALL_PORTS (0x1F001F) /* Read + writes outstanding transactions on all ports */
#define UDDRC_PCTRL_0 (0x490) /* UDDRC Port 0 Control Register */
#define UDDRC_PCTRL_1 (0x540) /* UDDRC Port 1 Control Register */
#define UDDRC_PCTRL_2 (0x5F0) /* UDDRC Port 2 Control Register */
#define UDDRC_PCTRL_3 (0x6A0) /* UDDRC Port 3 Control Register */
#define UDDRC_PCTRL_4 (0x750) /* UDDRC Port 4 Control Register */
#endif /* CONFIG_SOC_SAMA7 */
#endif /* __SAMA7_DDR_H__ */

34
include/soc/at91/sama7-sfrbu.h Normal file
View File

@ -0,0 +1,34 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Microchip SAMA7 SFRBU registers offsets and bit definitions.
*
* Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries
*
* Author: Claudu Beznea <claudiu.beznea@microchip.com>
*/
#ifndef __SAMA7_SFRBU_H__
#define __SAMA7_SFRBU_H__
#ifdef CONFIG_SOC_SAMA7
#define AT91_SFRBU_PSWBU (0x00) /* SFRBU Power Switch BU Control Register */
#define AT91_SFRBU_PSWBU_PSWKEY (0x4BD20C << 8) /* Specific value mandatory to allow writing of other register bits */
#define AT91_SFRBU_PSWBU_STATE (1 << 2) /* Power switch BU state */
#define AT91_SFRBU_PSWBU_SOFTSWITCH (1 << 1) /* Power switch BU source selection */
#define AT91_SFRBU_PSWBU_CTRL (1 << 0) /* Power switch BU control */
#define AT91_SFRBU_25LDOCR (0x0C) /* SFRBU 2.5V LDO Control Register */
#define AT91_SFRBU_25LDOCR_LDOANAKEY (0x3B6E18 << 8) /* Specific value mandatory to allow writing of other register bits. */
#define AT91_SFRBU_25LDOCR_STATE (1 << 3) /* LDOANA Switch On/Off Control */
#define AT91_SFRBU_25LDOCR_LP (1 << 2) /* LDOANA Low-Power Mode Control */
#define AT91_SFRBU_PD_VALUE_MSK (0x3)
#define AT91_SFRBU_25LDOCR_PD_VALUE(v) ((v) & AT91_SFRBU_PD_VALUE_MSK) /* LDOANA Pull-down value */
#define AT91_FRBU_DDRPWR (0x10) /* SFRBU DDR Power Control Register */
#define AT91_FRBU_DDRPWR_STATE (1 << 0) /* DDR Power Mode State */
#endif /* CONFIG_SOC_SAMA7 */
#endif /* __SAMA7_SFRBU_H__ */