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dmaengine: edma: Get qDMA channel information from HW also
Query the number of qDMA channels from CCCFG register. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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@ -107,6 +107,7 @@
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/* CCCFG register */
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#define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
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#define GET_NUM_QDMACH(x) (x & 0x70 >> 4) /* bits 4-6 */
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#define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
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#define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
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#define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
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@ -220,6 +221,7 @@ struct edma_cc {
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/* eDMA3 resource information */
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unsigned num_channels;
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unsigned num_qchannels;
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unsigned num_region;
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unsigned num_slots;
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unsigned num_tc;
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@ -1819,6 +1821,9 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
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value = GET_NUM_DMACH(cccfg);
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ecc->num_channels = BIT(value + 1);
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value = GET_NUM_QDMACH(cccfg);
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ecc->num_qchannels = value * 2;
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value = GET_NUM_PAENTRY(cccfg);
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ecc->num_slots = BIT(value + 4);
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@ -1830,6 +1835,7 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
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dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg);
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dev_dbg(dev, "num_region: %u\n", ecc->num_region);
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dev_dbg(dev, "num_channels: %u\n", ecc->num_channels);
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dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels);
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dev_dbg(dev, "num_slots: %u\n", ecc->num_slots);
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dev_dbg(dev, "num_tc: %u\n", ecc->num_tc);
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dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no");
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