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https://github.com/edk2-porting/linux-next.git
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sh: fix Transfer Size calculation in both DMA drivers
Both the original arch/sh/drivers/dma/dma-sh.c and the new SH dmaengine drivers do not take into account bits 3:2 of the Transfer Size field in the CHCR register, besides, bit-field defines set bit 2, but the mask only passes bits 1:0 through. TS_16BLK and TS_32BLK macros are bogus too. This patch fixes all these issues for sh7722 and sh7724, other CPUs stay unchanged and might need to be fixed too. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Guennadi Liakhovetski
Paul Mundt
parent
fc4618575f
commit
623b4ac4bf
@ -52,11 +52,14 @@ static inline unsigned int get_dmte_irq(unsigned int chan)
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*
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* iterations to complete the transfer.
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*/
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static unsigned int ts_shift[] = TS_SHIFT;
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static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
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{
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u32 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
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int cnt = ((chcr & CHCR_TS_LOW_MASK) >> CHCR_TS_LOW_SHIFT) |
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((chcr & CHCR_TS_HIGH_MASK) >> CHCR_TS_HIGH_SHIFT);
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return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT];
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return ts_shift[cnt];
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}
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/*
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@ -83,7 +83,7 @@ static int dmte_irq_map[] __maybe_unused = {
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* Define the default configuration for dual address memory-memory transfer.
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* The 0x400 value represents auto-request, external->external.
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*/
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#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_32)
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#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_INDEX2VAL(XMIT_SZ_32BIT))
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/* DMA base address */
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static u32 dma_base_addr[] __maybe_unused = {
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@ -20,8 +20,10 @@
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#define TS_32 0x00000010
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#define TS_128 0x00000018
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#define CHCR_TS_MASK 0x18
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#define CHCR_TS_SHIFT 3
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#define CHCR_TS_LOW_MASK 0x18
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#define CHCR_TS_LOW_SHIFT 3
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#define CHCR_TS_HIGH_MASK 0
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#define CHCR_TS_HIGH_SHIFT 0
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#define DMAOR_INIT DMAOR_DME
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@ -36,11 +38,13 @@ enum {
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XMIT_SZ_128BIT,
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};
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static unsigned int ts_shift[] __maybe_unused = {
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[XMIT_SZ_8BIT] = 0,
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[XMIT_SZ_16BIT] = 1,
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[XMIT_SZ_32BIT] = 2,
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[XMIT_SZ_128BIT] = 4,
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};
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#define TS_SHIFT { \
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[XMIT_SZ_8BIT] = 0, \
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[XMIT_SZ_16BIT] = 1, \
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[XMIT_SZ_32BIT] = 2, \
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[XMIT_SZ_128BIT] = 4, \
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}
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#define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT)
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#endif /* __ASM_CPU_SH3_DMA_H */
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@ -2,13 +2,26 @@
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#define __ASM_SH_CPU_SH4_DMA_SH7780_H
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#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
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defined(CONFIG_CPU_SUBTYPE_SH7722) || \
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defined(CONFIG_CPU_SUBTYPE_SH7730)
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#define DMTE0_IRQ 48
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#define DMTE4_IRQ 76
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#define DMAE0_IRQ 78 /* DMA Error IRQ*/
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#define SH_DMAC_BASE0 0xFE008020
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#define SH_DMARS_BASE 0xFE009000
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#define CHCR_TS_LOW_MASK 0x00000018
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#define CHCR_TS_LOW_SHIFT 3
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#define CHCR_TS_HIGH_MASK 0
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#define CHCR_TS_HIGH_SHIFT 0
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#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
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#define DMTE0_IRQ 48
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#define DMTE4_IRQ 76
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#define DMAE0_IRQ 78 /* DMA Error IRQ*/
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#define SH_DMAC_BASE0 0xFE008020
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#define SH_DMARS_BASE 0xFE009000
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#define CHCR_TS_LOW_MASK 0x00000018
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#define CHCR_TS_LOW_SHIFT 3
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#define CHCR_TS_HIGH_MASK 0x00300000
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#define CHCR_TS_HIGH_SHIFT 20
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#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
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defined(CONFIG_CPU_SUBTYPE_SH7764)
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#define DMTE0_IRQ 34
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@ -16,8 +29,11 @@
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#define DMAE0_IRQ 38
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#define SH_DMAC_BASE0 0xFF608020
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#define SH_DMARS_BASE 0xFF609000
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#elif defined(CONFIG_CPU_SUBTYPE_SH7723) || \
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defined(CONFIG_CPU_SUBTYPE_SH7724)
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#define CHCR_TS_LOW_MASK 0x00000018
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#define CHCR_TS_LOW_SHIFT 3
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#define CHCR_TS_HIGH_MASK 0
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#define CHCR_TS_HIGH_SHIFT 0
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#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
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#define DMTE0_IRQ 48 /* DMAC0A*/
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#define DMTE4_IRQ 76 /* DMAC0B */
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#define DMTE6_IRQ 40
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@ -30,6 +46,27 @@
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#define SH_DMAC_BASE0 0xFE008020
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#define SH_DMAC_BASE1 0xFDC08020
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#define SH_DMARS_BASE 0xFDC09000
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#define CHCR_TS_LOW_MASK 0x00000018
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#define CHCR_TS_LOW_SHIFT 3
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#define CHCR_TS_HIGH_MASK 0
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#define CHCR_TS_HIGH_SHIFT 0
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#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
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#define DMTE0_IRQ 48 /* DMAC0A*/
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#define DMTE4_IRQ 76 /* DMAC0B */
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#define DMTE6_IRQ 40
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#define DMTE8_IRQ 42 /* DMAC1A */
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#define DMTE9_IRQ 43
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#define DMTE10_IRQ 72 /* DMAC1B */
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#define DMTE11_IRQ 73
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#define DMAE0_IRQ 78 /* DMA Error IRQ*/
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#define DMAE1_IRQ 74 /* DMA Error IRQ*/
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#define SH_DMAC_BASE0 0xFE008020
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#define SH_DMAC_BASE1 0xFDC08020
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#define SH_DMARS_BASE 0xFDC09000
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#define CHCR_TS_LOW_MASK 0x00000018
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#define CHCR_TS_LOW_SHIFT 3
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#define CHCR_TS_HIGH_MASK 0x00600000
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#define CHCR_TS_HIGH_SHIFT 21
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#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
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#define DMTE0_IRQ 34
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#define DMTE4_IRQ 44
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@ -42,6 +79,10 @@
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#define SH_DMAC_BASE0 0xFC808020
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#define SH_DMAC_BASE1 0xFC818020
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#define SH_DMARS_BASE 0xFC809000
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#define CHCR_TS_LOW_MASK 0x00000018
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#define CHCR_TS_LOW_SHIFT 3
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#define CHCR_TS_HIGH_MASK 0
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#define CHCR_TS_HIGH_SHIFT 0
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#else /* SH7785 */
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#define DMTE0_IRQ 33
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#define DMTE4_IRQ 37
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@ -55,17 +96,16 @@
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#define SH_DMAC_BASE0 0xFC808020
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#define SH_DMAC_BASE1 0xFCC08020
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#define SH_DMARS_BASE 0xFC809000
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#define CHCR_TS_LOW_MASK 0x00000018
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#define CHCR_TS_LOW_SHIFT 3
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#define CHCR_TS_HIGH_MASK 0
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#define CHCR_TS_HIGH_SHIFT 0
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#endif
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#define REQ_HE 0x000000C0
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#define REQ_H 0x00000080
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#define REQ_LE 0x00000040
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#define TM_BURST 0x0000020
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#define TS_8 0x00000000
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#define TS_16 0x00000008
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#define TS_32 0x00000010
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#define TS_16BLK 0x00000018
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#define TS_32BLK 0x00100000
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#define REQ_HE 0x000000C0
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#define REQ_H 0x00000080
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#define REQ_LE 0x00000040
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#define TM_BURST 0x00000020
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/*
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* The SuperH DMAC supports a number of transmit sizes, we list them here,
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@ -74,22 +114,31 @@
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* Defaults to a 64-bit transfer size.
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*/
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enum {
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XMIT_SZ_8BIT,
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XMIT_SZ_16BIT,
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XMIT_SZ_32BIT,
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XMIT_SZ_128BIT,
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XMIT_SZ_256BIT,
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XMIT_SZ_8BIT = 0,
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XMIT_SZ_16BIT = 1,
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XMIT_SZ_32BIT = 2,
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XMIT_SZ_64BIT = 7,
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XMIT_SZ_128BIT = 3,
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XMIT_SZ_256BIT = 4,
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XMIT_SZ_128BIT_BLK = 0xb,
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XMIT_SZ_256BIT_BLK = 0xc,
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};
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/*
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* The DMA count is defined as the number of bytes to transfer.
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*/
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static unsigned int ts_shift[] __maybe_unused = {
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[XMIT_SZ_8BIT] = 0,
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[XMIT_SZ_16BIT] = 1,
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[XMIT_SZ_32BIT] = 2,
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[XMIT_SZ_128BIT] = 4,
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[XMIT_SZ_256BIT] = 5,
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};
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#define TS_SHIFT { \
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[XMIT_SZ_8BIT] = 0, \
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[XMIT_SZ_16BIT] = 1, \
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[XMIT_SZ_32BIT] = 2, \
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[XMIT_SZ_64BIT] = 3, \
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[XMIT_SZ_128BIT] = 4, \
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[XMIT_SZ_256BIT] = 5, \
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[XMIT_SZ_128BIT_BLK] = 4, \
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[XMIT_SZ_256BIT_BLK] = 5, \
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}
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#define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \
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((((i) >> 2) & 3) << CHCR_TS_HIGH_SHIFT))
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#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
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@ -6,8 +6,6 @@
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#ifdef CONFIG_CPU_SH4A
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#define DMAOR_INIT (DMAOR_DME)
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#define CHCR_TS_MASK 0x18
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#define CHCR_TS_SHIFT 3
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#include <cpu/dma-sh4a.h>
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#else /* CONFIG_CPU_SH4A */
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@ -29,8 +27,10 @@
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#define TS_32 0x00000030
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#define TS_64 0x00000000
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#define CHCR_TS_MASK 0x70
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#define CHCR_TS_SHIFT 4
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#define CHCR_TS_LOW_MASK 0x70
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#define CHCR_TS_LOW_SHIFT 4
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#define CHCR_TS_HIGH_MASK 0
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#define CHCR_TS_HIGH_SHIFT 0
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#define DMAOR_COD 0x00000008
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@ -41,23 +41,26 @@
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* Defaults to a 64-bit transfer size.
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*/
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enum {
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XMIT_SZ_64BIT,
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XMIT_SZ_8BIT,
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XMIT_SZ_16BIT,
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XMIT_SZ_32BIT,
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XMIT_SZ_256BIT,
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XMIT_SZ_8BIT = 1,
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XMIT_SZ_16BIT = 2,
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XMIT_SZ_32BIT = 3,
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XMIT_SZ_64BIT = 0,
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XMIT_SZ_256BIT = 4,
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};
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/*
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* The DMA count is defined as the number of bytes to transfer.
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*/
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static unsigned int ts_shift[] __maybe_unused = {
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[XMIT_SZ_64BIT] = 3,
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[XMIT_SZ_8BIT] = 0,
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[XMIT_SZ_16BIT] = 1,
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[XMIT_SZ_32BIT] = 2,
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[XMIT_SZ_256BIT] = 5,
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};
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#define TS_SHIFT { \
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[XMIT_SZ_8BIT] = 0, \
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[XMIT_SZ_16BIT] = 1, \
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[XMIT_SZ_32BIT] = 2, \
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[XMIT_SZ_64BIT] = 3, \
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[XMIT_SZ_256BIT] = 5, \
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}
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#define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT)
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#endif
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#endif /* __ASM_CPU_SH4_DMA_H */
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@ -105,10 +105,14 @@ static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
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return false; /* waiting */
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}
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static unsigned int ts_shift[] = TS_SHIFT;
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static inline unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan)
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{
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u32 chcr = sh_dmae_readl(sh_chan, CHCR);
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return ts_shift[(chcr & CHCR_TS_MASK) >> CHCR_TS_SHIFT];
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int cnt = ((chcr & CHCR_TS_LOW_MASK) >> CHCR_TS_LOW_SHIFT) |
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((chcr & CHCR_TS_HIGH_MASK) >> CHCR_TS_HIGH_SHIFT);
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return ts_shift[cnt];
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}
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static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
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