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MIPS: Select CONFIG_ARCH_USE_CMPXCHG_LOCKREF for MIPS64
On MIPS64 we have spinlocks that are 32b in size and an efficient cmpxchg64 implementation, so we qualify to make use of cmpxchg backed lockrefs. Select the ARCH_USE_CMPXCHG_LOCKREF Kconfig symbol and provide a trivial implementation of arch_spin_value_unlocked to satisfy the lockref code. Using Linus' simple testcase from http://article.gmane.org/gmane.linux.file-systems/77466 on a dual core system with an in-development MIPS64 CPU running on FPGA I see around an 8% gain: Pre-patch: Total loops: 252698 Total loops: 251482 Total loops: 250806 Total loops: 252885 Total loops: 251666 Post-patch: Total loops: 273728 Total loops: 269932 Total loops: 269341 Total loops: 275004 Total loops: 270208 [ralf@linux-mips.org: Fixed conflict.] Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: Maciej W. Rozycki <macro@codesourcery.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/10810/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -3,6 +3,7 @@ config MIPS
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default y
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select ARCH_MIGHT_HAVE_PC_PARPORT
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select ARCH_MIGHT_HAVE_PC_SERIO
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select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
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select HAVE_CONTEXT_TRACKING
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select HAVE_GENERIC_DMA_COHERENT
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select HAVE_IDE
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@ -42,6 +42,11 @@ static inline int arch_spin_is_locked(arch_spinlock_t *lock)
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return ((counters >> 16) ^ counters) & 0xffff;
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}
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static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
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{
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return lock.h.serving_now == lock.h.ticket;
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}
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#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
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#define arch_spin_unlock_wait(x) \
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while (arch_spin_is_locked(x)) { cpu_relax(); }
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