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KVM: x86: Mark bit 7 in long-mode PDPTE according to 1GB pages support
In long-mode, bit 7 in the PDPTE is not reserved only if 1GB pages are supported by the CPU. Currently the bit is considered by KVM as always reserved. Signed-off-by: Nadav Amit <namit@cs.technion.ac.il> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -88,4 +88,11 @@ static inline bool guest_cpuid_has_x2apic(struct kvm_vcpu *vcpu)
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return best && (best->ecx & bit(X86_FEATURE_X2APIC));
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}
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static inline bool guest_cpuid_has_gbpages(struct kvm_vcpu *vcpu)
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{
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struct kvm_cpuid_entry2 *best;
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best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
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return best && (best->edx & bit(X86_FEATURE_GBPAGES));
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}
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#endif
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@ -22,6 +22,7 @@
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#include "mmu.h"
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#include "x86.h"
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#include "kvm_cache_regs.h"
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#include "cpuid.h"
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#include <linux/kvm_host.h>
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#include <linux/types.h>
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@ -3516,11 +3517,14 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
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{
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int maxphyaddr = cpuid_maxphyaddr(vcpu);
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u64 exb_bit_rsvd = 0;
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u64 gbpages_bit_rsvd = 0;
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context->bad_mt_xwr = 0;
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if (!context->nx)
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exb_bit_rsvd = rsvd_bits(63, 63);
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if (!guest_cpuid_has_gbpages(vcpu))
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gbpages_bit_rsvd = rsvd_bits(7, 7);
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switch (context->root_level) {
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case PT32_ROOT_LEVEL:
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/* no rsvd bits for 2 level 4K page table entries */
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@ -3557,14 +3561,14 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
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context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
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rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 7);
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context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
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rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 7);
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gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51);
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context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
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rsvd_bits(maxphyaddr, 51);
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context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
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rsvd_bits(maxphyaddr, 51);
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context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
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context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
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rsvd_bits(maxphyaddr, 51) |
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gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
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rsvd_bits(13, 29);
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context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
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rsvd_bits(maxphyaddr, 51) |
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