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net: mvpp2: adapt the mvpp2_rxq_*_pool_set functions to PPv2.2
The MVPP2_RXQ_CONFIG_REG register has a slightly different layout between PPv2.1 and PPv2.2, so this commit adapts the functions modifying this register to accommodate for both the PPv2.1 and PPv2.2 cases. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -50,9 +50,11 @@
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#define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
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#define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
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#define MVPP2_RXQ_POOL_SHORT_OFFS 20
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#define MVPP2_RXQ_POOL_SHORT_MASK 0x700000
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#define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
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#define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
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#define MVPP2_RXQ_POOL_LONG_OFFS 24
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#define MVPP2_RXQ_POOL_LONG_MASK 0x7000000
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#define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
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#define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
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#define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
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#define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
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#define MVPP2_RXQ_DISABLE_MASK BIT(31)
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@ -3718,17 +3720,20 @@ static int mvpp2_bm_init(struct platform_device *pdev, struct mvpp2 *priv)
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static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
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int lrxq, int long_pool)
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{
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u32 val;
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u32 val, mask;
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int prxq;
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/* Get queue physical ID */
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prxq = port->rxqs[lrxq]->id;
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val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
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val &= ~MVPP2_RXQ_POOL_LONG_MASK;
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val |= ((long_pool << MVPP2_RXQ_POOL_LONG_OFFS) &
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MVPP2_RXQ_POOL_LONG_MASK);
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if (port->priv->hw_version == MVPP21)
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mask = MVPP21_RXQ_POOL_LONG_MASK;
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else
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mask = MVPP22_RXQ_POOL_LONG_MASK;
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val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
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val &= ~mask;
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val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
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mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
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}
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@ -3736,17 +3741,20 @@ static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
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static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port,
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int lrxq, int short_pool)
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{
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u32 val;
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u32 val, mask;
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int prxq;
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/* Get queue physical ID */
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prxq = port->rxqs[lrxq]->id;
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val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
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val &= ~MVPP2_RXQ_POOL_SHORT_MASK;
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val |= ((short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) &
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MVPP2_RXQ_POOL_SHORT_MASK);
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if (port->priv->hw_version == MVPP21)
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mask = MVPP21_RXQ_POOL_SHORT_MASK;
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else
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mask = MVPP22_RXQ_POOL_SHORT_MASK;
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val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
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val &= ~mask;
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val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask;
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mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
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}
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