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drm/vmwgfx: Add support for UA view commands
Virtual device now support new commands to manage unordered access views. Allow them as part of user-space command buffer. This involves adding UA view cotable, binding tracker info, new view type and command verifier functions. v2: fix comment typo v3: style fixes (don't use deprecated PTR_RET) Signed-off-by: Deepak Rawat <drawat.floss@gmail.com> Signed-off-by: Neha Bhende <bhenden@vmware.com> Reviewed-by: Thomas Hellström (VMware) <thomas_os@shipmail.org> Reviewed-by: Roland Scheidegger <sroland@vmware.com> Signed-off-by: Roland Scheidegger <sroland@vmware.com>
This commit is contained in:
Deepak Rawat
Roland Scheidegger
parent
d2e90ab374
commit
5e8ec0d919
@ -59,7 +59,9 @@
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#define VMW_BINDING_PS_BIT 1
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#define VMW_BINDING_SO_BIT 2
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#define VMW_BINDING_VB_BIT 3
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#define VMW_BINDING_NUM_BITS 4
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#define VMW_BINDING_UAV_BIT 4
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#define VMW_BINDING_CS_UAV_BIT 5
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#define VMW_BINDING_NUM_BITS 6
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#define VMW_BINDING_PS_SR_BIT 0
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@ -75,6 +77,7 @@
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* @vertex_buffers: Vertex buffer bindings.
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* @index_buffer: Index buffer binding.
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* @per_shader: Per shader-type bindings.
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* @ua_views: UAV bindings.
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* @dirty: Bitmap tracking per binding-type changes that have not yet
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* been emitted to the device.
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* @dirty_vb: Bitmap tracking individual vertex buffer binding changes that
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@ -99,6 +102,7 @@ struct vmw_ctx_binding_state {
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struct vmw_ctx_bindinfo_vb vertex_buffers[SVGA3D_DX_MAX_VERTEXBUFFERS];
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struct vmw_ctx_bindinfo_ib index_buffer;
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struct vmw_dx_shader_bindings per_shader[SVGA3D_NUM_SHADERTYPE];
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struct vmw_ctx_bindinfo_uav ua_views[VMW_MAX_UAV_BIND_TYPE];
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unsigned long dirty;
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DECLARE_BITMAP(dirty_vb, SVGA3D_DX_MAX_VERTEXBUFFERS);
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@ -121,6 +125,9 @@ static int vmw_binding_scrub_dx_shader(struct vmw_ctx_bindinfo *bi,
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bool rebind);
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static int vmw_binding_scrub_ib(struct vmw_ctx_bindinfo *bi, bool rebind);
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static int vmw_binding_scrub_vb(struct vmw_ctx_bindinfo *bi, bool rebind);
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static int vmw_binding_scrub_uav(struct vmw_ctx_bindinfo *bi, bool rebind);
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static int vmw_binding_scrub_cs_uav(struct vmw_ctx_bindinfo *bi, bool rebind);
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static void vmw_binding_build_asserts(void) __attribute__ ((unused));
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typedef int (*vmw_scrub_func)(struct vmw_ctx_bindinfo *, bool);
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@ -189,6 +196,12 @@ static const size_t vmw_binding_vb_offsets[] = {
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static const size_t vmw_binding_ib_offsets[] = {
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offsetof(struct vmw_ctx_binding_state, index_buffer),
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};
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static const size_t vmw_binding_uav_offsets[] = {
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offsetof(struct vmw_ctx_binding_state, ua_views[0].views),
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};
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static const size_t vmw_binding_cs_uav_offsets[] = {
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offsetof(struct vmw_ctx_binding_state, ua_views[1].views),
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};
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static const struct vmw_binding_info vmw_binding_infos[] = {
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[vmw_ctx_binding_shader] = {
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@ -235,6 +248,14 @@ static const struct vmw_binding_info vmw_binding_infos[] = {
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.size = sizeof(struct vmw_ctx_bindinfo_ib),
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.offsets = vmw_binding_ib_offsets,
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.scrub_func = vmw_binding_scrub_ib},
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[vmw_ctx_binding_uav] = {
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.size = sizeof(struct vmw_ctx_bindinfo_view),
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.offsets = vmw_binding_uav_offsets,
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.scrub_func = vmw_binding_scrub_uav},
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[vmw_ctx_binding_cs_uav] = {
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.size = sizeof(struct vmw_ctx_bindinfo_view),
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.offsets = vmw_binding_cs_uav_offsets,
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.scrub_func = vmw_binding_scrub_cs_uav},
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};
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/**
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@ -320,6 +341,18 @@ void vmw_binding_add(struct vmw_ctx_binding_state *cbs,
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INIT_LIST_HEAD(&loc->res_list);
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}
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/**
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* vmw_binding_add_uav_index - Add UAV index for tracking.
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* @cbs: Pointer to the context binding state tracker.
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* @slot: UAV type to which bind this index.
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* @index: The splice index to track.
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*/
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void vmw_binding_add_uav_index(struct vmw_ctx_binding_state *cbs, uint32 slot,
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uint32 index)
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{
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cbs->ua_views[slot].index = index;
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}
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/**
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* vmw_binding_transfer: Transfer a context binding tracking entry.
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*
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@ -459,6 +492,10 @@ void vmw_binding_state_commit(struct vmw_ctx_binding_state *to,
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vmw_binding_transfer(to, from, entry);
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vmw_binding_drop(entry);
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}
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/* Also transfer uav splice indices */
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to->ua_views[0].index = from->ua_views[0].index;
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to->ua_views[1].index = from->ua_views[1].index;
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}
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/**
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@ -1014,6 +1051,66 @@ static int vmw_emit_set_vb(struct vmw_ctx_binding_state *cbs)
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return 0;
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}
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static int vmw_emit_set_uav(struct vmw_ctx_binding_state *cbs)
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{
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const struct vmw_ctx_bindinfo *loc = &cbs->ua_views[0].views[0].bi;
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struct {
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SVGA3dCmdHeader header;
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SVGA3dCmdDXSetUAViews body;
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} *cmd;
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size_t cmd_size, view_id_size;
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const struct vmw_resource *ctx = vmw_cbs_context(cbs);
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vmw_collect_view_ids(cbs, loc, SVGA3D_MAX_UAVIEWS);
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view_id_size = cbs->bind_cmd_count*sizeof(uint32);
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cmd_size = sizeof(*cmd) + view_id_size;
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cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);
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if (!cmd)
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return -ENOMEM;
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cmd->header.id = SVGA_3D_CMD_DX_SET_UA_VIEWS;
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cmd->header.size = sizeof(cmd->body) + view_id_size;
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/* Splice index is specified user-space */
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cmd->body.uavSpliceIndex = cbs->ua_views[0].index;
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memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);
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vmw_fifo_commit(ctx->dev_priv, cmd_size);
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return 0;
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}
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static int vmw_emit_set_cs_uav(struct vmw_ctx_binding_state *cbs)
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{
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const struct vmw_ctx_bindinfo *loc = &cbs->ua_views[1].views[0].bi;
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struct {
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SVGA3dCmdHeader header;
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SVGA3dCmdDXSetCSUAViews body;
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} *cmd;
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size_t cmd_size, view_id_size;
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const struct vmw_resource *ctx = vmw_cbs_context(cbs);
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vmw_collect_view_ids(cbs, loc, SVGA3D_MAX_UAVIEWS);
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view_id_size = cbs->bind_cmd_count*sizeof(uint32);
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cmd_size = sizeof(*cmd) + view_id_size;
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cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);
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if (!cmd)
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return -ENOMEM;
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cmd->header.id = SVGA_3D_CMD_DX_SET_CS_UA_VIEWS;
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cmd->header.size = sizeof(cmd->body) + view_id_size;
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/* Start index is specified user-space */
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cmd->body.startIndex = cbs->ua_views[1].index;
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memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);
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vmw_fifo_commit(ctx->dev_priv, cmd_size);
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return 0;
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}
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/**
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* vmw_binding_emit_dirty - Issue delayed binding commands
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*
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@ -1045,6 +1142,12 @@ static int vmw_binding_emit_dirty(struct vmw_ctx_binding_state *cbs)
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case VMW_BINDING_VB_BIT:
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ret = vmw_emit_set_vb(cbs);
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break;
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case VMW_BINDING_UAV_BIT:
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ret = vmw_emit_set_uav(cbs);
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break;
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case VMW_BINDING_CS_UAV_BIT:
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ret = vmw_emit_set_cs_uav(cbs);
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break;
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default:
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BUG();
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}
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@ -1171,6 +1274,22 @@ static int vmw_binding_scrub_ib(struct vmw_ctx_bindinfo *bi, bool rebind)
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return 0;
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}
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static int vmw_binding_scrub_uav(struct vmw_ctx_bindinfo *bi, bool rebind)
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{
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struct vmw_ctx_binding_state *cbs = vmw_context_binding_state(bi->ctx);
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__set_bit(VMW_BINDING_UAV_BIT, &cbs->dirty);
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return 0;
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}
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static int vmw_binding_scrub_cs_uav(struct vmw_ctx_bindinfo *bi, bool rebind)
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{
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struct vmw_ctx_binding_state *cbs = vmw_context_binding_state(bi->ctx);
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__set_bit(VMW_BINDING_CS_UAV_BIT, &cbs->dirty);
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return 0;
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}
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/**
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* vmw_binding_state_alloc - Allocate a struct vmw_ctx_binding_state with
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* memory accounting.
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@ -1257,8 +1376,8 @@ void vmw_binding_state_reset(struct vmw_ctx_binding_state *cbs)
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* Each time a resource is put on the validation list as the result of a
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* context binding referencing it, we need to determine whether that resource
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* will be dirtied (written to by the GPU) as a result of the corresponding
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* GPU operation. Currently rendertarget-, depth-stencil-, and
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* stream-output-target bindings are capable of dirtying its resource.
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* GPU operation. Currently rendertarget-, depth-stencil-, stream-output-target
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* and unordered access view bindings are capable of dirtying its resource.
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*
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* Return: Whether the binding type dirties the resource its binding points to.
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*/
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@ -1269,10 +1388,12 @@ u32 vmw_binding_dirtying(enum vmw_ctx_binding_type binding_type)
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[vmw_ctx_binding_dx_rt] = VMW_RES_DIRTY_SET,
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[vmw_ctx_binding_ds] = VMW_RES_DIRTY_SET,
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[vmw_ctx_binding_so] = VMW_RES_DIRTY_SET,
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[vmw_ctx_binding_uav] = VMW_RES_DIRTY_SET,
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[vmw_ctx_binding_cs_uav] = VMW_RES_DIRTY_SET,
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};
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/* Review this function as new bindings are added. */
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BUILD_BUG_ON(vmw_ctx_binding_max != 11);
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BUILD_BUG_ON(vmw_ctx_binding_max != 13);
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return is_binding_dirtying[binding_type];
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}
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@ -33,6 +33,8 @@
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#define VMW_MAX_VIEW_BINDINGS 128
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#define VMW_MAX_UAV_BIND_TYPE 2
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struct vmw_private;
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struct vmw_ctx_binding_state;
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@ -51,6 +53,8 @@ enum vmw_ctx_binding_type {
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vmw_ctx_binding_so,
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vmw_ctx_binding_vb,
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vmw_ctx_binding_ib,
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vmw_ctx_binding_uav,
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vmw_ctx_binding_cs_uav,
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vmw_ctx_binding_max
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};
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@ -189,9 +193,21 @@ struct vmw_dx_shader_bindings {
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unsigned long dirty;
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};
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/**
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* struct vmw_ctx_bindinfo_uav - UAV context binding state.
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* @views: UAV view bindings.
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* @splice_index: The device splice index set by user-space.
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*/
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struct vmw_ctx_bindinfo_uav {
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struct vmw_ctx_bindinfo_view views[SVGA3D_MAX_UAVIEWS];
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uint32 index;
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};
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extern void vmw_binding_add(struct vmw_ctx_binding_state *cbs,
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const struct vmw_ctx_bindinfo *ci,
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u32 shader_slot, u32 slot);
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extern void vmw_binding_add_uav_index(struct vmw_ctx_binding_state *cbs,
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uint32 slot, uint32 splice_index);
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extern void
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vmw_binding_state_commit(struct vmw_ctx_binding_state *to,
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struct vmw_ctx_binding_state *from);
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@ -36,7 +36,7 @@ struct vmw_user_context {
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struct vmw_resource res;
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struct vmw_ctx_binding_state *cbs;
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struct vmw_cmdbuf_res_manager *man;
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struct vmw_resource *cotables[SVGA_COTABLE_DX10_MAX];
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struct vmw_resource *cotables[SVGA_COTABLE_MAX];
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spinlock_t cotable_lock;
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struct vmw_buffer_object *dx_query_mob;
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};
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@ -116,12 +116,15 @@ static const struct vmw_res_func vmw_dx_context_func = {
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* Context management:
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*/
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static void vmw_context_cotables_unref(struct vmw_user_context *uctx)
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static void vmw_context_cotables_unref(struct vmw_private *dev_priv,
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struct vmw_user_context *uctx)
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{
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struct vmw_resource *res;
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int i;
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u32 cotable_max = has_sm5_context(dev_priv) ?
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SVGA_COTABLE_MAX : SVGA_COTABLE_DX10_MAX;
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for (i = 0; i < SVGA_COTABLE_DX10_MAX; ++i) {
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for (i = 0; i < cotable_max; ++i) {
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spin_lock(&uctx->cotable_lock);
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res = uctx->cotables[i];
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uctx->cotables[i] = NULL;
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@ -155,7 +158,7 @@ static void vmw_hw_context_destroy(struct vmw_resource *res)
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!dev_priv->query_cid_valid)
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__vmw_execbuf_release_pinned_bo(dev_priv, NULL);
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mutex_unlock(&dev_priv->cmdbuf_mutex);
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vmw_context_cotables_unref(uctx);
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vmw_context_cotables_unref(dev_priv, uctx);
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return;
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}
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@ -208,7 +211,9 @@ static int vmw_gb_context_init(struct vmw_private *dev_priv,
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spin_lock_init(&uctx->cotable_lock);
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if (dx) {
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for (i = 0; i < SVGA_COTABLE_DX10_MAX; ++i) {
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u32 cotable_max = has_sm5_context(dev_priv) ?
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SVGA_COTABLE_MAX : SVGA_COTABLE_DX10_MAX;
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for (i = 0; i < cotable_max; ++i) {
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uctx->cotables[i] = vmw_cotable_alloc(dev_priv,
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&uctx->res, i);
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if (IS_ERR(uctx->cotables[i])) {
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@ -222,7 +227,7 @@ static int vmw_gb_context_init(struct vmw_private *dev_priv,
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return 0;
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out_cotables:
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vmw_context_cotables_unref(uctx);
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vmw_context_cotables_unref(dev_priv, uctx);
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out_err:
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if (res_free)
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res_free(res);
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@ -545,10 +550,12 @@ void vmw_dx_context_scrub_cotables(struct vmw_resource *ctx,
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{
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struct vmw_user_context *uctx =
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container_of(ctx, struct vmw_user_context, res);
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u32 cotable_max = has_sm5_context(ctx->dev_priv) ?
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SVGA_COTABLE_MAX : SVGA_COTABLE_DX10_MAX;
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int i;
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vmw_binding_state_scrub(uctx->cbs);
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for (i = 0; i < SVGA_COTABLE_DX10_MAX; ++i) {
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for (i = 0; i < cotable_max; ++i) {
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struct vmw_resource *res;
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/* Avoid racing with ongoing cotable destruction. */
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@ -839,7 +846,10 @@ struct vmw_cmdbuf_res_manager *vmw_context_res_man(struct vmw_resource *ctx)
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struct vmw_resource *vmw_context_cotable(struct vmw_resource *ctx,
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SVGACOTableType cotable_type)
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{
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if (cotable_type >= SVGA_COTABLE_DX10_MAX)
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u32 cotable_max = has_sm5_context(ctx->dev_priv) ?
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SVGA_COTABLE_MAX : SVGA_COTABLE_DX10_MAX;
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if (cotable_type >= cotable_max)
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return ERR_PTR(-EINVAL);
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return container_of(ctx, struct vmw_user_context, res)->
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@ -82,7 +82,8 @@ static const struct vmw_cotable_info co_info[] = {
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{1, sizeof(SVGACOTableDXSamplerEntry), NULL},
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{1, sizeof(SVGACOTableDXStreamOutputEntry), NULL},
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{1, sizeof(SVGACOTableDXQueryEntry), NULL},
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{1, sizeof(SVGACOTableDXShaderEntry), &vmw_dx_shader_cotable_list_scrub}
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{1, sizeof(SVGACOTableDXShaderEntry), &vmw_dx_shader_cotable_list_scrub},
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{1, sizeof(SVGACOTableDXUAViewEntry), &vmw_view_cotable_list_destroy}
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};
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/*
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@ -102,6 +103,7 @@ const SVGACOTableType vmw_cotable_scrub_order[] = {
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SVGA_COTABLE_SAMPLER,
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SVGA_COTABLE_STREAMOUTPUT,
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SVGA_COTABLE_DXQUERY,
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SVGA_COTABLE_UAVIEW,
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};
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static int vmw_cotable_bind(struct vmw_resource *res,
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@ -459,11 +459,13 @@ static int vmw_resource_context_res_add(struct vmw_private *dev_priv,
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int ret = 0;
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struct vmw_resource *res;
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u32 i;
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u32 cotable_max = has_sm5_context(ctx->dev_priv) ?
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SVGA_COTABLE_MAX : SVGA_COTABLE_DX10_MAX;
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/* Add all cotables to the validation list. */
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if (has_sm4_context(dev_priv) &&
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vmw_res_type(ctx) == vmw_res_dx_context) {
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for (i = 0; i < SVGA_COTABLE_DX10_MAX; ++i) {
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for (i = 0; i < cotable_max; ++i) {
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res = vmw_context_cotable(ctx, i);
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if (IS_ERR(res))
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continue;
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@ -2814,6 +2816,128 @@ static int vmw_cmd_intra_surface_copy(struct vmw_private *dev_priv,
|
||||
&cmd->body.surface.sid, NULL);
|
||||
}
|
||||
|
||||
static int vmw_cmd_sm5_view_define(struct vmw_private *dev_priv,
|
||||
struct vmw_sw_context *sw_context,
|
||||
SVGA3dCmdHeader *header)
|
||||
{
|
||||
if (!has_sm5_context(dev_priv))
|
||||
return -EINVAL;
|
||||
|
||||
return vmw_cmd_dx_view_define(dev_priv, sw_context, header);
|
||||
}
|
||||
|
||||
static int vmw_cmd_sm5_view_remove(struct vmw_private *dev_priv,
|
||||
struct vmw_sw_context *sw_context,
|
||||
SVGA3dCmdHeader *header)
|
||||
{
|
||||
if (!has_sm5_context(dev_priv))
|
||||
return -EINVAL;
|
||||
|
||||
return vmw_cmd_dx_view_remove(dev_priv, sw_context, header);
|
||||
}
|
||||
|
||||
static int vmw_cmd_clear_uav_uint(struct vmw_private *dev_priv,
|
||||
struct vmw_sw_context *sw_context,
|
||||
SVGA3dCmdHeader *header)
|
||||
{
|
||||
struct {
|
||||
SVGA3dCmdHeader header;
|
||||
SVGA3dCmdDXClearUAViewUint body;
|
||||
} *cmd = container_of(header, typeof(*cmd), header);
|
||||
struct vmw_resource *ret;
|
||||
|
||||
if (!has_sm5_context(dev_priv))
|
||||
return -EINVAL;
|
||||
|
||||
ret = vmw_view_id_val_add(sw_context, vmw_view_ua,
|
||||
cmd->body.uaViewId);
|
||||
|
||||
return PTR_ERR_OR_ZERO(ret);
|
||||
}
|
||||
|
||||
static int vmw_cmd_clear_uav_float(struct vmw_private *dev_priv,
|
||||
struct vmw_sw_context *sw_context,
|
||||
SVGA3dCmdHeader *header)
|
||||
{
|
||||
struct {
|
||||
SVGA3dCmdHeader header;
|
||||
SVGA3dCmdDXClearUAViewFloat body;
|
||||
} *cmd = container_of(header, typeof(*cmd), header);
|
||||
struct vmw_resource *ret;
|
||||
|
||||
if (!has_sm5_context(dev_priv))
|
||||
return -EINVAL;
|
||||
|
||||
ret = vmw_view_id_val_add(sw_context, vmw_view_ua,
|
||||
cmd->body.uaViewId);
|
||||
|
||||
return PTR_ERR_OR_ZERO(ret);
|
||||
}
|
||||
|
||||
static int vmw_cmd_set_uav(struct vmw_private *dev_priv,
|
||||
struct vmw_sw_context *sw_context,
|
||||
SVGA3dCmdHeader *header)
|
||||
{
|
||||
struct {
|
||||
SVGA3dCmdHeader header;
|
||||
SVGA3dCmdDXSetUAViews body;
|
||||
} *cmd = container_of(header, typeof(*cmd), header);
|
||||
u32 num_uav = (cmd->header.size - sizeof(cmd->body)) /
|
||||
sizeof(SVGA3dUAViewId);
|
||||
int ret;
|
||||
|
||||
if (!has_sm5_context(dev_priv))
|
||||
return -EINVAL;
|
||||
|
||||
if (num_uav > SVGA3D_MAX_UAVIEWS) {
|
||||
VMW_DEBUG_USER("Invalid UAV binding.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = vmw_view_bindings_add(sw_context, vmw_view_ua,
|
||||
vmw_ctx_binding_uav, 0, (void *)&cmd[1],
|
||||
num_uav, 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
vmw_binding_add_uav_index(sw_context->dx_ctx_node->staged, 0,
|
||||
cmd->body.uavSpliceIndex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int vmw_cmd_set_cs_uav(struct vmw_private *dev_priv,
|
||||
struct vmw_sw_context *sw_context,
|
||||
SVGA3dCmdHeader *header)
|
||||
{
|
||||
struct {
|
||||
SVGA3dCmdHeader header;
|
||||
SVGA3dCmdDXSetCSUAViews body;
|
||||
} *cmd = container_of(header, typeof(*cmd), header);
|
||||
u32 num_uav = (cmd->header.size - sizeof(cmd->body)) /
|
||||
sizeof(SVGA3dUAViewId);
|
||||
int ret;
|
||||
|
||||
if (!has_sm5_context(dev_priv))
|
||||
return -EINVAL;
|
||||
|
||||
if (num_uav > SVGA3D_MAX_UAVIEWS) {
|
||||
VMW_DEBUG_USER("Invalid UAV binding.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = vmw_view_bindings_add(sw_context, vmw_view_ua,
|
||||
vmw_ctx_binding_cs_uav, 0, (void *)&cmd[1],
|
||||
num_uav, 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
vmw_binding_add_uav_index(sw_context->dx_ctx_node->staged, 1,
|
||||
cmd->body.startIndex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int vmw_cmd_check_not_3d(struct vmw_private *dev_priv,
|
||||
struct vmw_sw_context *sw_context,
|
||||
void *buf, uint32_t *size)
|
||||
@ -3163,6 +3287,24 @@ static const struct vmw_cmd_entry vmw_cmd_entries[SVGA_3D_CMD_MAX] = {
|
||||
true, false, true),
|
||||
VMW_CMD_DEF(SVGA_3D_CMD_INTRA_SURFACE_COPY, &vmw_cmd_intra_surface_copy,
|
||||
true, false, true),
|
||||
|
||||
/*
|
||||
* SM5 commands
|
||||
*/
|
||||
VMW_CMD_DEF(SVGA_3D_CMD_DX_DEFINE_UA_VIEW, &vmw_cmd_sm5_view_define,
|
||||
true, false, true),
|
||||
VMW_CMD_DEF(SVGA_3D_CMD_DX_DESTROY_UA_VIEW, &vmw_cmd_sm5_view_remove,
|
||||
true, false, true),
|
||||
VMW_CMD_DEF(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT, &vmw_cmd_clear_uav_uint,
|
||||
true, false, true),
|
||||
VMW_CMD_DEF(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT,
|
||||
&vmw_cmd_clear_uav_float, true, false, true),
|
||||
VMW_CMD_DEF(SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT, &vmw_cmd_invalid, true,
|
||||
false, true),
|
||||
VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_UA_VIEWS, &vmw_cmd_set_uav, true, false,
|
||||
true),
|
||||
VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_CS_UA_VIEWS, &vmw_cmd_set_cs_uav, true,
|
||||
false, true),
|
||||
};
|
||||
|
||||
bool vmw_cmd_describe(const void *buf, u32 *size, char const **cmd)
|
||||
|
||||
@ -319,7 +319,8 @@ int vmw_view_add(struct vmw_cmdbuf_res_manager *man,
|
||||
static const size_t vmw_view_define_sizes[] = {
|
||||
[vmw_view_sr] = sizeof(SVGA3dCmdDXDefineShaderResourceView),
|
||||
[vmw_view_rt] = sizeof(SVGA3dCmdDXDefineRenderTargetView),
|
||||
[vmw_view_ds] = sizeof(SVGA3dCmdDXDefineDepthStencilView)
|
||||
[vmw_view_ds] = sizeof(SVGA3dCmdDXDefineDepthStencilView),
|
||||
[vmw_view_ua] = sizeof(SVGA3dCmdDXDefineUAView)
|
||||
};
|
||||
|
||||
struct vmw_private *dev_priv = ctx->dev_priv;
|
||||
@ -499,8 +500,8 @@ struct vmw_resource *vmw_view_lookup(struct vmw_cmdbuf_res_manager *man,
|
||||
* Each time a resource is put on the validation list as the result of a
|
||||
* view pointing to it, we need to determine whether that resource will
|
||||
* be dirtied (written to by the GPU) as a result of the corresponding
|
||||
* GPU operation. Currently only rendertarget- and depth-stencil views are
|
||||
* capable of dirtying its resource.
|
||||
* GPU operation. Currently only rendertarget-, depth-stencil and unordered
|
||||
* access views are capable of dirtying its resource.
|
||||
*
|
||||
* Return: Whether the view type of @res dirties the resource it points to.
|
||||
*/
|
||||
@ -509,10 +510,11 @@ u32 vmw_view_dirtying(struct vmw_resource *res)
|
||||
static u32 view_is_dirtying[vmw_view_max] = {
|
||||
[vmw_view_rt] = VMW_RES_DIRTY_SET,
|
||||
[vmw_view_ds] = VMW_RES_DIRTY_SET,
|
||||
[vmw_view_ua] = VMW_RES_DIRTY_SET,
|
||||
};
|
||||
|
||||
/* Update this function as we add more view types */
|
||||
BUILD_BUG_ON(vmw_view_max != 3);
|
||||
BUILD_BUG_ON(vmw_view_max != 4);
|
||||
return view_is_dirtying[vmw_view(res)->view_type];
|
||||
}
|
||||
|
||||
@ -520,12 +522,14 @@ const u32 vmw_view_destroy_cmds[] = {
|
||||
[vmw_view_sr] = SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW,
|
||||
[vmw_view_rt] = SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW,
|
||||
[vmw_view_ds] = SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW,
|
||||
[vmw_view_ua] = SVGA_3D_CMD_DX_DESTROY_UA_VIEW,
|
||||
};
|
||||
|
||||
const SVGACOTableType vmw_view_cotables[] = {
|
||||
[vmw_view_sr] = SVGA_COTABLE_SRVIEW,
|
||||
[vmw_view_rt] = SVGA_COTABLE_RTVIEW,
|
||||
[vmw_view_ds] = SVGA_COTABLE_DSVIEW,
|
||||
[vmw_view_ua] = SVGA_COTABLE_UAVIEW,
|
||||
};
|
||||
|
||||
const SVGACOTableType vmw_so_cotables[] = {
|
||||
|
||||
@ -30,6 +30,7 @@ enum vmw_view_type {
|
||||
vmw_view_sr,
|
||||
vmw_view_rt,
|
||||
vmw_view_ds,
|
||||
vmw_view_ua,
|
||||
vmw_view_max,
|
||||
};
|
||||
|
||||
@ -61,6 +62,7 @@ union vmw_view_destroy {
|
||||
struct SVGA3dCmdDXDestroyRenderTargetView rtv;
|
||||
struct SVGA3dCmdDXDestroyShaderResourceView srv;
|
||||
struct SVGA3dCmdDXDestroyDepthStencilView dsv;
|
||||
struct SVGA3dCmdDXDestroyUAView uav;
|
||||
u32 view_id;
|
||||
};
|
||||
|
||||
@ -87,6 +89,10 @@ static inline enum vmw_view_type vmw_view_cmd_to_type(u32 id)
|
||||
{
|
||||
u32 tmp = (id - SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW) / 2;
|
||||
|
||||
if (id == SVGA_3D_CMD_DX_DEFINE_UA_VIEW ||
|
||||
id == SVGA_3D_CMD_DX_DESTROY_UA_VIEW)
|
||||
return vmw_view_ua;
|
||||
|
||||
if (tmp > (u32)vmw_view_max)
|
||||
return vmw_view_max;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user